DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsutsumi (2003/0230769).
[claim 1] A semiconductor device (fig. 10, 11, 22, 23, fig. 10 shows a plural power cell Cp2 [0117], fig. 11 shows an plural power cell CP2 [0117] among single power supply cells Un1 [0119], fig. 22 shows a cell array with Cp2 and Un1, fig. 23 shows a larger cell array with CP2, note that the plural power cell Cp2 comprises 4 transistors a p-type at the top, followed by n-type, n-type, and a p-type at the bottom of CP2, each transistor is interpreted as being a cell) comprising: a first cell row (leftmost column of cells, fig. 22 see annotated figure below), wherein in the first cell row includes a first plurality of cells c (fig. 22, each of the individual transistors may constitute a cell); a first power rail (see annotated drawing below, fig. 2a) extending from a first side of the first cell row, wherein the first power rail connects to a first group of the first plurality of cells comprising a first cell and a second cell (two of the transistors in the upper half of CP2 fig. 22 adjacent the first power rail); and a second power rail (see annotated drawing below, fig. 2a) extending from a second side of the first cell row, wherein the second power rail connects to a second group of the first plurality of cells comprising a third cell and fourth cell (two of the transistors in the bottom half of CP2 fig. 22 adjacent the second power rail).
PNG
media_image1.png
724
574
media_image1.png
Greyscale
[claim 2] The semiconductor device of claim 1, further comprising: an open space between the first power rail and the second power rail, wherein the open space is used for signal routing (e.g. the space between the first and second power rail has a gate signal line in the annotated drawing above, see also fig. 10 which labels the gate3).
[claim 3] The semiconductor device of claim 1, wherein the first plurality of cells are standard cells [Abstract].
[claim 4] The semiconductor device of claim 1, wherein the first plurality of cells are standard cells and non-standard cells (Whether a particular cell block is standard vs non-standard is merely a user defined standard. Thus, the structure of fig. 22, can be defined to be have standard and non-standard cells by interpreting CP2 as standard and Un1 as non-standard according a possible user interpretation).
[claim 5] The semiconductor device of claim 1, further comprising: a second cell row adjacent to the first cell row, wherein in the second cell row includes a second plurality of cells (see annotated figure above), and wherein a first group of the second plurality of cells connects to the first power rail (see annotated fig. 2).
[claim 6] The semiconductor device of claim 5, wherein the first group of the second plurality of cells has contacts (e.g. through common rail line 502 in the first and second cell rows, as labeled in fig. 11, see also fig. 22 annotated) that extend from the second cell row to the first cell row and connect to the first power rail.
[claim 7] The semiconductor device of claim 5, further comprising: a third power rail (see annotated figure 22 above) extending from a first side of the second cell row, wherein the third power rail connects to a second group of the second plurality of cells (see annotated figure 22 above).
[claim 8] The semiconductor device of claim 5, further comprising: A fourth power rail (see annotated figure 22 above) extending from a second side of the second cell row, wherein the fourth power rail connects to a third group of the second plurality of cells (see annotated figure 22 above).
[claim 9] A semiconductor device (fig. 10, 11, 22, 23, fig. 10 shows a plural power cell Cp2 [0117], fig. 11 shows an plural power cell CP2 [0117] among single power supply cells Un1 [0119], fig. 22 shows a cell array with Cp2 and Un1, note that the plural power cell Cp2 comprises 4 transistors a p-type at the top, followed by n-type, n-type, and a p-type at the bottom of CP2, each transistor is interpreted as being a cell) comprising: a plurality of cell rows (see annotated fig. 22 above); a first power rail (see annotated fig. 22 above) extending from a first side of the semiconductor device across a first cell row of the plurality of cell rows; and wherein the first power rail connects to at two cells in the first cell row (two of the transistors in the upper half of CP2 fig. 22 adjacent the first power rail, see annotated fig. 22 above) and to two cells in a second cell row (two of the transistors in the upper half of CP2 fig. 22 adjacent the first power rail through common rail line 502 in the first and second cell rows, as labeled in fig. 11, see also fig. 22 annotated) of the of the plurality of cell rows.
[claim 10] The semiconductor device of claim 9, further comprising: a second power rail (see annotated fig. 22 above, note that the second power rail only refers to the portion extending 90% of the extension from the common rail) extending from a first side of the semiconductor device across the second cell row of the plurality of cell rows; and wherein the second power rail connects to at least one cell in the second cell row of the plurality of cell rows.
[claim 11] The semiconductor device of claim 10, wherein the first power rail has a first length from the first side and wherein the second power rail has a second length from the first side, and wherein the first length is larger than the second length (the first power rail includes the entire portion of the extension from the common power rail while the second power rail only includes the 90% of the extension from the common power rail 502 as labelled in fig. 11, see also annotated fig. 22 above).
[claim 12] The semiconductor device of claim 10, wherein the first power rail and the second power rail are connected to form a single power rail (see annotated fig. 22 above).
[claim 13] The semiconductor device of claim 10, wherein an open space is between the first power rail and the second power rail (e.g. through common rail line 502 in the first and second cell rows, as labeled in fig. 11, see also fig. 22 annotated) .
[claim 14] The semiconductor device of claim 9, wherein each cell row of the plurality of cell rows includes a plurality of cells and wherein the plurality of cells are selected from the group consisting of standard cells and non-standard cells (Whether a particular cell block is standard vs non-standard is merely a user defined standard. Thus, the structure of fig. 22, can be defined to be have standard and non-standard cells by interpreting CP2 as standard and Un1 as non-standard according a possible user interpretation see also [Abstract]).
[claim 15] The semiconductor device of claim 10, further comprising: a power tap (the common rail 502 as labelled in fig. 11, see also annotated fig. 22 above) connected to the first power rail and the second power rail, wherein the power tap is inside a first standard cell in the first cell row and wherein the first standard cell is on the first side of the semiconductor device (see annotated fig. 22 above).
[claim 16] The semiconductor device of claim 10, further comprising: a power tap (the common rail 502 as labelled in fig. 11, see also annotated fig. 22 above) connected to the first power rail and the second power rail, wherein the power tap is between a first standard cell in the first cell row and the first side of the semiconductor device (see annotated fig. 22 above).
[claim 17] A semiconductor device (fig. 10, 11, 22, 23, fig. 10 shows a plural power cell Cp2 [0117], fig. 11 shows an plural power cell CP2 [0117] among single power supply cells Un1 [0119], fig. 22 shows a cell array with Cp2 and Un1, note that the plural power cell Cp2 comprises 4 transistors a p-type at the top, followed by n-type, n-type, and a p-type at the bottom of CP2, each transistor is interpreted as being a cell) comprising: a plurality of transistors (transistors in first and second cell rows, see annotated fig. 22 above); and a power rail (first and second power rail as shown in annotated fig. 22 as well as common rail 502 as labeled in fig. 11) connected to the plurality of transistors, wherein a first portion of the power rail has a first length, and a second portion of the power rail has a second length and connects to a first cell and a second cell (each portion of the power rail directly contacts individual transistor cells), and wherein the first length is greater than the second length (the first portion may interpreted as the whole of the first power rail while the second portion is only 90% of the extent of the third power rail in annotated fig. 22 above).
[claim 18] The semiconductor device of claim 17, wherein the plurality of transistors form a plurality of cells and wherein the plurality of cells form a plurality of cell rows (see annotated fig. 22 above).
[claim 19] The semiconductor device of claim 18, where the plurality of cells are selected from the group consisting of standard cells and non-standard cells (Whether a particular cell block is standard vs non-standard is merely a user defined standard. Thus, the structure of fig. 22, can be defined to be have standard and non-standard cells by interpreting CP2 as standard and Un1 as non-standard according a possible user interpretation see also [Abstract]).
[claim 20] The semiconductor device of claim 17, wherein the first portion of the power rail and the second portion of the power rail are connected (through the common line 502 as labeled in fig. 11,see also annotated fig. 22 above).
Response to Arguments
Applicant's arguments filed 3-2-2026 have been fully considered but they are not persuasive. Applicant argues that the prior art does not teach that the power rail connects to two cells (e.g. a first and second cell). While superficially this may appear true in context of claims 1 and 9, further consideration reveals the term “connect” does not require a direct and immediate connection. A power rail indirectly connects to multiple transistor cells in the cell row when the gate reaches sufficient threshold voltage to form an inversion layer in the channel. An amendment stating that each of the first and second cell or each of the two cells is directly connected to the power rail would overcome this interpretation. With regard to claim 17 the power rail in different portions directly contacts the transistors in tow separate rows and thus it is unclear how this amendment overcomes the pending rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMAR MOVVA whose telephone number is (571)272-9009. The examiner can normally be reached Monday-Friday 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AMAR MOVVA/Primary Examiner, Art Unit 2898
Prosecution Insights