Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed 06 October 2025 has been entered. Claims 1-4 and 6-21 remain pending in the application. Claim 5 has been canceled.
Response to Arguments
Claim Rejections – 35 USC § 103
Applicant’s arguments have been fully considered and are persuasive.
Applicant amended independent claim 1 (and similarly claims 20 and 21) to recite the limitations of claim 5 which were previous indicated as reciting allowable subject matter. Therefore claims 1, 20, and 21, and any claims which depend therefrom, are allowable over the prior art. The rejections are withdrawn.
Claim Rejections – 35 USC § 101
Applicant’s arguments have been fully considered but are not persuasive.
Applicant argues under Step 2A Prong 2 that the abstract idea is integrated into a practical application. Specifically, Applicant argues the remainder estimate circuitry is configured to enable parallel computations which provide a solution to a technical problem of improving the efficiency of the square root calculation.
Examiner respectfully disagrees. As noted in the previous grounds of rejection, the claims are directed to the abstract idea of mathematical concepts. Claim 1 recites an apparatus comprising circuitry configured to perform a square root calculation via digit recurrence algorithm (see equations (14)-(19), Specification pg. 31, and equations (20)-(26), Specification pg. 33-36). According to MPEP 2106.05(a), “the judicial exception alone cannot provide the improvement. The improvement can be provided by one or more additional elements.” However, the various circuitry recited in the claim are described at a high level of generality and amount to no more than mere instructions to apply the exception in hardware. As such, the recited circuitry does not constitute elements sufficient to integrate the abstract idea into a practical application nor amount to significantly more, and the abstract idea alone cannot provide the technical improvement. Therefore, the claim is not patent eligible.
The Applicant further argues their reasoning is consistent with ex parte Desjardins et al (Appeal 2024-000567).
Examiner respectfully disagrees. The claims of the instant application more closely resemble the claims at issue in Gottschalk v. Benson, 409 U.S. 63, 70, 175 USPQ 673, 676 (1972), not Desjardins.
Applicant amends claim 21 to recite “non-transitory computer-readable storage medium”. This amendment overcomes the grounds of rejection of claim 21 related to the non-statutory embodiments of transitory media. However, the claim limitations of claims 21 are otherwise identical to those recited in claim 1, and claim 21 remains rejected under 35 USC 101 for at least the same reason(s) as noted above with respect to claim 1.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-4 and 6-21 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception without significantly more. The claims are directed to the abstract idea of Mathematical Concepts, i.e. a digital-recurrence algorithm for iteratively calculating a square root.
Regarding claim 1, the first limitation of claim 1 recites a square root processing circuitry to calculate a radix-r square root by performing a plurality of radix-n sub-iterations where n<r. The second limitation recites circuitry to select a root result digit based on a previous remainder estimate. The third limitation recites circuitry to update a remainder value based on the root result digit. The fourth limitation recites remainder estimate circuitry to estimate a portion of the updated remainder value. The fifth limitation recites output signal paths to provide updated remainder and updated remainder estimate to a subsequent sub-iteration. The sixth limitation recites generating a remainder estimate in parallel with the remainder update. The seventh limitation recites determining the updated remained estimate via the remainder estimate circuitry based on the previous remainder estimate and the remainder adjustment value in the final radix-n sub-iteration. Under Prong One of Step 2A of the USPTO current eligibility guidance (MPEP 2106), the foregoing limitations fall within the “Mathematical Concepts” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Under Prong Two of Step 2A, this judicial exception is not integrated into a practical application. The limitations of claim 1 recite various circuitry, but these elements are claimed at a high level of generality and amount to no more than mere instructions to apply the exception in hardware. The circuitry is recited to perform the abstract idea, particularly to implement the mathematical equations (14)-(19) (see Specification pg. 31) and their radix-64 implementation, equations (20)-(26) (see Specification pg. 33-36). Accordingly, these elements individually and in combination do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea.
Under Step 2B, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. Thus, the claim does not provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim beyond the judicial exception, and fails to ensure the claim as a whole amounts to significantly more than the judicial exception itself. Accordingly, the claim is not patent eligible under 35 U.S.C. 101.
Claims 2-4 and 6-19 are rejected for at least the reasons set forth with respect to claim 1. Claims 2, 4, 6-7, 10, 12, and 16-17 merely further mathematically limit the abstract idea set forth in claim 1. These indicated claims recite no further additional elements individually or in combination that would require further analysis under Step 2A prong 2 and Step 2B.
Claim 3 recites the additional elements of carry-save adding circuitry and carry-propagate adding circuitry, but these additional elements are recited in a generic manner and only serve to facilitate the mathematical operations of the remainder update and remainder estimate circuitry. For this reason, claim 3 is neither integrated into a practical application nor amounts to significantly more than the abstract idea.
Claim 8 recites the additional limitations of one or more instances of replicated circuitry comprising two or more replicated circuits to generate candidate output values and selection circuitry to select one of a plurality of candidate output values. These additional limitations recite circuitry, but the circuitry is recited at a high level of generality and only serve to facilitate computations of the mathematical algorithm. For this reasons, claim 8 is neither integrated into a practical application nor amounts to significantly more than the abstract idea.
Claim 9 recites the additional limitation of a shared circuit unit handling both positive and negative result digits and outputting a shared candidate output value. This additional limitation recites a shared circuit unit, but circuitry is recited at a high level of generality and only serves to facilitate mathematical computations using a redundant representation of the remainder update value as recited in claim 2. The redundant representation only serves to further mathematically limit the abstract idea. For this reason, claim 9 is neither integrated into a practical application nor amounts to significantly more than the abstract idea.
Claim 11 recites the additional limitation of shared adding circuitry to determine the shared candidate output value. This additional limitation recite a shared adding circuitry, but the circuitry is recited at a high level of generality and only serves to facilitate mathematical computations using the redundant representation. For this reason, claim 11 is neither integrated into a practical application nor amounts to significantly more than the abstract idea.
Claim 13 recites the additional limitation that the remainder update circuitry comprises one of said one or more instances of replicated circuitry. This additional limitation recites an instance of the replicated circuitry recited in claim 8, but this circuitry is recited at a high level of generality and only serves to facilitate mathematical computations of the mathematical algorithm. For this reason, claim 13 is neither integrated into a practical application nor amounts to significantly more than the abstract idea.
Claim 14 recites the additional limitation that the remainder estimate circuitry comprises one of said one or more instances of replicated circuitry. This additional limitation recites an instance of the replicated circuitry recited in claim 8, but this circuitry is recited at a high level of generality and only serves to facilitate mathematical computations of the mathematical algorithm. For this reason, claim 14 is neither integrated into a practical application nor amounts to significantly more than the abstract idea.
Claim 15 recites the additional limitation of one or more instances of replicated circuitry comprises on-the-fly conversion circuitry to generate a partial root value. This additional limitation recites an instance of conversion circuitry, but this circuitry is recited at a high level of generality and only serves to perform the mathematical operation of a conversion from a redundant presentation to a non-redundant representation. For this reason, claim 14 is neither integrated into a practical application nor amounts to significantly more than the abstract idea.
Claim 18 recites the additional limitation of iterative square root processing circuitry configured to provide output values of a final sub-iteration as an input to the same circuitry to perform a subsequent radix-n iteration of the radix-r square root operation. This additional limitation recites processing circuitry, but the circuitry is recited at a high level of generality and only serves to facilitate mathematical computations of the mathematical algorithm. For this reason, claim 18 is neither integrated into a practical application nor amounts to significantly more than the abstract idea.
Claim 19 recites the additional limitation of a pipelined square root processing unit comprising a plurality of pipeline stages in which output signals supply output values of a final sub-iteration of a first pipeline stage to an input of a first sub-iteration of a second pipeline stage. This additional limitation recites pipeline stage processing, but this pipeline processing is recited at a high level of generality and only serves to perform the mathematical computations of the mathematical algorithm. For this reason, claim 18 is neither integrated into a practical application nor amounts to significantly more than the abstract idea.
Regarding claim 20, the first limitation recites performing a radix-r square root operation by performing a plurality of radix-n sub-iterations where n<r. The second limitation recites selecting a result digit based on a previous remainder. The third limitation recites adjusting a previous remainder value based on an adjustment depending on the selected result digit. The third limitation recites generating an updated remainder estimate. The fourth limitation recites supplying the remainder value and remainder estimate as input to a subsequent sub-iteration or a next radix-r iteration. The fifth limitation recites updating the remainder estimate and remainder value in parallel in a final sub-iteration. Under Prong One of Step 2A of the USPTO current eligibility guidance (MPEP 2106), the foregoing limitations fall within the “Mathematical Concepts” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Under Prong Two of Step 2A, this judicial exception is not integrated into a practical application. The claim does not recite any additional elements individually or in combination which would serve to integrate the abstract idea into a practical application and therefore does not impose any meaningful limits on practicing the abstract idea.
Under Step 2B, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. Thus, the claim does not provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim beyond the judicial exception, and fails to ensure the claim as a whole amounts to significantly more than the judicial exception itself. Accordingly, the claim is not patent eligible under 35 U.S.C. 101.
Regarding claim 21, the claim recites limitations which are identical to the limitations recited in claims 1 and 21, and is therefore not patent eligible for at least the same reason(s).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN DAVID WARNER whose telephone number is (703)756-5956. The examiner can normally be reached M-F: 9-5.
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/J.D.W./
Jonathan David WarnerExaminer, Art Unit 2182
(703)756-5956
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182