DETAILED ACTION
This Office Action is in response to the Response to Restriction/Election filed 19 November 2025. Claims 1-20 are pending in this application. Claims 7, 14 are withdrawn from consideration.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species A and Modification C in the reply filed on 19 November 2025 is acknowledged. The traversal is on the ground(s) that there is no examination and search burden to consider all species and modifications. This is not found persuasive because it is unlikely that a single reference would be applicable to each of the different species and modifications. Therefore, each species and modification would likely require a different reference with different search queries required to search for them.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-6, 8-13, 15-16, 18-20 is/are rejected under 35 U.S.C. 102a(2) as being anticipated by Hong et. al (US 2022/0302172 A1).
Regarding Claim 1, Hong discloses (as shown in fig. 2B):
An integrated circuit ([0006] Thus, the SDB structure may be employed in integrated circuits requiring a higher device density. However, the DDB structure may be more easily formed than the SDB structure because of its relatively large size, and also may achieve a better isolation performance than the SDB structure.), comprising: ([0052] Referring to FIGS. 2A and 2B, a multi-stack semiconductor device 20 shown therein may have the same or similar structures as those of the of multi-stack semiconductor device 10 shown in FIGS. 1A and 1B except some structures including a lower DDB structure 200L and an upper DDB structure 200U.)
a first semiconductor device ([0038] Each of the two multi-stack nanosheet transistors 100 and 200 includes a lower nanosheet transistor LNT) having one or more first bodies ([0039] The lower nanosheet transistor LNT includes a plurality of lower nanosheet layers 110 as channel for current flow in the lower nanosheet transistor LNT) of semiconductor material ([0039] Both of the lower nanosheet layers 110 and the upper nanosheet layers 120 may be grown by epitaxy from the substrate 105 formed of, for example, silicon (Si).) extending in a first direction ([0037] D1 direction) from a first source or drain region ([0040] lower source/drain regions 111) to a second source or drain region ([0040] lower source/drain regions …/112); (See Fig. 2B, showing the lower nanosheet layers 110 extending from the lower source/drain 111 to the lower source/drain 112 along the D1 direction)
a second semiconductor device ([0038] Each of the two multi-stack nanosheet transistors 100 and 200 includes … an upper nanosheet transistor UNT) having one or more second bodies ([0039] the upper nanosheet transistor UNT includes a plurality of upper nanosheet layers 120 as channel for current flow in the upper nanosheet transistor UNT) of semiconductor material ([0039] Both of the lower nanosheet layers 110 and the upper nanosheet layers 120 may be grown by epitaxy from the substrate 105 formed of, for example, silicon (Si).) extending in the first direction from a third source or drain region ([0040] upper source/drain regions 121) to a fourth source or drain region ([0040] upper source/drain regions …/122), (See Fig. 2B, showing the upper nanosheet layers 120 extending from the upper source/drain 121 to the upper source/drain 122 along the D1 direction)
wherein the one or more second bodies (120) of semiconductor material are spaced vertically from the one or more first bodies (110) of semiconductor material in a second direction ([0038] D3 direction) different from the first direction (D1), ([0038] a lower nanosheet transistor LNT and an upper nanosheet transistor UNT formed above a substrate 105 in this order in a D3 direction perpendicular to the D1 direction and the D2 direction.)
the third source or drain region (121) is spaced vertically from the first source or drain region (111) in the second direction (D3); ([0040] a 3rd isolation layer 133 may be formed between the lower source/drain regions 111/112 and the upper source/drain regions 121/122 for isolation thereof) (See Fig. 2B, showing the upper source/drain region 121 is spaced above the lower source/drain region 111 in the vertical D3 direction)
a first spacer structure ([0040] a spacer layer 151) extending between ends of the one or more first bodies of semiconductor material (110) and ends of the one or more second bodies of semiconductor material (120) in the second direction; ([0040] Further, a spacer layer 151 may be formed on two opposite surfaces of the lower gate structure 115, where the lower source/drain regions 111/112 are formed, and two opposite surfaces of the upper gate structure 125 where the upper source/drain regions 121/122 are formed)
a second spacer structure ([0040] A 2nd isolation layer 132) extending in the second direction (D3), (See Annotated Figure 2B, showing a portion of the end isolation layer 132 (Ann. Fig. 2B Second Spacer) comprising the second spacer of the second spacer structure (SSS))
the first source or drain region (111) and the third source or drain region (121) between the first spacer structure (151) and the second spacer structure (Ann. Fig. 2B, SSS); (See Ann. Fig. 2B, showing the first (111) and third (121) source/drain regions between the first (151) and second (SSS) spacer structure)
and a stressor material ([0043] According to an embodiment, the lower DDB structure 100L may be formed of a material favorable to compressive stress control of PFETs, such as silicon nitride or a combination of silicon nitride (SiN) and an oxide material including silicon oxide (SiO) or silicon dioxide (SiO.sub.2) not being limited thereto) ([0053] According to an embodiment, the lower DDB structure 200L and the upper DDB structure 200U are disposed between the 1st multi-stack nanosheet transistor 100 and the 2nd multi-stack nanosheet transistor 200 to cover a space SP2 corresponding to approximately one gate pitch in the D1 direction) adjacent to the second spacer structure (SSS), (See Ann. Fig. 2B, showing the lower (200L) adjacent to the second spacer structure (SSS))
such that at least a portion of the second spacer structure (SSS) is between the stressor material (200L, 200U) and the first source or drain region (111). (See Ann. Fig. 2B, showing a portion of the second spacer structure (SSS) is between the stressor material (200L) and the first source or drain region (111))
PNG
media_image1.png
760
981
media_image1.png
Greyscale
Ann. Fig. 2B
Regarding Claim 2, Hong further discloses (as shown in Fig. 2B):
wherein the one or more first bodies of semiconductor material (110) and the one or more second bodies of semiconductor material (120) comprise germanium, silicon, or any combination thereof. ([0039] Both of the lower nanosheet layers 110 and the upper nanosheet layers 120 may be grown by epitaxy from the substrate 105 formed of, for example, silicon (Si).)
Regarding Claim 4, Hong further discloses (as shown in Fig. 2B):
wherein the stressor material (200L) comprises a compressive stressor material that comprises silicon and nitrogen. ([0043] According to an embodiment, the lower DDB structure 100L may be formed of a material favorable to compressive stress control of PFETs, such as silicon nitride or a combination of silicon nitride (SiN) and an oxide material including silicon oxide (SiO) or silicon dioxide (SiO.sub.2) not being limited thereto)
Regarding Claim 5, Hong further discloses (as shown in Fig. 2B):
wherein the stressor material (200L) comprises a tensile stressor material that comprises silicon and oxygen. ([0043] formed of a material favorable to tensile stress control of NFETs, such as tonen silazene (TOSZ) not being limited thereto, according to an embodiment…[0044] For example, the lower DDB structure 100L may be formed of tonen silazene (TOSZ))
Regarding Claim 6, Hong further discloses (as shown in Fig. 2B):
wherein the stressor material (200L) is a first stressor material ([0043] According to an embodiment, the lower DDB structure 100L may be formed of a material favorable to compressive stress control of PFETs, such as silicon nitride or a combination of silicon nitride (SiN) and an oxide material including silicon oxide (SiO) or silicon dioxide (SiO2) not being limited thereto)
and the portion of the second spacer structure (132, SSS) is a first portion of the second spacer structure, (See Ann. Fig. 2B, showing a first portion (the portion between the first stressor material (200L) and the first source/drain (111)) of the second spacer structure)
and the integrated circuit further comprises a second stressor material ([0043] In contrast, the upper DDB structure 100U may be formed of a material favorable to tensile stress control of NFETs, such as tonen silazene (TOSZ) not being limited thereto, according to an embodiment.) ([0052] an upper DDB structure 200U) adjacent to the second spacer structure (SSS), (See Ann. Fig. 2B, showing the upper (200U) adjacent to the second spacer structure (SSS))
a second portion of the second spacer structure (SSS) being between the second stressor material (200U) and the third source or drain region (121). (See Ann. Fig. 2B, showing a second portion (Ann. Fig. 2B Second portion of Second Spacer Structure) between the second stressor material (200U) and the third source/drain (121))
Regarding Claim 8, Hong further discloses (as shown in Fig. 2B):
one or more nubs of semiconductor material within the second spacer structure (SSS) (See Ann. Fig. 2B, showing nubs of semiconductor material in the second spacer structure (SSS))
Regarding Claim 9, Hong further discloses (as shown in Fig. 2B):
A printed circuit board comprising the integrated circuit of claim 1. ([0112] Referring to FIG. 10, a semiconductor module 1000 according to an embodiment may include a processor 1200 and semiconductor devices 1300 that are mounted on a module substrate 1100. The processor 1200 and/or the semiconductor devices 1300 may include one or more multi-stack semiconductor devices described in at least one of the above embodiments.)
Regarding Claim 10, Hong discloses (as shown in Fig. 2B):
An electronic device ([0034] FIG. 1A illustrates a top plan view of a multi-stack semiconductor device), comprising:
a chip package comprising one or more dies ([0005] Referring to FIG. 12, a semiconductor device array 12 includes a plurality of gate structures PC1 through PC6 arranged at a predetermined interval of a gate pitch GP across an active region RX extended in a D1 direction above a substrate 105),
at least one of the one or more dies (105) comprising a first semiconductor device ([0039] The lower nanosheet transistor LNT) having one or more first semiconductor nanoribbons ([0039] The lower nanosheet transistor LNT includes a plurality of lower nanosheet layers 110 as channel for current flow in the lower nanosheet transistor LNT) extending in a first direction ([0037] D1 direction) between a first source or drain region ([0040] lower source/drain regions 111) and a second source or drain region ([0040] lower source/drain regions …/112); (See Fig. 2B, showing the lower nanosheet layers 110 extending from the lower source/drain 111 to the lower source/drain 112 along the D1 direction)
a second semiconductor device (an upper nanosheet transistor UNT) having one or more second semiconductor nanoribbons extending ([0039] upper nanosheet layers 120) ([0038] Each of the two multi-stack nanosheet transistors 100 and 200 includes … an upper nanosheet transistor UNT) in the first direction (D1) between a third source or drain region ([0040] upper source/drain regions 121) and a fourth source or drain region ([0040] upper source/drain regions …/122), (See Fig. 2B, showing the upper nanosheet layers 120 extending from the upper source/drain 121 to the upper source/drain 122 along the D1 direction)
wherein the one or more second semiconductor nanoribbons (120) are spaced vertically from the one or more first semiconductor nanoribbons (110) in a second direction ([0038] D3 direction) different from the first direction (D1), ([0038] a lower nanosheet transistor LNT and an upper nanosheet transistor UNT formed above a substrate 105 in this order in a D3 direction perpendicular to the D1 direction and the D2 direction.)
the third source or drain region (121) is spaced vertically from the first source or drain region (111) in the second direction (D3); ([0040] a 3rd isolation layer 133 may be formed between the lower source/drain regions 111/112 and the upper source/drain regions 121/122 for isolation thereof) (See Fig. 2B, showing the upper source/drain region 121 is spaced above the lower source/drain region 111 in the vertical D3 direction)
a first spacer structure ([0040] a spacer layer 151) extending between ends of the one or more first semiconductor nanoribbons (110) and ends of the one or more second semiconductor nanoribbons (120) in the second direction (D3); ([0040] Further, a spacer layer 151 may be formed on two opposite surfaces of the lower gate structure 115, where the lower source/drain regions 111/112 are formed, and two opposite surfaces of the upper gate structure 125 where the upper source/drain regions 121/122 are formed)
a second spacer structure ([0040] A 2nd isolation layer 132) structure extending in the second direction (D3), (See Annotated Figure 2B, showing a portion of the end isolation layer 132 (Ann. Fig. 2B Second Spacer Structure SSS))
wherein the first source or drain region (111) and the third source or drain region (121) are between the first spacer structure (151) and the second spacer structure (Ann. Fig. 2B, SSS); (See Ann. Fig. 2B, showing the first (111) and third (121) source/drain regions between the first (151) and second (SSS) spacer structure)
and a stressor material ([0043] According to an embodiment, the lower DDB structure 100L may be formed of a material favorable to compressive stress control of PFETs, such as silicon nitride or a combination of silicon nitride (SiN) and an oxide material including silicon oxide (SiO) or silicon dioxide (SiO.sub.2) not being limited thereto. In contrast, the upper DDB structure 100U may be formed of a material favorable to tensile stress control of NFETs, such as tonen silazene (TOSZ) not being limited thereto, according to an embodiment.) ([0053] According to an embodiment, the lower DDB structure 200L and the upper DDB structure 200U are disposed between the 1st multi-stack nanosheet transistor 100 and the 2nd multi-stack nanosheet transistor 200 to cover a space SP2 corresponding to approximately one gate pitch in the D1 direction) adjacent to the second spacer structure (SSS), (See Ann. Fig. 2B, showing the lower (200L) and upper (200U) adjacent to the second spacer structure (SSS))
wherein a portion of the second spacer structure (SSS) is between the stressor material (200L, 200U) and the first source or drain region (111). (See Ann. Fig. 2B, showing a portion of the second spacer structure (SSS) is between the stressor material (200L, 200U) and the first source or drain region (111))
Regarding Claim 11, Hong further discloses (as shown in Fig. 2B):
wherein the one or more first semiconductor nanoribbons (110) and the one or more second semiconductor nanoribbons (120) comprise germanium, silicon, or any combination thereof. ([0039] Both of the lower nanosheet layers 110 and the upper nanosheet layers 120 may be grown by epitaxy from the substrate 105 formed of, for example, silicon (Si).)
Regarding Claim 12, Hong further discloses (as shown in Fig. 2B):
wherein the stressor material (200L) is a first stressor material ([0043] According to an embodiment, the lower DDB structure 100L may be formed of a material favorable to compressive stress control of PFETs, such as silicon nitride or a combination of silicon nitride (SiN) and an oxide material including silicon oxide (SiO) or silicon dioxide (SiO2) not being limited thereto)
and the at least one of the one or more dies further comprises a second stressor material ([0043] In contrast, the upper DDB structure 100U may be formed of a material favorable to tensile stress control of NFETs, such as tonen silazene (TOSZ) not being limited thereto, according to an embodiment.) ([0052] an upper DDB structure 200U) adjacent to the second spacer structure (SSS), (See Ann. Fig. 2B, showing the upper (200U) adjacent to the second spacer structure (SSS))
such that a portion of the second spacer structure (SSS) is between the second stressor material (200U) and the third source or drain region (121). (See Ann. Fig. 2B, showing a second portion (Ann. Fig. 2B Second portion of Second Spacer Structure) between the second stressor material (200U) and the third source/drain (121))
Regarding Claim 13, Hong further discloses (as shown in Fig. 2B):
wherein the second stressor material (200U) is on the first stressor material (200L). (See Fig. 2B, showing the upper DDB structure 200U on the lower DBB structure 200L)
Regarding Claim 15, Hong further discloses (as shown in Fig. 2B):
further comprising a printed circuit board ([0112] Referring to FIG. 10, a semiconductor module 1000),
wherein the chip package is attached to the printed circuit board (1000). ([0112] Referring to FIG. 10, a semiconductor module 1000 according to an embodiment may include a processor 1200 and semiconductor devices 1300 that are mounted on a module substrate 1100. The processor 1200 and/or the semiconductor devices 1300 may include one or more multi-stack semiconductor devices described in at least one of the above embodiments.)
Regarding Claim 16, Hong discloses (as shown in Fig. 2B):
An integrated circuit ([0006] Thus, the SDB structure may be employed in integrated circuits requiring a higher device density. However, the DDB structure may be more easily formed than the SDB structure because of its relatively large size, and also may achieve a better isolation performance than the SDB structure.), comprising: ([0052] Referring to FIGS. 2A and 2B, a multi-stack semiconductor device 20 shown therein may have the same or similar structures as those of the of multi-stack semiconductor device 10 shown in FIGS. 1A and 1B except some structures including a lower DDB structure 200L and an upper DDB structure 200U.)
a first semiconductor device a first semiconductor device ([0038] Each of the two multi-stack nanosheet transistors 100 and 200 includes a lower nanosheet transistor LNT) having one or more first semiconductor nanoribbons ([0039] The lower nanosheet transistor LNT includes a plurality of lower nanosheet layers 110 as channel for current flow in the lower nanosheet transistor LNT) extending in a first direction ([0037] D1 direction) between a first p-doped source or drain region ([0040] lower source/drain regions 111) and a second p-doped source or drain region ([0040] lower source/drain regions …/112) ([0043] lower nanosheet transistors LNT, that is, PFETs); (See Fig. 2B, showing the lower nanosheet layers 110 extending from the lower source/drain 111 to the lower source/drain 112 along the D1 direction)
a second semiconductor device ([0038] Each of the two multi-stack nanosheet transistors 100 and 200 includes … an upper nanosheet transistor UNT) having one or more second semiconductor nanoribbons ([0039] upper nanosheet layers 120) ([0038] Each of the two multi-stack nanosheet transistors 100 and 200 includes … an upper nanosheet transistor UNT) extending in the first direction ([0037] D1 direction) between a first n-doped source or drain region ([0040] upper source/drain regions 121) and a second n-doped source or drain region ([0040] upper source/drain regions …/122) ([0043] upper nanosheet transistors UNT, that is, NFETs), (See Fig. 2B, showing the upper nanosheet layers 120 extending from the upper source/drain 121 to the upper source/drain 122 along the D1 direction)
wherein the one or more second semiconductor nanoribbons (120) are spaced vertically from the one or more first semiconductor nanoribbons (110) in a second direction ([0038] D3 direction) different from the first direction (D1), ([0038] a lower nanosheet transistor LNT and an upper nanosheet transistor UNT formed above a substrate 105 in this order in a D3 direction perpendicular to the D1 direction and the D2 direction.)
the first n-doped source or drain region (121) is spaced vertically from the first p-doped source or drain region (111) in the second direction (D3); ([0040] a 3rd isolation layer 133 may be formed between the lower source/drain regions 111/112 and the upper source/drain regions 121/122 for isolation thereof) (See Fig. 2B, showing the upper source/drain region 121 is spaced above the lower source/drain region 111 in the vertical D3 direction)
a first spacer structure ([0040] a spacer layer 151) extending between ends of the one or more first semiconductor nanoribbons (110) and ends of the one or more second semiconductor nanoribbons (120) in the second direction; ([0040] Further, a spacer layer 151 may be formed on two opposite surfaces of the lower gate structure 115, where the lower source/drain regions 111/112 are formed, and two opposite surfaces of the upper gate structure 125 where the upper source/drain regions 121/122 are formed)
a second spacer structure ([0040] A 2nd isolation layer 132) extending in the second direction (D3), (See Annotated Figure 2B, showing a portion of the end isolation layer 132 (Ann. Fig. 2B Second Spacer Structure SSS))
such that the first n-doped source or drain region (121) and the first p-doped source or drain region (111) are between the first spacer structure (151) and the second spacer structure (132, SSS); (See Ann. Fig. 2B, showing the first (111) and third (121) source/drain regions between the first (151) and second (SSS) spacer structure)
a compressive stressor material ([0043] According to an embodiment, the lower DDB structure 100L may be formed of a material favorable to compressive stress control of PFETs, such as silicon nitride or a combination of silicon nitride (SiN) and an oxide material including silicon oxide (SiO) or silicon dioxide (SiO2) not being limited thereto) adjacent to the second spacer structure (132, SSS), (See Ann. Fig. 2B, showing a portion of the 2nd isolation layer 132 in the second spacer structure SSS is adjacent to the lower DDB 200L)
such that a portion of the second spacer structure (132, SSS) is between the compressive stressor material (200L) and the first p- doped source or drain region (111); (See Ann. Fig. 2B, a portion of the 2nd isolation layer 132 in the second spacer structure SSS is between the compressive stressor material (200L) and the first p-doped source or drain region (111))
and a tensile stressor material ([0043] In contrast, the upper DDB structure 100U may be formed of a material favorable to tensile stress control of NFETs, such as tonen silazene (TOSZ) not being limited thereto, according to an embodiment.) ([0052] an upper DDB structure 200U) adjacent to the second spacer structure (132, SSS), (See Ann. Fig. 2B, showing the upper (200U) adjacent to the second spacer structure (SSS))
such that a portion of the second spacer structure (132, SSS) is between the tensile stressor material (200U) and the first n-doped source or drain region (121). (See Ann. Fig. 2B, showing a second portion (Ann. Fig. 2B Second portion of Second Spacer Structure) between the second stressor material (200U) and the first n-doped source/drain (121))
Regarding Claim 18, Hong further discloses (as shown in Fig. 2B)
wherein the compressive stressor material (200L) comprises silicon and nitrogen. ([0043] According to an embodiment, the lower DDB structure 100L may be formed of a material favorable to compressive stress control of PFETs, such as silicon nitride or a combination of silicon nitride (SiN))
Regarding Claim 19, Hong further discloses (as shown in Fig. 2B)
wherein the tensile stressor material (200U) comprises silicon and oxygen. ([0043] In contrast, the upper DDB structure 100U may be formed of a material favorable to tensile stress control of NFETs, such as tonen silazene (TOSZ) not being limited thereto, according to an embodiment.)
Regarding Claim 19, Hong further discloses (as shown in Fig. 2B)
wherein the tensile stressor material (200U) is on the compressive stressor material (200L). (See Fig. 2B, showing the upper DBB 200U is on the lower DBB 200L)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong as applied to claim 1 above, and further in view of Lee et. al (US 2019/0131395 A1).
Regarding Claim 3, Hong fails to disclose wherein the first source or drain region (111) and the second source or drain region (112) comprise silicon, germanium, and boron, and the third source or drain region (121) and the fourth source or drain region (122) comprise silicon and phosphorous.
Lee discloses (as shown in Fig. 13) wherein the first source or drain region and the second source or drain region ([0050] The remaining portion of the pFET S/D semiconductor material 22 can be referred to herein as a pFET S/D region 22S.) comprise silicon, germanium, and boron, ([0049] pFET S/D semiconductor material 22 may comprise a silicon germanium alloy… [0049] The term “p-type” refers to the addition of impurities to an intrinsic semiconductor that creates deficiencies of valence electrons. In a silicon-containing semiconductor material, examples of p-type dopants, i.e., impurities, include, but are not limited to, boron, aluminum, gallium and indium.)
and the third source or drain region and the fourth source or drain region ([0055] nFET S/D region 26S) comprise silicon and phosphorous ([0055] each nFET S/D region 26S comprises silicon that is doped with phosphorus (i.e., P doped Si))
It would have been obvious to one having ordinary skill in the art before the effective filing date of the present application to combine the teachings of Hong and Lee. Hong discloses a stacked nanosheet transistor design featuring an NFET and a PFET ([0041] According to an embodiment, each of the lower nanosheet transistors LNT may be one of a p-type transistor and an n-type transistor, and each of the upper nanosheet transistor UNT may be the other of the p-type transistor and the n-type transistor.) with source/drain structures. (111, 112, 121, 122) However, Hong fails to disclose the materials that the NFET and PFET source drain structures are made from. Lee also discloses a stacked nanosheet transistor design featuring an NFET and a PFET ([0031] stacked pFET and nFET device regions) and further discloses the materials used in forming the source drain regions of the pFET ([0050] pFET S/D region 22S) and the nFET ([0055] nFET S/D region 26S). Therefore, it would have been obvious to make the S/D regions of Hong out of the materials used in Lee since the materials in Lee form functioning S/D regions for stacked nFETs and pFETs.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong as applied to claim 16 above, and further in view of Lee et. al (US 2019/0131395 A1).
Regarding Claim 17, Hong fails to disclose wherein the first p-doped source or drain region (111) and the second p-doped source or drain region (112) comprise silicon, germanium, and boron, and the first n-doped source or drain region (121) and the second n-doped source or drain region (122) comprise silicon and phosphorous.
Lee discloses (as shown in Fig. 13) wherein the first p-doped source or drain region and the second p-doped source or drain region ([0050] The remaining portion of the pFET S/D semiconductor material 22 can be referred to herein as a pFET S/D region 22S.) comprise silicon, germanium, and boron, ([0049] pFET S/D semiconductor material 22 may comprise a silicon germanium alloy… [0049] The term “p-type” refers to the addition of impurities to an intrinsic semiconductor that creates deficiencies of valence electrons. In a silicon-containing semiconductor material, examples of p-type dopants, i.e., impurities, include, but are not limited to, boron, aluminum, gallium and indium.)
and the first n-doped source or drain region and the second n-doped source or drain region ([0055] nFET S/D region 26S) comprise silicon and phosphorous ([0055] each nFET S/D region 26S comprises silicon that is doped with phosphorus (i.e., P doped Si))
It would have been obvious to one having ordinary skill in the art before the effective filing date of the present application to combine the teachings of Hong and Lee. Hong discloses a stacked nanosheet transistor design featuring an NFET and a PFET ([0041] According to an embodiment, each of the lower nanosheet transistors LNT may be one of a p-type transistor and an n-type transistor, and each of the upper nanosheet transistor UNT may be the other of the p-type transistor and the n-type transistor.) with source/drain structures. (111, 112, 121, 122) However, Hong fails to disclose the materials that the NFET and PFET source drain structures are made from. Lee also discloses a stacked nanosheet transistor design featuring an NFET and a PFET ([0031] stacked pFET and nFET device regions) and further discloses the materials used in forming the source drain regions of the pFET ([0050] pFET S/D region 22S) and the nFET ([0055] nFET S/D region 26S). Therefore, it would have been obvious to make the S/D regions of Hong out of the materials used in Lee since the materials in Lee form functioning S/D regions for stacked nFETs and pFETs.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON JAMES GREAVING whose telephone number is (703)756-5653. The examiner can normally be reached 7:30am - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/J.J.G./Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893