DETAILED ACTION
This Office Actions is in response to communication (Amendment) filed on 04/28/2026.
Claims 1 – 13, 16, and 18 – 23 are pending. Claims 1, 16, and 20 are in independent form. Claims 1, 7, 8, 16, and 20 are amended. Claims 14, 15 and 17 are canceled. This action is Final.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to the applicant’s remarks and arguments filed on 04/28/2026.
Claims 1, 7, 8, 16, and 20 were amended. Claims 1 – 13, 16, and 18 – 23 remain pending in the application. Claims 1 – 13, 16, 18 – 23 are being considered on the merits.
The rejection under 35 U.S.C. §112 has been withdrawn due to the amendment to the claim filed on 04/28/2026.
The rejection under 35 U.S.C. §101 has been maintained, because the newly added limitations are analyzed under Prong 2 Step 2A, and step 2B, in which the newly added limitations are merely recites "apply it" (or an equivalent) or are no more than mere instructions to implement an abstract idea or other exception on a computer, which did not help to overcome the 35 U.S.C. §101 Rejection.
The Rejection of claims 1 – 13, 16, and 18 – 23 under 35 U.S.C § 103 has been withdrawn due to the amendment to the claims filed on 04/28/2026. However, upon further consideration, a new ground(s) of rejection is made in view of a newly found prior art Fejfar et al. US Pat. No. US 9891978 B1 (hereafter Fejfar), and in view of the previously cited prior art(s). Reference Fejfar, in combination with previously cited prior art(s), discloses each element of the claims highlighted by applicant. For further details, please see below claims rejections under 35 U.S.C § 103.
Response to Arguments
The applicant’s remarks and/or arguments, filed on 04/28/2026 have been fully considered with the following result(s).
The examiner is entitled to give claim limitations their broadest reasonable interpretation in light of the specification. See MPEP 2111 [R-1] Interpretation of Claims-Broadest Reasonable Interpretation. The applicant always has the opportunity to amend the claims during prosecution, and broad interpretation by the examiner reduces the possibility that the claim, once issued, will be interpreted more broadly than is justified. In re Prater, 162 USPQ 541,550-51 (CCPA 1969).
Response to 35 U.S.C. §101 Remarks
Applicant’s argument filed on 04/28/2026 regarding the 35 USC § 101 rejection has been fully considered but they are not persuasive.
The examiner would like to point out that the newly added limitation “processing, by a first physical central processing unit (CPU) core of a computing device, a workload during a runtime of the computing device, wherein a first logical CPU core of the first physical CPU core is included in a first mapping that maps a virtual processor to the first logical CPU core;” and “generating a set of performance indicators for [[a]] the first physical CPU by executing a performance test on the first physical CPU core, wherein the set of performance indicators is generated based on evaluating at least one of performance logs or alert logs indicating historical performance of the first physical CPU core” are analyzed under Prong 2 Step 2A, and step 2B, in which the newly added limitations are merely recites "apply it" (or an equivalent) or are no more than mere instructions to implement an abstract idea or other exception on a computer.
Thus, based on all of the above explanation, the examiner finds these arguments unpersuasive and maintains that the rejection under 35 U.S.C. § 101 is proper.
Response to 35 U.S.C. §112 Remarks
Applicant’s argument filed on 04/28/2026 regarding the 35 USC § 112 rejection has been fully considered and they are persuasive. The examiner agreed with all the changes made to the claims. The previous 35 USC § 112 rejection has been withdrawn.
Response to 35 U.S.C. §103 Remarks
Applicant’s argument filed on 04/28/2026 in the applicant’s remarks and amendments of independent claims 1 – 13, 16, and 18 – 23, found on pages 10-11 and filed on 04/28/2026, have been fully considered and are persuasive. Therefore, the previous claim(s) rejection under 35 U.S.C § 103 has been withdrawn.
However, upon further consideration, a new ground(s) of rejection is made in view of a newly found prior art Fejfar et al. US Pat. No. US 9891978 B1 (hereafter Fejfar), and in view of the previously cited prior art(s). Reference Fejfar, in combination with previously cited prior art(s), discloses each element of the claims highlighted by applicant.
For further details, please see below claims rejections under 35 U.S.C § 103.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1 – 13, 16, 18 – 23 are rejected under 35 U.S.C. 101 because the claimed invention recites a judicial exception, is directed to that judicial exception, an abstract idea, as it has not been integrated into practical application and the claims further do not recite significantly more than the judicial exception. Examiner has evaluated the claims under the framework provided in the 2019 Patent Eligibility Guidance published in the Federal Register 01/07/2019 and has provided such analysis below.
With regard to claims 1, 16, and 20 these claims are within at least one of the four categories of patent eligible subject matter as it is directing to:
Step 1:
Claims 1 is directed to methods and fall within the statutory category of processes;
Claim 16 is directed to a system and falls within the statutory category of machine;
Claim 20 is directed to a device and falls within the statutory category of machine;
Therefore, “Are the claims to a process, machine, manufacture or composition of matter?” Yes, under Step 1.
In order to evaluate the Step 2A inquiry “Is the claim directed to a law of nature, a natural phenomenon or an abstract idea?” we must determine, at Step 2A Prong 1, whether the claim recites a law of nature, a natural phenomenon or an abstract idea and further whether the claim recites additional elements that integrate the judicial exception into a practical application.
Step 2A Prong 1:
However, the limitations
Claim 1: based on the set of performance indicators, determining the first physical CPU core is to be off-parked .......; creating a second mapping that maps the virtual processor to a second logical CPU core of the second physical CPU, wherein the first physical CPU core is not mapped to the virtual processor in the second mapping;
Claim 16: based on the set of performance indicators.........; creating a second mapping, wherein the second mapping correlates a second logical CPU core of the second physical CPU core to the virtual processor of the virtual machine
Claim 20: based on the set of performance indicators, determining the first physical CPU core is to be off-parked.........; creating a second mapping, wherein the second mapping correlates a second logical CPU core of the second physical CPU core to the virtual processors of the set of virtual machines.
as drafted, recite functions that, under its broadest reasonable interpretation, covers functions that could reasonably be performed in the mind, including with the aid of pen and paper, but for the recitation of generic computer components. The limitations encompass a human mind carrying out the function through observation, evaluation judgment and /or opinion, or even with the aid of pen and paper. For example, a person can perform the determining/selecting which CPU cores to be off-parked, or creating/selecting which virtual processors to be mapped to the logical CPU cores, in the mind, and/or including with the aid of pen and paper, but for the recitation of generic computer components. (See MPEP § 2106.04(a)(2)(III)).
That is, the above limitations in the claims 1, 16, and 20, as drafted, are functions that, under its broadest reasonable interpretation, recite the abstract idea of a mental process. The limitations encompass a human mind carrying out the functions through observation, evaluation, judgment and /or opinion, or even with the aid of pen and paper. Thus, these limitations recite and fall within the “Mental Processes” grouping of abstract ideas under Step 2A Prong 1.
Prong 2 Step 2A:
Under Prong 2 Step 2A, this judicial exception is not integrated into a practical application. The claims recite the following additional elements:
Claim 1: A method comprising ....... a computing device
Claim 16: A system comprising: memory comprising computer executable instructions that, when executed, perform operations comprising
Claim 20: A device comprising: memory comprising computer executable instructions that, when executed, perform operations comprising
are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using a generic computer component, or merely a generic computer or generic computer components to perform the judicial exception.
Further, the claims recite the following additional elements:
Claim 1: processing, by a first physical central processing unit (CPU) core of a computing device, a workload during a runtime of the computing device, wherein a first logical CPU core of the first physical CPU core is included in a first mapping that maps a virtual processor to the first logical CPU core; generating a set of performance indicators for a first physical CPU by executing a performance test on the first physical CPU core, wherein the set of performance indicators is generated based on evaluating at least one of performance logs or alert logs indicating historical performance of the first physical CPU core; ........ wherein off-parking the first physical CPU core comprises: disabling the first physical CPU core such that the first physical CPU core is ignored during allocation of workloads to the virtual processor; and maintaining a second physical CPU core to process the workloads; and implementing the second mapping by executing at least one of the workloads using the virtual processor in accordance with the second mapping.
Claim 16: generating a set of performance indicators for a first physical central processing unit (CPU) core that is malfunctioning by executing a performance test on the first physical CPU core, the first physical CPU core being associated with a first logical CPU core, wherein a first mapping correlates the first logical CPU core to a virtual processor of a virtual machine; ........... off-parking the first physical CPU core, wherein off-parking the first physical CPU core comprises disabling the first physical CPU core such that the first physical CPU core is ignored during allocation of workloads to the virtual processor; and maintaining a second physical CPU core in an active state, thereby enabling the second physical CPU core to process the workloads; ........ and implementing the second mapping by executing at least one of the workloads using the virtual processor in accordance with the second mapping.
Claim 20: processing, by a first physical central processing unit (CPU) core, a workload during a runtime of the device, wherein a first logical CPU core of the first physical CPU core is included in a first mapping that maps a virtual processor of a virtual machine to the first logical CPU core; ......... by executing a performance test on the first physical CPU core, wherein the set of performance indicators is generated based on evaluating at least one of performance logs or alert logs indicating historical performance of the first physical CPU core; ......... wherein off-parking the first physical CPU core comprises disabling the first physical CPU core such that workloads are prevented from being provided to or processed by the first physical CPU core; and maintaining a second physical CPU core to process the workloads; and implementing the second mapping by executing at least one of the workloads using the virtual processors of the set of virtual machines in accordance with the second mapping.
which are merely recites "apply it" (or an equivalent) or are no more than mere instructions to implement an abstract idea or other exception on a computer. The above limitations invoke computers or other machinery merely as a tool to perform an existing process (e.g., to generate data by executing a function, and analyzing the data) or simply adding a general-purpose computer or computer components after the fact to an abstract idea (e.g., determining CPU cores to be off-parked) does not integrate a judicial exception into a practical application or provide significantly more (see MPEP § 2106.05(f)).
In addition, the claims also recite the following additional elements:
Claim 20: receiving a set of performance indicators for a first physical central processing unit (CPU) core that is malfunctioning
which are the limitations merely a recitation of limit the use of the abstract idea amounts to necessary data gathering and outputting - Insignificant Extra-Solution Activity - pre-solution and post-solution activity - mere data gathering. Extra-solution activity includes both pre-solution and post-solution activity. An example of pre-solution activity is a step of gathering data for use in a claimed process. As explained by the Supreme Court, the addition of insignificant extra-solution activity does not amount to an inventive concept, particularly when the activity is well-understood or conventional, which does not integrate a judicial exception into practical application. (See MPEP § 2106.05(g)).
Therefore, these additional elements do not integrate the abstract idea into a practical application and they do not impose any meaningful limits on practicing the abstract idea. The claims are directed to an abstract idea.
After having evaluating the inquires set forth in Steps 2A Prong 1 and 2, it has been concluded that the claims 1, 16, and 20 do not only recites a judicial exception but that the claims are directed to the judicial exception as the judicial exception has not been integrated into practical application.
Step 2B:
Under Step 2B, the claims do not include additional elements, alone or in combination, that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements amount to no more than generic computing components and invoking computers and other machinery merely as a tool to perform an existing process, which do not amount to significantly more than the abstract idea. The claims that amount to nothing more than an instruction to apply the abstract idea using a generic computer do not render an abstract idea eligible.
The claims recite the following additional elements:
Claim 20: receiving a set of performance indicators for a first physical central processing unit (CPU) core that is malfunctioning
which is the limitation merely a recitation of limit the use of the abstract idea amounts to necessary data gathering and outputting - Insignificant Extra-Solution Activity - pre-solution and post-solution activity - mere data gathering. Extra-solution activity includes both pre-solution and post-solution activity. The courts have recognized the “sending and receiving data” are insignificant extra-solution data gathering activity which do not amount to significantly more than the abstract idea, and are limitations computer functions as well-understood, routine, conventional (WURC) functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. (See TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 614, 118 USPQ2d 1744, 1748 (Fed. Cir. 2016) (Specification described additional elements as “either performing basic computer functions such as sending and receiving data, or performing functions ‘known’ in the art.”) and MPEP § 2106.05(d)).
In addition, the claims also recite the following additional elements:
Claim 1: processing, by a first physical central processing unit (CPU) core of a computing device, a workload during a runtime of the computing device, wherein a first logical CPU core of the first physical CPU core is included in a first mapping that maps a virtual processor to the first logical CPU core; generating a set of performance indicators for a first physical CPU by executing a performance test on the first physical CPU core, wherein the set of performance indicators is generated based on evaluating at least one of performance logs or alert logs indicating historical performance of the first physical CPU core; ........ wherein off-parking the first physical CPU core comprises: disabling the first physical CPU core such that the first physical CPU core is ignored during allocation of workloads to the virtual processor; and maintaining a second physical CPU core to process the workloads; and implementing the second mapping by executing at least one of the workloads using the virtual processor in accordance with the second mapping.
Claim 16: generating a set of performance indicators for a first physical central processing unit (CPU) core that is malfunctioning by executing a performance test on the first physical CPU core, the first physical CPU core being associated with a first logical CPU core, wherein a first mapping correlates the first logical CPU core to a virtual processor of a virtual machine; ........... off-parking the first physical CPU core, wherein off-parking the first physical CPU core comprises disabling the first physical CPU core such that the first physical CPU core is ignored during allocation of workloads to the virtual processor; and maintaining a second physical CPU core in an active state, thereby enabling the second physical CPU core to process the workloads; ........ and implementing the second mapping by executing at least one of the workloads using the virtual processor in accordance with the second mapping.
Claim 20: processing, by a first physical central processing unit (CPU) core, a workload during a runtime of the device, wherein a first logical CPU core of the first physical CPU core is included in a first mapping that maps a virtual processor of a virtual machine to the first logical CPU core; ......... by executing a performance test on the first physical CPU core, wherein the set of performance indicators is generated based on evaluating at least one of performance logs or alert logs indicating historical performance of the first physical CPU core; ......... wherein off-parking the first physical CPU core comprises disabling the first physical CPU core such that workloads are prevented from being provided to or processed by the first physical CPU core; and maintaining a second physical CPU core to process the workloads; and implementing the second mapping by executing at least one of the workloads using the virtual processors of the set of virtual machines in accordance with the second mapping.
which are merely recites "apply it" (or an equivalent) or are no more than mere instructions to implement an abstract idea or other exception on a computer, which do not amount to significantly more than the abstract idea. The courts have found the additional elements to be mere instructions to apply an exception, because they do no more than merely invoke computers or machinery as a tool to perform an existing process include requiring the use of software to tailor information and provide it to the user on a generic computer. (See Intellectual Ventures I LLC v. Capital One Bank (USA), 792 F.3d 1363, 1370-71, 115 USPQ2d 1636, 1642 (Fed. Cir. 2015)) and MPEP § 2106.05(f)).
Therefore, “Do the claims recite additional elements that amount to significantly more than the judicial exception? No, these additional elements, alone or in combination, do not amount to significantly more than the judicial exception.
Having concluded analysis within the provided framework, claims 1, 16, and 20 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Apply the same analysis to the dependent claims 2 – 13 and 18, 19, and 21 – 23, according to the above analysis, are mental processes, groupings of abstract ideas. Thus claims 2 – 14 and 18, 19, 21, and 22 are ineligible.
With regard to claim 2, the claim has the limitation to further indicate the wherein the first physical CPU core is implemented by a host device, the host device comprising a virtual machine. The limitation is the additional element analyzed under Prong 2 Step 2A, which merely recites "apply it" (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. Thus, they do not cite any additional elements that are sufficient to amount to significantly more than the judicial exception.
With regard to claim 3, the claim has the limitation to further indicate the wherein the virtual processor is implemented by the virtual machine to execute workloads of the virtual machine. The limitation is the additional element analyzed under Prong 2 Step 2A, which merely recites "apply it" (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. Thus, they do not cite any additional elements that are sufficient to amount to significantly more than the judicial exception.
With regard to claim 4, the claim has the limitation to further indicate the wherein the performance test is executed by a hypervisor of the host device, wherein the hypervisor manages the virtual machine. The limitation is the additional element analyzed under Prong 2 Step 2A, which merely recites "apply it" (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. Thus, they do not cite any additional elements that are sufficient to amount to significantly more than the judicial exception.
With regard to claim 5, the claim has the limitation to further indicate the wherein the first logical CPU core represents a number of threads that can be executed by the first physical CPU core. The limitation is the additional element analyzed under Prong 2 Step 2A, which merely recites "apply it" (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. Thus, they do not cite any additional elements that are sufficient to amount to significantly more than the judicial exception.
With regard to claim 6, the claim has the limitation to further indicate the wherein executing the performance test comprises causing the first physical CPU core to execute a set of commands or instructions that generate CPU metrics for the first physical CPU core. The limitation is the additional element analyzed under Prong 2 Step 2A, which merely recites "apply it" (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. Thus, they do not cite any additional elements that are sufficient to amount to significantly more than the judicial exception.
With regard to claim 7, the claim has the limitation to further indicate the wherein executing the performance test comprises accessing the at least one of the performance logs or alert logs for the first physical CPU core. The limitation is the additional element analyzed under Prong 2 Step 2A, which merely recites "apply it" (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. Thus, they do not cite any additional elements that are sufficient to amount to significantly more than the judicial exception.
With regard to claim 8, the claim has the limitation to further indicate the wherein set of performance indicators comprises CPU metrics for the first physical CPU core, the CPU metrics comprising at least one of: availability; response time; or service time. The limitation is the additional element analyzed under Prong 2 Step 2A, which merely recites "apply it" (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. Thus, they do not cite any additional elements that are sufficient to amount to significantly more than the judicial exception.
With regard to claim 9, the claim has the limitation to further indicate the wherein the CPU metrics further comprise at least one of: channel capacity; bandwidth; or relative efficiency. The limitation is the additional element analyzed under Prong 2 Step 2A, which merely recites "apply it" (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. Thus, they do not cite any additional elements that are sufficient to amount to significantly more than the judicial exception.
With regard to claim 10, the claim has the limitation to further indicate the wherein set of performance indicators comprises at least one of: a number of errors reported for the first physical CPU core; a frequency of errors reported for the first physical CPU core; or a length of time the first physical CPU core has been in use. The limitation is the additional element analyzed under Prong 2 Step 2A, which merely recites "apply it" (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. Thus, they do not cite any additional elements that are sufficient to amount to significantly more than the judicial exception.
With regard to claim 11, the claim further includes the limitation of “wherein determining the first physical CPU core is to be off-parked comprises comparing the set of performance indicators to a set of parameters indicating threshold values for the set of performance indicators” that fall with the “Mental Processes” grouping of abstract ideas, which is analyzed under Prong 1 Step 2A. Thus, they do not cite any additional elements that are sufficient to amount to significantly more than the judicial exception.
With regard to claim 12, the claim further includes the limitation of “wherein performance indicators in the set of performance indicators that exceed the threshold values indicate the first physical CPU core is currently defective.” that fall with the “Mental Processes” grouping of abstract ideas, which is analyzed under Prong 1 Step 2A. Thus, they do not cite any additional elements that are sufficient to amount to significantly more than the judicial exception.
With regard to claim 13, the claim has the limitation to further indicate the wherein the virtual processor is implemented by a virtual machine. The limitation is the additional element analyzed under Prong 2 Step 2A, which merely recites "apply it" (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. Thus, they do not cite any additional elements that are sufficient to amount to significantly more than the judicial exception.
With regard to claim 18, the claim has the limitation to further indicate the wherein disabling the first physical CPU core comprises placing the first physical CPU core into an emergency role such that the first physical CPU core receives workloads when no other physical CPU cores are available. The limitation is the additional element analyzed under Prong 2 Step 2A, which merely recites "apply it" (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. Thus, they do not cite any additional elements that are sufficient to amount to significantly more than the judicial exception.
With regard to claim 19, the claim has the limitation to further indicate the wherein implementing the second mapping comprises: replacing the first mapping with the second mapping. The limitation is the additional element analyzed under Prong 2 Step 2A, which merely recites "apply it" (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. Thus, they do not cite any additional elements that are sufficient to amount to significantly more than the judicial exception.
With regard to claim 21, the claim further includes the limitation of “wherein determining the first physical CPU core is to be off-parked comprises: comparing at least one performance indicator in the set of performance indicators to a threshold value for the at least one performance indicator; determining the at least one performance indicator meets or exceeds the threshold value; and in response to determining the at least one performance indicator meets or exceeds the threshold value, determining the first physical CPU core is to be off-parked.” that fall with the “Mental Processes” grouping of abstract ideas, which is analyzed under Prong 1 Step 2A. Thus, they do not cite any additional elements that are sufficient to amount to significantly more than the judicial exception.
With regard to claim 22, the claim further includes the limitation of “wherein determining the at least one performance indicator meets or exceeds the threshold value comprises determining the at least one performance indicator meets or exceeds a count of errors defined for a lifetime of the first physical CPU core.” that fall with the “Mental Processes” grouping of abstract ideas, which is analyzed under Prong 1 Step 2A. Thus, they do not cite any additional elements that are sufficient to amount to significantly more than the judicial exception.
With regard to claim 23, the claim has the limitation to further indicate the wherein implementing the second mapping further comprises preventing, by an operating system kernel of the computing device, scheduling of application threads on the first physical CPU core while the first physical CPU core is off- parked. The limitation is the additional element analyzed under Prong 2 Step 2A, which merely recites "apply it" (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. Thus, they do not cite any additional elements that are sufficient to amount to significantly more than the judicial exception.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 3, 5-7, 11 – 13, 16, 19, 20 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Bieswanger et al. US Pub. No. US 20100037038 A1 (hereafter Bieswanger), in further view of PACKER ALI et al. US Pub. No. US 20180253314 A1 (hereafter PACKER) and Fejfar et al. US Pat. No. US 9891978 B1 (hereafter Fejfar)
Regarding claim 1, Bieswanger teaches the invention suitable as claim A method comprising: processing, by a first physical central processing unit (CPU) core of a computing device, a workload during a runtime of the computing device, (e.g. FIG. 1 and [0023]: “As depicted in FIG. 1, system 100 may execute a number of applications 110 in memory 104. For example, system 100 may comprise part of a server system, such as a computing board, or blade server, in a rack-mount server. Processors 140 and 150 may execute operating instructions for programs and applications run by users of system 100.”) The citation discloses the system 100 execute/process, applications 110/workload, using processor 140 and 150/CPU.
wherein a first logical CPU core of the first physical CPU core is included in a first mapping that maps a virtual processor to the first logical CPU core (e.g. FIG. 2A, and [0043]: “Processors 250, 252, 254, and 256 may comprise physical processors. In an embodiment, each processor may have a plurality of cores. In the embodiment of FIGS. 2A and 2B, each processor has two cores....... Processors 250, 252, 254, and 256 may comprise a shared processor pool. The shared processing pool may allow a system or apparatus to assign partial processors to a logical partition. In other words, a system may hold physical processors 250, 252, 254, and 256 in a shared processing pool and share processors 250, 252, 254, and 256, as well as the cores of the processors, among numerous logical partitions. In FIG. 2A, for example, a system may share processors 250, 252, 254, and 256 among partitions 202, 204, 206, 208, and 210.” and [0044]: “In an embodiment, virtual processors may comprise whole numbers of concurrent operations which an operating system can utilize. The processing power may be conceptualized as being spread equally across these virtual processors. Selecting a specific number of virtual processors may depend on the workload of the partition. In the embodiment of FIG. 2A, the system has 4 physical processors in the shared pool, specifically processors 250, 252, 254, and 256. The 4 physical processors have 8 cores 241-248 which may provide a total of 8.00 virtual processing units.” and [0045]) The citation discloses a system comprises multiple physical processors, and each has plurality of cores/logical CPU core. As the system may share processors 250, 252, 254, and 256 among partitions 202, 204, 206, 208, and 210, and there is a VM manager that managing the virtual processors, it implies that there is a mapping between the virtual processors and the cores or the physical processors.
wherein off-parking the first physical CPU core comprises disabling the first physical CPU core such that workloads are prevented from being provided to or processed by the first physical CPU core (e.g. FIG. 2B and [0051]: “As illustrated in the transition from FIG. 2A to FIG. 2B, virtual machine manager 230 may shift the loads from cores 246, 247, and 248 over to cores 241-245. As a result of shifting the loads and remapping the virtual processing units, cores 246, 247, and 248 may be executing no instructions........ virtual machine manager 230 may also be able to switch the power state of processor 256 to a low power state, or potentially to a sleep mode, which may allow for even greater power conservation since cores 247 and 248 are inactive.”) the citation discloses the processor 256/physical CPU core, is in a sleep mode/disable, with no instructions is executing on the processor 256/workloads are prevented from being provided.
and maintaining a second physical CPU core of the computing device such that the second physical CPU core is able to process the workloads (e.g. FIG. 2A, FIG. 2B, and [0049]: “As illustrated in FIG. 2B, virtual machine manager 230 may change the mapping of the virtual processing units among the logical partitions 202, 204, 206, 208, and 210. Virtual machine manager 230 may reduce the processing units for partition 202 from 2.0 processing units to 1.0 processing unit. Similarly, virtual machine manager 230 may reduce the processing units for partitions 204, 206, and 208 to 1.0, 0.75, and 0.25, respectively. Consequently, virtual machine manager 230 may reduce the number of virtual processors from 8 to 5, and remap the virtual processing units from cores 246, 247, and 248, packing the virtual processing units onto cores 241-245.” and [0051] In reducing and expanding the number of active processor cores, virtual machine manager 230 may pack the active cores together on a smaller number of chips or integrated circuits (ICs) to conserve power. As illustrated in the transition from FIG. 2A to FIG. 2B, virtual machine manager 230 may shift the loads from cores 246, 247, and 248 over to cores 241-245.) The citation discloses the load from cores 246, 247, and 248 is being move to cores 241 – 245 that are currently in the active state.
creating a second mapping that maps the virtual processor to a second logical CPU core of the second physical CPU, wherein the first physical CPU core is not mapped to the virtual processor in the second mapping; (e.g. FIG. 2B and [0049]: “As illustrated in FIG. 2B, virtual machine manager 230 may change the mapping of the virtual processing units among the logical partitions 202, 204, 206, 208, and 210. Virtual machine manager 230 may reduce the processing units for partition 202 from 2.0 processing units to 1.0 processing unit. Similarly, virtual machine manager 230 may reduce the processing units for partitions 204, 206, and 208 to 1.0, 0.75, and 0.25, respectively. Consequently, virtual machine manager 230 may reduce the number of virtual processors from 8 to 5, and remap the virtual processing units from cores 246, 247, and 248, packing the virtual processing units onto cores 241-245.” and [0050]: “One may note that after the mapping change, all five partitions still have at least one processor. Under a different set of conditions, however, applications of a partition may be completely inactive. Consequently, virtual machine manager 230 may be able to suspend the operating system for the partition and change the mapping of virtual processors as well, reducing the number of virtual processors from 8 to 7, as an example.” and [0051]: “As illustrated in the transition from FIG. 2A to FIG. 2B, virtual machine manager 230 may shift the loads from cores 246, 247, and 248 over to cores 241-245. As a result of shifting the loads and remapping the virtual processing units, cores 246, 247, and 248 may be executing no instructions........ virtual machine manager 230 may also be able to switch the power state of processor 256 to a low power state, or potentially to a sleep mode, which may allow for even greater power conservation since cores 247 and 248 are inactive.”) the citation discloses the concept of changing the mapping of virtual processing units from cores 246 – 248 to cores 241 – 245, and after the change, the total number of virtual processing units (232 – 240) remain the same, with each has at least one processor, and all virtual processing units now run on cores 241 – 245, and cores 246 – 248 execute no instructions/not map to the previous virtual processor. Processor 256 could be switched to a sleep mode/off-park.
implementing the second mapping by executing at least one of the workloads using the virtual processor in accordance with the second mapping. (e.g. FIG. 2A, FIG. 2B, and [0051]: “As illustrated in the transition from FIG. 2A to FIG. 2B, virtual machine manager 230 may shift the loads from cores 246, 247, and 248 over to cores 241-245. As a result of shifting the loads and remapping the virtual processing units, cores 246, 247, and 248 may be executing no instructions.”) The citation discloses the loads from cores 246 – 248 is shifted to cores 241 – 245, and cores 246 – 248 execute no instruction, so it implies that all of the virtual processors previously execute on cores 246 – 248 are now executes on cores 241 – 245, as the results of remapping or second mapping.
Bieswanger does not clearly teach that generating a set of performance indicators for the first physical CPU by executing a performance test on the first physical CPU core, wherein the set of performance indicators is generated based on evaluating at least one of performance logs or alert logs indicating historical performance of the first physical CPU core; based on the set of performance indicators, determining the first physical CPU core is to be off-parked,
However, PACKER teaches generating a set of performance indicators for the first physical CPU by executing a performance test on the first physical CPU core (e.g. [0028]: “Further, in certain such aspects, the code in the ROM 160 is customized for the pre-defined boot CPU (e.g., based on the CPU core type, CPU resources, etc.). For example, different CPUs or different clusters selected for boot may necessitate changes in the configuration parameters/resources during boot for the SoC. Accordingly, in certain aspects, the ROM 160 includes boot code specifically for the pre-defined boot CPU. As discussed above, in certain aspects, the pre-defined boot CPU, after the SoC 100 is manufactured, may not function properly. When the pre-defined boot CPU is malfunctioning, there is no method by which to properly boot the SoC 100.” and FIG. 2 and [0034]: “At 205, a test is run on a CPU core of the SoC. At 210, it is determined if the CPU core passes the test. If the CPU core passes the test, the process continues to 220. If the CPU core does not pass the test, the process continues to 215, where quality information indicating the CPU core has failed is stored. For example, a corresponding efuse of the CPU core in the efuse component 140 is blown indicating the CPU core as failed. The process then continues to 220.”) The citations disclose at [0028] the pre-defined boot CPU that responsible for booting the ROM 160 is malfunctioning, and the SoC 100 would not properly boot; at FIG. 2 and [0034] discloses the test is run on a CPU core to determine if the CPU core is malfunctioning or not.
based on the set of performance indicators, determining the physical CPU core is to be off-parked (e.g. [0038]: “The OS or other operations may utilize the quality information to make further decisions when operating the SoC 100, such as which CPU core to schedule for a task, etc. For example, the OS may not schedule tasks to CPU cores indicated as failing, regardless of information stored in status registers as discussed.” and [0040]: “For example, if the CPU cores 111 and 112 of cluster 110 fail, then the OS may direct the CPU cores 121 and 122 of cluster 120 to utilize the cache 115 for storage, though the cache 115 may normally only be utilized by cluster 110. In another example, if the CPU core 111 fails, for example, and has a dedicated cache, and CPU core 112 is still functional, the dedicated cache may be reallocated to CPU core 112. It should be noted that repurposing of resources between CPU cores may be done in any suitable manner, in addition to the illustrative examples discussed herein.”) The citation discloses after indicating that the cores fail the test, no tasks will be scheduled to that CPU cores/to be off-parked [0038], or the failure core will be set aside, as the resources is reallocated to other CPU cores [0040].
It would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to add the generating a set of performance indicators for the first physical CPU by executing a performance test on the first physical CPU core; based on the set of performance indicators, determining the physical CPU core is to be off-parked, as taught in PACKER’s invention into Bieswanger’s invention because the system can proactively identify underperforming cores and make informed decisions on CPU resource management. This combination enhances system reliability and efficiency by ensuring that only malfunctioning cores are removed from the virtual processor mapping, preventing performance degradation and minimizing the impact on workload execution.
However, Fejfar teaches wherein the set of performance indicators is generated based on evaluating at least one of performance logs or alert logs indicating historical performance of the first physical CPU core (e.g. 10 - Col 5, lines 53 – 57: “The safety-critical application 108a,b may respond to a received notification of a detected fault by logging the fault to a fault log (fault history) 124a,b associated with the specific core 104b,d on which the safety-critical application 108a,b is executing.” and 10 – Col 5, lines 66 – 67 and Col 6, lines 1 – 3: “As the system 100 builds a fault history for each processing core 104a-b of the MCP 102, each fault log 124a, b may be analyzed for optimal maintenance and certified operation of the MCP 102.”) The citation discloses the concept of gathering and recording fault logs or fault histories, for individual cores, and analyzes the historical fault data to identify issues with cores. The overall concept similar to the claim limitation of generation of performance indicators based on evaluating alert logs indicating historical performance of a physical CPU core.
It would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to add the wherein the set of performance indicators is generated based on evaluating at least one of performance logs or alert logs indicating historical performance of the first physical CPU core, as taught in Fejfar’s invention into Bieswanger’s invention because the additional features would enable the system more accurately identifies faults or issues with the cores, in which the system can have a better understanding of the CPU core performances, leading to better decisions on when to off-part the core and reassign workloads, reduce risk of CPU failure, ensure workloads are handled more efficiently, and improve overall system reliability and performance efficiency.
Regarding claim 2, Bieswanger, in view of PACKER and Fejfar, discloses the method of claim 1, and Bieswanger further teaches wherein the first physical CPU core is implemented by a host device, the host device comprising a virtual machine. (Bieswanger – e.g. FIG. 1 and [0023]: “Processors 140 and 150 may execute operating instructions for programs and applications run by users of system 100.” and [0024]: “Also as depicted in FIG. 1, system 100 may have a virtual machine manager 114, such as a hypervisor, that manages one or more virtual machines, such as virtual machine 108.”) The citation discloses at FIG. 1 and [0023] the system 100/host device, comprises the processors 140 and 150/physical CPU, and at [0024] discloses the virtual machine 108.
Regarding claim 3, Bieswanger, in view of PACKER and Fejfar, discloses the method of claim 2, and Bieswanger further teaches wherein the virtual processor is implemented by the virtual machine to execute workloads of the virtual machine. (e.g. FIG. 1, FIG. 2A, 2B and [0026]: “An operating system 112 of virtual machine 108 may process the instructions of applications 110. In processing the instructions of applications 110, cores 142, 143, 152, and 153 may comprise a core pool that system 100 uses to execute the instructions.”) The citation discloses at FIG. 1 and [0026] that the application 110/workload, is processed by the virtual machine, and at FIG. 2A and 2B discloses the virtual processing unit comprises virtual processors, which managed by VMM. As the VMM execute the VM, it implies that the virtual processors are utilized by the VM.
Regarding claim 5, Bieswanger, in view of PACKER and Fejfar, discloses the method of claim 1, and Bieswanger further teaches wherein the first logical CPU core represents a number of threads that can be executed by the first physical CPU core. (e.g. FIG. 2A and [0046]: “FIG. 2A depicts that core 241 is heavily loaded, which may correspond to executing a large number of instructions via numerous hardware threads, relative to the execution capability of core 241. For example, core 241 may be able to execute instructions via some number "n" of hardware threads, with 0 to n hardware threads being concurrently active based on the operation of core 241.”) The citation discloses processor 250 executes core 24, and core 241 can execute number or threads.
Regarding claim 6, Bieswanger, in view of PACKER and Fejfar, discloses the method of claim 1, and PACKER further teaches wherein executing the performance test comprises causing the first physical CPU core to execute a set of commands or instructions that generate CPU metrics for the first physical CPU core. (PACKER - e.g. FIG. 2 and [0034] At 205, a test is run on a CPU core of the SoC. At 210, it is determined if the CPU core passes the test. If the CPU core passes the test, the process continues to 220. If the CPU core does not pass the test, the process continues to 215, where quality information indicating the CPU core has failed is stored. For example, a corresponding efuse of the CPU core in the efuse component 140 is blown indicating the CPU core as failed. The process then continues to 220”) The citation discloses a test is run on a CPU core, which implies that CPU core execute a set of commands or instructions, and quality information/metric, that indicating the CPU core has failed is stored.
Regarding claim 7, Bieswanger, in view of PACKER and Fejfar, discloses the method of claim 1, and Fejfar further teaches wherein executing the performance test comprises accessing the at least one of the performance logs or alert logs for the first physical CPU core. (e.g. 10 – Col 5, lines 66 – 67 and Col 6, lines 1 – 3: “As the system 100 builds a fault history for each processing core 104a-b of the MCP 102, each fault log 124a, b may be analyzed for optimal maintenance and certified operation of the MCP 102.”) The citation discloses the analyzing of the fault log, and in order to analyze the log, the system needs access to log.
Regarding claim 11, Bieswanger, in view of PACKER and Fejfar, discloses the method of claim 1, and PACKER further teaches wherein determining the first physical CPU core is to be off-parked comprises comparing the set of performance indicators to a set of parameters indicating threshold values for the set of performance indicators. (PACKER – e.g. [0036]: “In certain aspects, at runtime of the SoC 100 (e.g., when the SoC 100 is powered on, reset, boots, etc.), the reset controller 130 of the SoC 100 checks the efuse component 140 for the quality information of each of the CPU cores 111, 112, 121, and 122 of the CPUSS 105 and determines which CPU core to use as the boot CPU for the SoC 100 based on the quality information. For example, the quality information may be checked in a some order, and the first CPU core with a suitable quality level (e.g., threshold level, indication of functionality, etc.) may be selected as the boot CPU.”) The citation discloses the quality information/performance indicators, is checked/compare, with threshold level that corresponding to the quality information.
Regarding claim 12, Bieswanger, in view of PACKER and Fejfar, discloses the method of claim 11, and PACKER further teaches wherein performance indicators in the set of performance indicators that exceed the threshold values indicate the first physical CPU core is currently defective. (PACKER – e.g. [0032]: “In certain aspects, after a SoC 100 is manufactured, each of the CPU cores 111, 112, 121, and 122 are quality screened (e.g., at the factory) using known CPU testing techniques (e.g., tests of whether the CPU and overall SoC meet target margins on voltage, temperature, current corner design, etc., tests that validate reliability of internal memories used in a CPU, etc.). Accordingly, the quality (e.g., whether the CPU core fails or not, whether certain resources used by the CPU core fail or not, etc.) of each CPU core is determined via the CPU testing. In certain aspects, the quality information of each of the CPU cores is stored in the SoC 100. For example, the quality information may be stored as a single bit for each CPU core that indicates whether the CPU core passes or fails screen, is available or not, etc. In certain aspects, the quality information is stored in a one-time programmable memory, such as by efuses of efuse component 140. In certain aspects, each efuse of the efuse component 140 corresponds to a particular CPU core/cluster. In some aspects, each efuse of the efuse component 140 is further associated with a memory (e.g., ROM, register, etc.) that includes an identifier of a particular CPU core/cluster. For example, in some aspects, each efuse may correspond to one bit, where a blown efuse (e.g., fuse bit =0) indicates the CPU core fails screening, and a no blown efuse (e.g., fuse bit =1) indicates the CPU core passes screening.”) The citation discloses the concept of CPU testing techniques that test the CPU meet target margins on voltage, temperature, and generates quality information and stored the quality information as a single bit, and using that bit to indicate the pass or fails/defective.
Regarding claim 13, Bieswanger, in view of PACKER and Fejfar, discloses the method of claim 1, and Bieswanger further teaches wherein the virtual processor is implemented by a virtual machine. (Bieswanger – e.g. FIG. 1 and [0023]: “Processors 140 and 150 may execute operating instructions for programs and applications run by users of system 100.” and [0024]: “Also as depicted in FIG. 1, system 100 may have a virtual machine manager 114, such as a hypervisor, that manages one or more virtual machines, such as virtual machine 108.”) The citation discloses at FIG. 1 and [0023] the system 100/host device, comprises the processors 140 and 150/physical CPU, and at [0024] discloses the virtual machine 108.
Regarding claim 16, the claim is a system claim that having similar limitations cited in claim 1. Thus, claim 16 is also rejected under the same rational as cited in the rejection of rejected claim 1.
Regarding claim 19, Bieswanger, in view of PACKER and Fejfar, discloses the system of claim 16, and Bieswanger further teaches wherein implementing the second mapping comprises: replacing the first mapping with the second mapping (e.g. FIG. 2A and FIG. 2B) The citation discloses at FIG. 2B is a new mapping of the system 200, of the old mapping of FIG. 2A.
Regarding claim 20, the claim is a device claim that having similar limitations cited in claim 1. Thus, claim 20 is also rejected under the same rational as cited in the rejection of rejected claim 1.
Regarding claim 21, the claim is a device claim that having similar limitations cited in claims 11 – 13. Thus, claim 21 is also rejected under the same rational as cited in the rejection of rejected claim 11 – 13.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Bieswanger, PACKER and Fejfar, in further view of Hearn et al. US Pub. No. US 20170090987 A1 (hereafter Hearn)
Regarding claim 4, Bieswanger, in view of PACKER and Fejfar, discloses the method of claim 2, and Bieswanger further teaches wherein the hypervisor manages the virtual machine. (Bieswanger - FIG. 1) Fig. 1 disclose the component VMM 114/Hypervisor manages the virtual machine 108.
Bieswanger, in view of PACKER and Fejfar, does not explicitly teach wherein the performance test is executed by a hypervisor of the host device.
However, Hearn teaches wherein the performance test is executed by a hypervisor of the host device ([0110]: “A hypervisor or operating system executed by the platform logic may run benchmark tests on the platform logic to collect the telemetry data indicating the topology of at least a portion of the platform logic.”) The citation discloses the platform logic/host device comprises the hypervisor, and the hypervisor runs benchmark tests/performance test.
It would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to add the wherein the performance test is executed by a hypervisor of the host device, as taught in Hearn’s invention into Bieswanger, PACKER and Fejfar’s invention because using a hypervisor for CPU performance testing would provide isolation, security, and scalability by running tests in controlled virtualized environments without affecting the host system. It also enables dynamic resource allocation, making testing more flexible and efficient across different hardware platform.
Claims 8, 9 are rejected under 35 U.S.C. 103 as being unpatentable over Bieswanger, PACKER and Fejfar, in further view of Surisetty et al. US Pub. No. US 20230135825 A1 (hereafter Surisetty)
Regarding claim 8, Bieswanger, in view of PACKER and Fejfar, discloses the method of claim 1, but does not explicitly teach wherein set of performance indicators comprises CPU metrics for the first physical CPU core, the CPU metrics comprising at least one of: availability; response time; or service time.
However, Surisetty teaches wherein set of performance indicators comprises CPU metrics for the first physical CPU core, the CPU metrics comprising at least one of: availability, response time; ([0028]: “CPU measurements (e.g., processor utilization, processing speed, number of cores, size of cache)”). The citation disclose the CPU measurements/CPU metrics comprise processor utilization/availability and processing speed/response time.
or service time.
It would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to add the wherein set of performance indicators comprises CPU metrics for the first physical CPU core, the CPU metrics comprising at least one of: availability; response time; or service time, as taught in Reynolds’s invention into Bieswanger, PACKER and Fejfar’s invention because by providing response time, or service time, etc., the system can make precise and accurate evaluation of the current CPU’s condition. Therefore, the system can detect performance degradation more accurately, and ensuring that malfunctioning cores are put on hold only when necessary, and preventing unnecessary remapping.
Regarding claim 9, Bieswanger, PACKER, Fejfar, and Surisetty, discloses the method of claim 8, and Surisetty further teaches wherein the CPU metrics further comprise at least one of: channel capacity, bandwidth; (Surisetty - [0028]: “CPU measurements (e.g., processor utilization, processing speed, number of cores, size of cache)”). The citation disclose the CPU measurements/CPU metrics comprise, number of cores/channel capacity, size of cache/bandwidth.
or relative efficiency;
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Bieswanger, PACKER and Fejfar, in further view of Hyde et al. US Pub. No. US 20210300425 A1 (hereafter Hyde)
Regarding claim 10, Bieswanger, in view of PACKER and Fejfar, discloses the method of claim 1, but does not explicitly teach wherein set of performance indicators comprises at least one of: a number of errors reported for the first physical CPU core; a frequency of errors reported for the first physical CPU core; or a length of the time the first physical CPU core has been in use.
However, Reynolds teaches wherein set of performance indicators comprises at least one of: a number of errors reported for the first physical CPU core; ([0118]: “As an example, the monitoring circuitry 430 may evaluate aspects of the CPU 406 while operating (e.g., clock error reporting, voltage monitoring, error collection, clock frequency monitoring, etc.).”) the citation discloses the monitoring circuitry evaluates aspects of CPU/performance indicator while operating, which includes clock error reporting/number of errors reported, and error collection and clock frequency monitoring/frequency of errors reported.
a frequency of errors reported for the first physical CPU core; or a length of the time the first physical CPU core has been in use.
It would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to add the wherein set of performance indicators comprises at least one of: a number of errors reported for the first physical CPU core; a frequency of errors reported for the first physical CPU core; or a length of the time the first physical CPU core has been in use, as taught in Reynolds’s invention into Bieswanger, PACKER and Fejfar’s invention because by using the performance indicator, such as number of errors, or frequency of errors, etc., the system can make precise and accurate evaluation of the current CPU’s condition. Therefore, the system can detect performance degradation more accurately, and ensuring that malfunctioning cores are put on hold only when necessary, and preventing unnecessary remapping.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Bieswanger, PACKER and Fejfar, in further view of Chavez et al. US Pub. No. US 20190041824 A1 (hereafter Chavez)
Regarding claim 18, Bieswanger, in view of PACKER and Fejfar, discloses the system of claim 16, but does not explicitly teach wherein off-parking the physical CPU core comprises placing the physical CPU core into an emergency role such that the off-parked physical CPU core receives workloads when no other physical CPU cores are available.
However, Chavez teaches wherein off-parking the physical CPU core comprises placing the physical CPU core into an emergency role such that the off-parked physical CPU core receives workloads when no other physical CPU cores are available. ([0101]: “In an example, the CPU 906 may have a low or high power mode, which may be activated or deactivated instead of turning the CPU 906 off or on. This example may be useful in cases where the CPU 906 is put in a low power state instead of being powered off to reduce thermal output, such as when the CPU 906 may be needed to be activated quickly.”) The citation discloses the CPU can be placed in activate or deactivate instead of turning it off completely, and the CPU can be activated when necessary.
It would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to add the wherein off-parking the physical CPU core comprises placing the physical CPU core into an emergency role such that the off-parked physical CPU core receives workloads when no other physical CPU cores are available, as taught in Reynolds’s invention into Bieswanger, PACKER and Fejfar’s invention because by enabling the emergency role features of the malfunctioning CPU core, instead of entirely deactivated, can still be utilized as a last resource when no other cores are available, this would improve the system reliability and workload continuity by preventing complete performance loss when all functional cores are occupied, and ensuring critical operations can proceed as needed.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Bieswanger, PACKER and Fejfar, in further view of FUKUTOMI et al. US Pub. No. US 20190041824 A1 (hereafter FUKUTOMI)
Regarding claim 22, Bieswanger, in view of PACKER and Fejfar, discloses the device of claim 22, wherein determining the at least one performance indicator meets or exceeds the threshold value but does not explicitly teach comprises determining the at least one performance indicator meets or exceeds a count of errors defined for a lifetime of the first physical CPU core.
However, FUKUTOMI teaches comprises determining the at least one performance indicator meets or exceeds a count of errors defined for a lifetime of the component. (e.g. FIG. 5, [0045] – [0054], and claim 11: “wherein the second memory module is configured to count a number of errors that occur in the second memory module, and notify the processor when the number of errors exceeds a predetermined number, and the processor is configured to, when the processor is notified that the number of errors has exceeded the predetermined number, stop storing new data in the second memory module, write data cached in a cache in the processor in the third memory module, and display a prompt to replace the second memory module.”) The citations disclose the concept when a number of errors exceeds a predetermined number, the system indicate that the memory module would need to be replace. This would read on the concept of the claim, as the “a count of errors defined for a lifetime of the first physical CPU core" could be interpreted as "a number of errors that can occur before the CPU need to be replaced or to be indicated as defective". Therefore, by applying the concept from the reference, and replace the component with the physical CPU component from Bieswanger and PACKER, a person with ordinary skills in the art would be able to come up with the claim invention.
It would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to add the comprises determining the at least one performance indictor meets or exceeds a count of errors defined for a lifetime of the component, as taught in FUKUTOMI’s invention into Bieswanger, PACKER and Fejfar’s invention because by determining the count of errors exceed the lifetime threshold value of the component, the system can make precise and accurate evaluation of the current component’s condition. Therefore, the system can detect the component failure more accurately, and ensuring that malfunctioning component are disable or being replaced as needed and workloads are handled more efficiently.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Bieswanger, PACKER and Fejfar, in further view of Chang et al. US Pub. No. US 20190041824 A1 (hereafter Chang)
Regarding claim 23, Bieswanger, in view of PACKER and Fejfar, discloses the method of claim 1, but does not explicitly teach wherein implementing the second mapping further comprises preventing, by an operating system kernel of the computing device, scheduling of application threads on the first physical CPU core while the first physical CPU core is off- parked.
However, Chang teaches wherein implementing the second mapping further comprises preventing, by an operating system kernel of the computing device, scheduling of application threads on the first physical CPU core while the first physical CPU core is off- parked. (e.g. [0007]: “To transition into the clearance mode, the kernel module is further configured to: migrate work from the target processor core to one or more other processor cores in the active mode in the computing system; and configure the computing system to prevent task assignment to the target processor core. While the target processor core is in the clearance mode, the target processor core is maintained in an online idle state in which the target processor core performs no work.” and [0022]: “when a processor core is in the clearance mode, the processor core is removed from the scheduling configuration 220 such that it is not usable to the scheduling module 140. When there are new tasks to be assigned, the scheduling module 140 cannot schedule these new tasks to a processor core in the clearance mode, thus preventing waking up the processor core from the clearance mode.”) The citations disclose when a target processor is in clearance mode/performs no work/off-park, the kernel module prevent tasks to be assigned to the target processor.
It would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to add the wherein implementing the second mapping further comprises preventing, by an operating system kernel of the computing device, scheduling of application threads on the first physical CPU core while the first physical CPU core is off- parked, as taught in Chang’s invention into Bieswanger, PACKER and Fejfar’s invention because the additional feature enables the system to be fast response, efficient power usage, improved performance, and ensuring that workloads are handled more efficiently. (Chang [0008])
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20020184445 A1: teaches when the system, during testing of multiple CPU cores, one CPU is found to be defective or otherwise unusable, the kernel may be configured to maintain the multiple CPU cores in the 1T state, where one CPU is an active CPU, which has access to both cache memory partitions of the active CPU and the defective CPU, and the defective CPU is inactive.
US 20220342739 A1: A method for determining a faulty computing core in a multi-core processor, applied to an electronic device configured with a multi-core processor. The method includes: determining a computing core corresponding to each of N running exceptions, where the running exception is caused by an exception that occurs when any computing core in the plurality of computing cores executes the program instructions; and when a quantity of running exceptions corresponding to the first computing core in the N running exceptions is greater than or equal to M, determining that the first computing core is a faulty computing core, where M is a preset value.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Examiner has cited particular columns/paragraphs/sections and line numbers in the references applied and not relied upon to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
When responding to the Office action, applicant is advised to clearly point out the patentable novelty the claims present in view of the state of the art disclosed by the reference(s) cited or the objections made. A showing of how the amendments avoid such references or objections must also be present. See 37 C.F.R. 1.111(c).
When responding to this Office action, applicant is advised to provide the line and page numbers in the application and/or reference(s) cited to assist in locating the appropriate paragraphs
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/TUAN M NGUYEN/Examiner, Art Unit 2198
/PIERRE VITAL/Supervisory Patent Examiner, Art Unit 2198
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