DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
According to paper filed January 5th 2026, claims 1-20 are pending for examination with an effective filing date of July 5th 2022.
By way of the present Amendment, claims 1, 9, 14, and 20 are amended. Claims 5-8 and 18 are canceled, no claim is added. Claim rejections under 35 USC103 and 35 USC 112(b) are withdrawn.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 USC 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1:
Claims 1-13 do not fall within at least one of the four categories of patent eligible subject matter because the claims are directed to an abstract idea. The claims as a whole, considering all claim elements both individually and in combination, do not amount to significantly more than an abstract idea.
The claims do not include additional elements, particularly, hardware elements, that are sufficient to amount to significantly more than an abstract idea. Claims 1-13 recite a method of obtaining, determining, and generating steps, which merely provide instructions to implement an abstract idea and do not integrate them into a practical application.
Claims 14-19 directed to an apparatus and claim 20 is directed to a computer program product. Therefore, each of these claims is directed to one of the four statutory categories of patent eligible subject matter.
Step 2A Prong 1:
Claims 1, 14, 20 recite:
“determining a second order of the plurality of qubits that is different from the first order of the plurality of qubits; wherein said determining the second order is based on an objective function, the objective function is configured to provide scores based on respective lengths of circuit components in graphical representations of the quantum circuit or portions thereof, wherein the objective function is configured to yield different scores for different orders of the plurality of qubits”; determining an order of quantum qubits is an evaluation that can be carried out by a human in the mind or with pen and paper, and is thus a mental process.
Step 2A Prong 2:
This judicial exception is not integrated into a practical application because the additional elements are as follows:
Claims 1, 14, 20 recite:
“obtaining a representation of a quantum circuit, the quantum circuit is configured to manipulate a plurality of qubits over a plurality of cycles, the representation defining, explicitly or implicitly, a first order of the plurality of qubits; generating a graphical representation of the quantum circuit or portion thereof, the graphical representation displaying the plurality of qubits in accordance with the second order of the plurality of qubits; and displaying the graphical representation of the quantum circuit or portion thereof”; this limitation amounts to data gathering and insignificant extra solution activity, as per MPEP 2106.05(g).
Claim 11 recites:
“wherein the first order of the plurality of qubits is obtained from a logical compiler that outputted, as part of a compilation process, the representation of the quantum circuit”; this limitation fails to integrate the judicial exception into a practical application, as per MPEP 2106.5(f).
Claim 12 recites:
“wherein the first order is implicitly defined by a naming of the plurality of qubits provided in the representation of the quantum circuit”; this limitation fails to integrate the judicial exception into a practical application, as per MPEP 2106.5(f).
Claim 13 recites:
“displaying a functional-level layer in accordance with the second order”; this limitation fails to
integrate the judicial exception into a practical application, as per MPEP 2106.5(f).
“displaying a gate-level layer of the functional element, wherein the gate-level layer of the functional element is displayed using a third order of the plurality of qubits or portion thereof, the third order is inconsistent with the second order”; this limitation fails to integrate the judicial exception into a practical application, as per MPEP 2106.5(f).
Claim 14 recites:
“an apparatus comprising a processor and coupled memory”; this limitation amounts to applying the abstract idea on generic computer components, as per MPEP 2106.05(f).
Claim 19 recites:
“displaying a functional-level layer in accordance with the second order”; this limitation fails to integrate the judicial exception into a practical application, as per MPEP 2106.5(f).
“display a gate-level layer of the functional element, wherein the gate-level layer of the functional element is displayed using a third order of the plurality of qubits or portion thereof, the third order is inconsistent with the second order”; this limitation fails to integrate the judicial exception into a practical application, as per MPEP 2106.5(f).
Claim 20 recites:
“a computer program product comprising a non-transitory computer readable medium retaining program instruction”; this limitation amounts to nothing more than an instruction to apply the abstract idea using a generic computer as per MPEP 2106.05(f).
Step 2B:
The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements are as follows:
Claims 1, 14, 20 recite:
“obtaining a representation of a quantum circuit, the quantum circuit is configured to manipulate a
plurality of qubits over a plurality of cycles, the representation defining, explicitly or implicitly, a first
order of the plurality of qubits; generating a graphical representation of the quantum circuit or portion thereof, the graphical representation displaying the plurality of qubits in accordance with the second order of the plurality of qubits; and displaying the graphical representation of the quantum circuit or portion thereof”; this limitation amounts to data gathering and insignificant extra solution activity, as per MPEP 2106.05(d)(II).
Claim 14 recites:
“an apparatus comprising a processor and coupled memory”; this limitation amounts to well-understood, routine, and conventional activity, as per MPEP 2106.05(d), and does not add significantly more than an abstract idea.
Claim 20 recites:
“a computer program product comprising a non-transitory computer readable medium retaining program instruction”; this limitation amounts to well-understood, routine, and conventional activity, as per MPEP 2106.05(d), and does not add significantly more than an abstract idea.
Dependent Claims
Claims 2-7, 9-13 and 15-19 are also rejected under 35 USC 101 for the following reasons:
Claims 2 and 15 recite:
“said determining the second order comprises solving an optimization problem with respect to the objective function”; this limitation amounts to this limitation amounts to well-understood, routine, and conventional activity, as per MPEP 2106.05(d), and cannot amount to significantly more than the judicial exception itself.
Claims 3 and 16 recite:
“wherein the graphical representation comprises a gate-level layer of the quantum circuit, wherein the circuit components comprise quantum gates, wherein the lengths of the quantum gates comprise, for each quantum gate, a distance between two farthest qubits that are manipulated by the quantum gate”; this limitation amounts to
Claims 4 and 17 recite:
“wherein the graphical representation comprises a functional-level layer of the quantum circuit, wherein the circuit components comprise functional blocks, wherein the lengths of the functional blocks comprise, for each functional block, a distance between two farthest qubits that are manipulated by the functional block”; this limitation amounts to this limitation amounts to well-understood, routine, and conventional activity, as per MPEP 2106.05(d), and cannot amount to significantly more than the judicial exception itself.
Claims 5 and 18 recite:
“wherein the graphical representation comprises two disjoint sections, wherein the objective function comprises a local objective function, wherein the local objective function is applied to at least one of the two disjoint sections, wherein the two disjoint sections comprise first and second sections, the method further comprising implementing a switching scheme between the first and second sections”; this limitation amounts to this limitation amounts to well-understood, routine, and conventional activity, as per MPEP 2106.05(d), and cannot amount to significantly more than the judicial exception itself.
Claim 6 recites:
“wherein the first section and the second section are determined so that there is no circuit component that is characterized in having a first portion thereof in the first section and a second portion thereof in the second section unless a relative order of qubits utilized by the circuit component is not affected by the switching scheme”; this limitation amounts to this limitation amounts to well-understood, routine, and conventional activity, as per MPEP 2106.05(d), and cannot amount to significantly more than the judicial exception itself.
Claim 7 recites:
“wherein the switching scheme comprises: utilizing the second order of the plurality of qubits for the first section, the second order is determined based on the local objective function and with respect to the first section; and utilizing a third order of the plurality of qubits for the second section, the third order is determined based on the local objective function and with respect to the second section”; this limitation amounts to this limitation amounts to well-understood, routine, and conventional activity, as per MPEP 2106.05(d), and cannot amount to significantly more than the judicial exception itself.
Claim 9 recites:
“wherein the switching scheme comprises: utilizing the second order of the plurality of qubits for the first section, the second order is determined based on the local objective function and with respect to the first section; and utilizing a third order of the plurality of qubits for the second section, the third order is determined based on the local objective function and with respect to the second section”; this limitation amounts to this limitation amounts to well-understood, routine, and conventional activity, as per MPEP 2106.05(d), and cannot amount to significantly more than the judicial exception itself.
Claim 10 recites:
“wherein the objective function comprises a global objective function, wherein the global objective function is applied to a layer of the graphical representation in its entirety”; this limitation amounts to this limitation amounts to well-understood, routine, and conventional activity, as per MPEP 2106.05(d), and cannot amount to significantly more than the judicial exception itself.
Claim 11 recites:
“wherein the first order of the plurality of qubits is obtained from a logical compiler that outputted, as part of a compilation process, the representation of the quantum circuit”; this limitation amounts to this limitation amounts to well-understood, routine, and conventional activity, as per MPEP 2106.05(d), and cannot amount to significantly more than the judicial exception itself.
Claim 12 recites:
“wherein the first order is implicitly defined by a naming of the plurality of qubits provided in the representation of the quantum circuit”; this limitation amounts to this limitation amounts to well-understood, routine, and conventional activity, as per MPEP 2106.05(d), and cannot amount to significantly more than the judicial exception itself.
Claim 13 recites:
“displaying a functional-level layer in accordance with the second order”; this limitation amounts to well-understood, routine, and conventional activity, as per MPEP 2106.05(d), and cannot amount to significantly more than the judicial exception itself.
“displaying a gate-level layer of the functional element, wherein the gate-level layer of the functional element is displayed using a third order of the plurality of qubits or portion thereof, the third order is inconsistent with the second order”; this limitation amounts to well-understood, routine, and conventional activity, as per MPEP 2106.05(d), and cannot amount to significantly more than the judicial exception itself.
Claim 19 recites:
“displaying a functional-level layer in accordance with the second order”; this limitation amounts to well-understood, routine, and conventional activity as per MPEP 2106.05(d), and cannot amount to significantly more than the judicial exception itself.
“display a gate-level layer of the functional element, wherein the gate-level layer of the functional element is displayed using a third order of the plurality of qubits or portion thereof, the third order is inconsistent with the second order”; this limitation amounts to well-understood, routine, and conventional activity as per MPEP 2106.05(d), and cannot amount to significantly more than the judicial exception itself.
Response to Arguments
Applicant's arguments filed January 5th 2026 have been fully considered but they are not persuasive.
With respect to claim rejections under 35 USC 101, applicant argues that “no explanation was provided regarding Claim 8 (see page 6 below, and page 8), and Applicants infers that such claim was not rejected on this basis. Furthermore, Applicant submits that the subject matter of Claim 8 is patent eligible. As all independent claims now recite the subject matter of Claim 8, all claims are now directed towards patent-eligible subject matter, the rejection is believed to be moot.” Said argument is not persuasive.
It is noted that the subject matters of dependent claims 5-8 are incorporated into independent claims 1, 14, and 20. Accordingly, claim rejections under 35 USC 103 are withdrawn. However, applicant fails to address the claim eligibility rejections. As a result, claim rejections under 35 USC 101 remain intact in the present Office action.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RUAY HO whose telephone number is (571)272-6088. The examiner can normally be reached Monday to Friday 9am - 5pm.
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/Ruay Ho/Primary Patent Examiner, Art Unit 2126