DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/05/2025 has been entered.
Response to Amendment
This office action is responsive to amendment filed on 11/10/2025. Claims 1-3. 6-8, 10-13, 17-18, and 20-21 are pending. The amendments have overcome the specification, claim objections, and rejections under 35 U.S.C. 112(a) and 112(b), as set forth in previous office action.
Response to Arguments
In response to applicant’s argument regarding rejection under 35 U.S.C. 101 on page 11-12, that the claimed subject matter is not directed to mathematical concepts or mental processes. “Rather, such limitations describes “performing, by one or more processor, elliptic curve cryptography (ECC) operations for an approach to public key cryptography based on algebraic structure of elliptic curves over finite fields by combining a key agreement with a symmetric encryption scheme” … certainly only is based on or involves a mathematical concept and therefore does not recite a mathematical concept”.
Examiner respectfully disagrees because the claim explicitly steps of adding using binary addition to generate a sum value, determining correction term using leading bits of the sum value and performing modular addition to generate a modular sum. Such limitation covers the mathematical concept of the abstract idea, and merely reciting the steps of receiving and using a lookup table do not integrate the judicial exception into a practical application. See rejection below for details. Furthermore, the step of performing ECC operations for an approach to public key cryptography … with a symmetric encryption scheme is recited as merely generally linking the use of the judicial exception into a particular technological environment or field of use, such as cryptography.
Applicant further asserted on page 12, “The following elements are concepts that cannot be practically performed in the human mind (including an observation, evaluation, judgment, opinion) and, accordingly, are not directed towards mental processes: "performing, by one or more processors, elliptic curve cryptography (ECC) operations for an approach to public-key cryptography based on algebraic structure of elliptic curves over finite fields by combining a key agreement with a symmetric encryption scheme, the ECC operations comprising: receiving, by one or more processors, a plurality of first operand values, wherein the plurality of first operand values are integer values; adding, by a hardware binary adder with a reduction tree unit, using binary addition, the plurality of first operand values, resulting in a sum value;… and performing, by a hardware modular adder comprising a second hardware binary adder and selector logic, a modular addition of the sum value and the single combined modular correction term, resulting in a modular sum of the plurality of first operand values."
Examiner respectfully disagrees because while some limitations, such as one or more processor, a hardware binary adder with a reduction tree unit, a hardware modular adder comprising a second hardware binary adder and selector logic are not characterized as abstract idea under step 2A prong one, but these elements are characterized as additional elements under step 2A prong two and such elements are recited at a high level of generality, e.g., computer components performing computer functions and amount to no more than mere instructions to apply the judicial exception using computer components (see MPEP 2106.05(f)). For example, having a binary adder to perform binary addition, having a modular adder to perform modular addition. Thus, such limitations amount to merely apply the math using computer components.
Applicant further asserted on page 13, “Applicant respectfully asserts that claims 1, 13, and 20 include additional elements by implementing a particular machine that is integral to the claim by, at least, utilizing the steps of "adding, by a hardware binary adder with a reduction tree unit, using binary addition, the plurality of first operand values, resulting in a sum value; and performing, by a hardware modular adder comprising a second hardware binary adder and selector logic, a modular addition of the sum value and the single combined modular correction term, resulting in a modular sum of the plurality of first operand values."
Examiner respectfully disagrees because the claim does not recite a particular machine, but rather recite additional elements at a high level of generality that amounts to no more than mere instructions to apply the judicial exception using computer component, such as a hardware binary adder performing binary addition, a hardware modular adder performs modular addition. Furthermore, the claim recites a reduction tree unit, but does not link the reduction tree unit to perform any function. Figure 6 illustrates a binary adder 404 includes a reduction tree 602 and binary adder 604, so the limitation “a hardware binary adder with a reduction tree unit” is interpreted as a hardware binary adder includes a reduction tree unit, wherein the hardware binary adder performs the binary addition. According, the claim merely recites a reduction tree unit, a second binary adder, select logic without performing any function. Thus, such limitation does not recite additional elements as a particular machine. Moreover, the recited second binary adder and select logic are also recited at a high level of generality, e.g., computer components performing computer functions, see at least [0055] describes the arithmetic operation for modular addition operation that requires binary addition and selection R1 or R2 as result based on selection whether R2 is less than or equal or greater than 0. Thus, the binary adder and select logic are amount no more than mere instructions to apply the judicial exception using computer components.
Applicant further asserted on page 13, “The “proposed concept may increase execution speed of modular operation - e.g. add and multiple - significantly when compared to existing technologies" by "using a 'carry save adder' [(e.g., reduction tree (CSA))] unit, [and] a binary adder,… only 3 machine cycles may be sufficient to perform a multi-input modular add operation for wide-sized integer values" "[c]ompared to conventional modular operation designs with typically 30 cycles, the proposed solution may be five times faster" and "the hardware overhead may be small since the reduction tree of the multiplier may be used (Current Office Action, [0015], [0018] & Figure 8).”
Examiner respectfully disagrees because MPEP 2106.04(d)(1) recites “if the specification sets forth an improvement in technology, the claim must be evaluated to ensure that the claim itself reflects the disclosed improvement.” and as asserted by the applicant above, the 3 machine cycles to perform multi-input modular add operation is achieved by using a carry save adder (e.g., a reduction tree unit). However, the claim 1 merely recites “adding, by a hardware binary adder with a reduction tree unit, using binary addition, the plurality of first operand values”, and figure 6 illustrates a reduction tree unit 602 and a binary adder 604. Thus, the adding operation using binary addition is performed by the binary adder (e.g., 604). Accordingly, the claim itself fails to reflect the improvement since the reduction tree unit is merely recited as a computer component without performing any function. In other words, if the improvement is achieved by using a carry save adder as asserted by the applicant, then the claim must reflects how having the carry save adder would achieve such improvement.
Applicant further asserted on page 13-14 that claims 1, 13, and 20 integrate any recited judicial exception into a practical application by performing ECC as ECC allows smaller keys compare to non-EC cryptography (e.g., based on plain finite field) and asserted that the quoted elements reflect an improvement in the functioning of a computer or technology because at least ECC allows smaller keys compared to non-ECC cryptography.
Examiner respectfully disagrees because the limitation of performing ECC operation for an approach to public-key cryptography based on algebraic structure of elliptic curve over finite fields by combining a key agreement with a symmetric encryption scheme recited in the claim is mere generally linking the use of the judicial exception into a particular technological environment or field of use, such as cryptography. Thus, such limitation fails to integrate the judicial exception into a practical application under step 2A prong two. Furthermore, any arguably improvements, such as allowing smaller keys compared to non-EC cryptography, is a direct consequence of performing the mathematical operations to perform elliptic curve cryptography (ECC) operations. See MPEP 2106.05(a) “It is important to note, the judicial exception alone cannot provide the improvement. The improvement can be provided by one or more additional elements.”. Thus, the mathematical of performing modular operations in the ECC operations alone cannot provide the improvement. Also see [0014] describes the concept of using binary addition instead of modular addition, such that when adding n operands, instead of performing n binary additions, each followed by a modular reduction, the solution proposes to do n binary additions followed by a single modular reduction, which increases the speed of binary execution significantly. Thus, any arguably improvement is a result of using binary additions followed by single modular reduction operations when adding n operands.
Applicant further asserted on page 15, “the claims are clearly directed to adding a specific limitation other than what is well-understood, routine, and conventional in the field, or adding unconventional steps that confine the claims to a particular useful application that improves the functionality of a computing device, and provides an improvement to the particular technological field of elliptic curve cryptography (ECC)”
Examiner respectfully disagrees because merely reciting the limitation of performing ECC operations does not integrate the judicial exception into a practical application under step 2A prong two or provide significantly more under step 2B because such ECC operations include the performance of mathematical concept, such as using binary addition, determining correction term and modular addition. Furthermore, even though the limitations are neither widely prevalent nor in common use in the relevant field, such limitations of using binary addition, determining correction term, and performing a modular addition are characterized as the abstract idea under step 2A prong one, MPEP 2106.04(I) “The Supreme Court’s decisions make it clear that judicial exceptions need not be old or long-prevalent, and that even newly discovered or novel judicial exceptions are still exceptions”. In other words, limitations that are not well-understood, routine, and conventional in the field are the abstract idea, and a new abstract idea is still an abstract idea. Furthermore, as explained above, any arguably improvement is a direct consequence of performing the abstract idea as recited in the claim that includes the steps of adding using binary addition, determining a single combined modular correction term, and performing a modular addition.
Claim Objections
Claim 21 is objected to because of the following informalities:
Claim 21 line 2 “the modular adder” should be “the hardware modular adder” as antecedently recited in claim 1 line 14.
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-3, 6-8, 10-13, 17-18, and 20-21 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Claim 1 recites a computer implemented method for modular operation.
Under Prong One of Step 2A of the USPTO current eligibility guidance (MPEP 2106), the claim recites a method comprising performing elliptic curve cryptography ECC operations comprising: the plurality of first operand values are integer values; adding, using binary addition, the plurality of first operand values resulting in a sum value; determining a single combined modular correction term for a binary sum of all operand values based on (i) leading bits of the sum value and (ii) by using a lookup table that gives a modulus number represented by the leading bits of the sum value; and performing a modular addition of the sum value and the single combined modular correction term, resulting in a modular sum of the plurality of first operand values. Such limitations of adding using binary addition, determining a single combined modular correction term, and performing a modular addition cover mathematical calculations, relationship, and/or formula (see at least figure 1 illustrating steps 102-108 for modular addition of a plurality of operands [0071-0073]. Also see [0032] describes the ECC operations includes addition and multiplication operations). The limitation of using a lookup table to give a modulus number, under broadest reasonable interpretation, cover the performance of limitation using pen and paper, such that one of ordinary skill in the art can create a table includes a plurality of precomputed values and select an entry based on an input. Therefore, the claim includes limitations that fall within the “Mathematical Concepts / Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Under Prong Two of Step 2A, this judicial exception is not integrated into a practical application. The claim recites the additional elements, such as a computer implemented method comprising receiving a plurality of first operand values, one or more processors, a hardware binary adder with a reduction tree unit, and a hardware modular adder comprising a second hardware binary adder and selector. However, these elements are recited at a high level of generality, e.g., as computer components performing computer functions of processing data and the step of receiving a plurality of first operand values is at most considered as insignificant extra solution activity because such limitation is mere data gathering. Furthermore, the limitation of performing elliptic curve cryptography operations for an approach to public-key cryptography based on algebraic structure of elliptic curves over finite fields by combining a key agreement with a symmetric encryption scheme can also be considered as an additional element, wherein such limitation is recited as mere generally linking the use of the judicial exception into a technological environment or field of use, such as cryptography. Moreover, the limitation of using a lookup table can also be considered as insignificant extra solution activity (e.g., additional element). Accordingly, such additional elements fail to provide a meaningful limitation on the claim invention, and amount to no more than mere instructions to apply the exception using a computer.
Under Step 2B, as discussed with respect to Prong Two of Step 2A, the additional elements in the claim amount no more than mere instructions to apply the exception using a computer. The same conclusion is reached in step 2B, i.e., mere instruction to apply an exception on a generic element cannot integrate a judicial exception into a practical application at step 2A or provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception. The steps of receiving the plurality of first operand values and using lookup table are considered to be insignificant extra-solution activity in step 2A, and are determined to be well-understood, routine, conventional activity in the field. Court decisions cited in MPEP 2106.05(d)(II) section (i), indicate that mere receiving or transmitting data over a network, is well-understood, routing, conventional function when it is claimed in a merely generic manner. Also see at least Hennessy, John L., et al. Computer Architecture: A Quantitative Approach, Elsevier Science & Technology, 2014. ProQuest Ebook Central, page 464 figure 5.35 illustrate a page table that stores data and receiving an address as input to generate a corresponding output. Thus, the additional element fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claims 2-3 further recite wherein said sum value S is represented in a redundant number form, wherein said redundant number form is a reduced-radix form. Such limitations cover mathematical calculations, relationship, and/or formula, such as mere format representation of a number (see at least [0060]). The claims do not recite additional elements that would integrate the judicial exception into a practical application under step 2A prong two or provide the additional element to ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 6 further recites performing a binary multiplication of second integer values resulting in a binary product, wherein the binary product is represented by a plurality of adjacent words of a predefined number of bits; and using a plurality of coarse-grained modular correction terms as the received plurality of first operand values, producing a result of a modular multiply operation. Such limitations cover mathematical calculations, relationship, and/or formula, such as performing modular multiplication (see at least figure 2 illustrates step 202-206). The claims do not recite additional elements that would integrate the judicial exception into a practical application under step 2A prong two or provide the additional element to ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claims 7-8 further recite wherein the redundant number form is a reduced-radix form. wherein the redundant number form is a reduced-radix form. Such limitations cover mathematical calculations, relationship, and/or formula, such as mere format representation of a number (see at least [0060]). The claims do not recite additional elements that would integrate the judicial exception into a practical application under step 2A prong two or provide the additional element to ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 10 further recites wherein the plurality of first operand values originate from a Solinas reduction operation. Such limitations cover mathematical calculations, relationship, and/or formula, such as describing the plurality of first operands value originated from reduction operations. The claims do not recite additional elements that would integrate the judicial exception into a practical application under step 2A prong two or provide the additional element to ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 11 further recites wherein the second integer values are each comprises an integer value having a number of bits between 255 bits and 521 bits. Such limitations cover mathematical calculations, relationship, and/or formula, such as describing size of integer values. The claims do not recite additional elements that would integrate the judicial exception into a practical application under step 2A prong two or provide the additional element to ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 12 further recites wherein the plurality of first operand values are operand values for elliptic curve operations. Such limitations cover mathematical calculations, relationship, and/or formula, such as data being performed for elliptic curve operation. The claims do not recite additional elements that would integrate the judicial exception into a practical application under step 2A prong two or provide the additional element to ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 21 further recites inputting, by one or more processors, a sum vector to the modular adder as additional input with single combined modular correction term. Such step of inputting a sum vector as additional element with single combined modular correction term is at most considered as insignificant extra solution activity (e.g., mere data gathering/transmitting), which is determined to be well-understood, routine and conventional under step 2B (see MPEP 2106.05(d)(II)(i) Receiving or transmitting data over a network). Furthermore, as explained above, one or more processors and the modular adder are recited at a high level of generality, e.g., computer components performing computer functions, which amount to no more than instructions to apply the judicial exception using computer components. Thus, the claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
claims 13 recites apparatus claim that would practice the method claim 1. Thus, it is rejected for the same reasons. The claim recites additional elements, such as a computer system comprising a processor set; one or more computer-readable storage media; and program instructions stored on the one or more computer-readable storage media to cause the processor set to perform operations. However, such additional elements are recited at a high level of generality, e.g., computer components performing computer functions such as storing and executing instructions. Thus, such additional elements fail to provide a meaningful limitation on the claim invention, and amount to no more than mere instructions to apply the exception using computer components and therefore does not integrate the judicial exception into a practical application under step 2A prong one or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claims are not patent-eligible under 35 U.S.C. 101.
Claim 17 recites the operations further comprise: generating an output as a sum and a carry vector pair, wherein the sum comprises an identical bit-width as the plurality of first operand values, and the carry comprises a predefined number carry bits. Such limitations cover mathematical calculations, relationship, and/or formula, such as data being performed addition operation. The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 18 recites the operations further comprise: binary adding the sum and the carry vector pair and the single combined modular correction term, wherein the single combined modular correction term is determined based on the sum and the carry vector pair; and determining the modular sum of the plurality of first operand values. Such limitations cover mathematical calculations, relationship, and/or formula, such as performing modular addition as explained in [0078]. The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 20 recites product claim having similar limitation as the apparatus claim 13. Thus, it is rejected for the same reasons.
Conclusion
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/HUY DUONG/Examiner, Art Unit 2182 (571)272-2764
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182