Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/22/2025 has been entered.
Response to Arguments
Applicant's arguments filed 11/26/2025 have been fully considered but they are not persuasive.
Applicant argues, “the claims are directed to embodiments that accurately determine an amount of classical computing resources needed to run a quantum computing simulation. Such concepts are not ones that fall within the abstract groupings.” Remarks 6-7. The steps of deriving, predicting, and translating are in line with other mathematical relationships and mental processes outlined in MPEP 2106.04(a)(2), “organizing information and manipulating information through mathematical correlations… collecting information, analyzing it, and displaying certain results of the collection and analysis…” Therefore, the claims are directed to an abstract idea.
Applicant argues, “claims implement a practical application. In particular, the claimed embodiments are structure to ‘prevent a reduction in a performance efficiency of the classical computing resources when the classical computing resources are used to execute the quantum computing simulation.’ As evidenced by this language, the claimed embodiments improve the performance efficiency of the resources when executing the simulation.” Remarks 7. MPEP 2106.05(a) states, “if the specification explicitly sets forth an improvement but in a conclusory manner (i.e., a bare assertion of an improvement without the detail necessary to be apparent to a person of ordinary skill in the art), the examiner should not determine the claim improves technology.” The specification paragraph 13 states, “An embodiment may help to ensure computationally-efficient performance of quantum computing simulations.” The specification paragraph 29 states, “output information 126 concerning aspects of the classical infrastructure expected to be needed to efficiently run the algorithm 106. Such output 126 may comprise, for example, memory and CPU requirements.” There is no reason why predicting classical computing resources needed for a quantum algorithm would improve the compute efficiency of a classical computer. First, efficiency isn’t described here, this is a business-style pitch more than a technological description – see the many descriptions of “cost-efficient performance”. Spec. 31 and abstract. Second, nothing about having a number of memories or CPUs makes the computer “efficient” at running a quantum algorithm. Therefore, this is a bare assertion of an improvement without the detail necessary to be apparent to a person that there is actually an improvement.
Applicant argues, “In particular, the claimed embodiments predict ‘an amount of classical computing resources that are needed for the execution of the simulation of the quantum algorithm while maintaining a determined computational efficiency for the classical computing resources while those classical computing resources are executing the simulation.’ As mentioned above, the claimed embodiments operate to improve computational efficiency. As such, the claims should be found to include concepts that are substantially more than any abstract idea.” Remarks 7. This is a rehash of the above argument. Likewise, saying that an embodiment is computationally efficient doesn’t make the embodiment computationally efficient, therefore the embodiment doesn’t amount to significantly more than the abstract idea – for the same reasons as mentioned above.
Art arguments are moot in light of new art required by amendments.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-5, 10-15 and 20-21 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claims 1 and 11 recite, “computing resources that are needed for the execution of the simulation of the quantum algorithm within a designated time period allotted for the execution…” This designated time period is not described in the specification and it constitutes new matter.
Applicant also claims “maintaining a determined computational efficiency…” Claim 1. This is not in the specification and is new matter.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-5, 10-15 and 20-21 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a mental concept abstract idea without significantly more. The claims recite deriving quantum attributes, predicting classical computing resource prediction, translating the classical computing resource prediction into elements of a classical computing infrastructure and executing a simulation. This judicial exception is not integrated into a practical application because receiving parameter values for quantum simulation and the user interface are insignificant extra solution activity. MPEP 2106.05(g). The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the data receiving step is a conventional step for gathering data using a generic computer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5, 10-12, 14-15 and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over US20190340532A1 to Ducore et al and US 20100313047 A1 to Kageshima.
Claims 3 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over US20190340532A1 to Ducore et al, US 20100313047 A1 to Kageshima and https://web.archive.org/web/20220527001110/https://www.tekdis.co.uk/insights/post/industrial-computer-product-selection-guide-and-how-to-choose-an-industrial-pc as archived 5/27/2022 (Tekdis).
Ducore teaches claims 1 and 11. A method for accurately determining an amount of classical computing resources needed to run a quantum computing simulation so as to prevent a reduction in a performance efficiency of the classical computing resources when the classical computing resources are used to execute the quantum computing simulation, said method, (Ducore para 60 “Then the quantum computer simulator system 110 (e.g., via the manager 130) can pick or select whichever backend hardware will be faster (or can provide the time it will take to run the fastest backend hardware)…”) comprising:
receiving parameter values relating to execution of a simulation of a quantum algorithm, wherein the parameter values indicate how much parallelization and acceleration are to be used for the execution of the simulation of the quantum algorithm (Ducore para 35 “The quantum computer simulator system 110 can receive a job (i.e., an input circuit, quantum program, or quantum algorithm) through the front end 120 and place the job in the queue 125.” The job is the parameter values relating to a quantum algorithm. Ducore para 60 “when the quantum computer simulator system 110 receives a job (e.g., in the queue 125), it is possible to add the cost (e.g., time) for each of the gates, steps, or operations in the job and that will give the total cost of running the job in the single-core CPU, the multi-core CPU, or the GPU, for example. Then the quantum computer simulator system 110 (e.g., via the manager 130) can pick or select whichever backend hardware will be faster (or can provide the time it will take to run the fastest backend hardware), or if there are two or more options that have similar timing performances, whichever one will result in the lower cost of simulation.” Acceleration is picking between the different CPUs and GPU.)
deriving quantum attributes from the parameter values; (Ducore para 41 “In addition to which gate is to be simulated, another aspect is the issue of how many system qubits there are overall in the circuit, quantum program, or quantum algorithm being considered for the simulation…”)
predicting, based on the quantum attributes, an amount of classical computing resources that are needed for the execution of the simulation of the quantum algorithm while maintaining a determined computational efficiency for the classical computing resources while those classical computing resources are executing the simulation; and (Ducore para 57 “This figure shows the gate cost (in nanoseconds or ns) for different system qubit counts for uncontrolled Z gates across three different simulation accelerators: single-core CPU-line or characteristic curve 310, multi-core CPU-line or characteristic curve 320, and GPU-line or characteristic curve 330.” The gate cost is the predicted computing resource on the classical system. The computational efficiency is determined by comparing the curves and selecting the best curve, Ducore para 36 “simulator process for which the overall predicted time is less and/or is predicted to perform the simulation most efficiently (e.g., power or resources used), is selected…”)
translating the predicted classical computing resource into a number of classical physical computing entities needed to execute the simulation of the quantum algorithm; (Applicant does not define “needed” in the claims or the specification. Examiner interprets needed to mean choosing some number of entities over some other number of entities. The translating in Ducore is Ducore’s selection of the faster hardware. Ducore para 60 “Then the quantum computer simulator system 110 (e.g., via the manager 130) can pick or select whichever backend hardware will be faster (or can provide the time it will take to run the fastest backend hardware), or if there are two or more options that have similar timing performances, whichever one will result in the lower cost of simulation.”)
wherein the predicted number of classical computing resource comprises a number of the central processing units (CPU) and an amount of memory. (Ducore para 35 says the “characteristic curves[ are] generated by the characterizer 150…” Ducore para 52 then shows that the predicted number of resources includes number of cores and memory size, “evaluation programs may differ in characterization functionality or features, while a hardware configuration may refer to the system resource settings (e.g., processing capabilities, processing cores (e.g., GPU, single core CPU, multi-core CPU, Tensor processor, etc.), memory size, memory configuration) allotted for a specific, separate piece of hardware.”)
Ducore doesn’t teach the time period that quantum simulations can happen in.
However, Kageshima teaches a designated time period allotted for the execution. (Kageshima para 53 “a first architecture generator 10d which generates an architecture (hereafter referred to as "first architecture") fulfilling a time limit and performance specifications…”)
Ducore, Kageshima and the claims all predict resources need for a classical system. It would have been obvious to a person having ordinary skill in the art, at the time of filing, to limit the architectures to architectures that can perform inside of a time and performance requests window to prevent the user from using "trial and error [because ]the user's burden for designing such an architecture increases and the work time becomes long.” Kageshima para 11.
Ducore teaches claims 2 and 12. The method as recited in claim 1, wherein the parameter values relate to any one or more of the following parameters: industry; quantum algorithm; problem space size; robustness of results expected from the execution of the simulation of the quantum algorithm; and a speed of the execution of the simulation of the quantum algorithm using the classical computing resources. (Ducore para 35 “The quantum computer simulator system 110 can receive a job (i.e…. quantum algorithm)” Ducore para 58 teaches that the number of qubits (problem space size) needed is used as an input to build the characteristic curves, “In the case of the single-core CPU (e.g., a hardware with hardware configuration having a single-core CPU), at very small numbers of qubits, it is faster…” The algorithm is related to speed of the execution. Robustness of the results is taught by para 38 “One way in which the characterizer 150 generates or builds these profiles is by building a simple circuit that includes a particular gate or quantum operation in a particular simulator process 145 many times.“ More simulations is equivalent to a more robustness of the result.)
Ducore teaches claims 3 and 13. The method as recited in claim 2, wherein the (Ducore para 47 “quantum computer simulator system 110 (e.g., the manager 130) can determine which resource is most efficient for simulating a circuit, quantum program, or quantum algorithm and/or how quickly that circuit, quantum program, or quantum algorithm can be simulated by such a resource.” Ducore para 9 “The process iteratively applies gates on systems of 1, n system qubits until an increasing exponential growth in simulation time is identified to determine the absolute number of supported system qubits.” Number of supported qubits is the circuit complexity.) Ducore doesn’t teach determining based on industry.
However, Tekdis teaches basing compute choices on industry type. (Tekdis “Industrial PCs, embedded systems, all-in-one touch panel PCs, DIN-rail embedded controllers, and IoT gateway devices are feature-rich and designed to meet the challenging requirements for operation in the automation industry.”)
Ducore, Tekdis and the claims are all directed to selecting computing devices. It would have been obvious to a person having ordinary skill in the art, at the time of filing, to choose different devices for different types of industry because “Industrial PCs, embedded systems, all-in-one touch panel PCs, DIN-rail embedded controllers, and IoT gateway devices are feature-rich and designed to meet the challenging requirements for operation in the automation industry.” Tekdis.
Ducore teaches claims 4 and 14. The method as recited in claim 2, wherein the problem space size determines, at least in part, a number of qubits associated with execution of the quantum algorithm. (Ducore para 58 “In the case of the single-core CPU (e.g., a hardware with hardware configuration having a single-core CPU), at very small numbers of qubits, it is faster…”)
Ducore teaches claims 5 and 15. The method as recited in claim 2, wherein the robustness of results determines, at least in part, a number of shots associated with execution of the quantum algorithm. (Ducore para 38 “One way in which the characterizer 150 generates or builds these profiles is by building a simple circuit that includes a particular gate or quantum operation in a particular simulator process 145 many times.“)
Ducore teaches claims 10 and 20. The method as recited in claim 1, wherein user-selectable parameters to which the parameter values respectively correspond are presented to a user by way of a user interface. (Ducore para 35 “user that submitted the job.” Ducore para 102 “computer device 700 can also include a user interface component 756 operable to receive inputs from a user “)
Ducore teaches claim 21. (New) The method of claim 1, wherein the amount of classical computing 21. resources generated from said predicting is provided at a granular level in that said predicting does not specify a type and number of actual computing entities needed to run the quantum algorithm but instead specifies raw amounts of basic resources needed to run the quantum algorithm. (Ducore para 49 “the selection of the simulator process can take into account the time it takes for the simulation to be carried out, the ability of a particular simulator process to carry out the simulation, and/or the cost associated with carrying out the simulation.” Ducore para 50 “(e.g., costs to operate the resources, time, acquisition costs of the resources) of the simulation.” The cost of resources is a raw amount of basic resourced needed to run the algorithm. Ducore also teaches an embodiment where the predicted cost is computer time for the different processors in para 60 “it is possible to add the cost (e.g., time) for each of the gates, steps, or operations in the job and that will give the total cost of running the job in the single-core CPU, the multi-core CPU, or the GPU, for example.”)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Austin Hicks whose telephone number is (571)270-3377. The examiner can normally be reached Monday - Thursday 8-4 PST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mariela Reyes can be reached at (571) 270-1006. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AUSTIN HICKS/Primary Examiner, Art Unit 2142