DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takenaka et al. (US Patent Application Publication # 2018/0054885).
Regarding Claim 1, Takenaka discloses a wiring substrate (i.e. wiring board 10), comprising:
an insulating layer (i.e. insulating resin layer 21/23 & solder resist layer 25) comprising resin (i.e. epoxy resin) and filler particles (i.e. inorganic fillers 29);
a via conductor (i.e. via conductors 23D) formed in the insulating layer such that the via conductor is formed in a through hole (i.e. via holes 23H) penetrating through the insulating layer; and
an embedded wiring layer (i.e. conductive circuit layers 22/24 w/ via conductors 23D & pads 26) comprising a plurality of wirings (i.e. wiring patterns (P)) and embedded in the insulating layer such that the plurality of wirings is filling a plurality of grooves (i.e. such as via holes 23H and holes where pads 26 are located) formed to extend in parallel (i.e. as shown on the left side in Fig. 2) on a surface of the insulating layer, respectively, and that the embedded wiring layer includes a metal film layer (i.e. metal film 41 & the conductive layers of the wiring patterns, via conductors, & pads) covering entire inner surfaces of the grooves,
wherein the embedded wiring layer is formed such that a smallest line width (i.e. minimum width) of the plurality of wirings in the embedded wiring layer is in a range of 2 µm to 8 µm (i.e. 8 µm or less, as disclosed in Paragraph 0059 & Claim 5), and the insulating layer is formed such that a maximum particle size of the filler particles is 50% or less (i.e. 50% or less, as disclosed in Paragraph 0061) of the smallest line width of the plurality of wirings in the embedded wiring layer (Fig. 1-5B & 10; Abstract; Paragraphs 0019, 0022-0028, 0032-0035, 0039-0045, 0054-0063). The figures show that the inner surfaces of the groves occupied by the wiring are covered by the metal film layer. Furthermore, conductive circuit layers 22 & 24 are embedded in insulating resin layer 23 & solder resist layer 25, respectively. Fig. 10 also shows insulating resin layer 21 having an embedded conductive circuit layer that is not numbered.
Regarding Claim 2, Takenaka discloses that the insulating layer is formed such that a content rate of the filler particles in the insulating layer is in a range of 25 weight% to 70 weight% (i.e. 30 to 80 wt. %) (Paragraphs 0024-0025, 0051-0052).
Regarding Claim 3, Takenaka discloses that the embedded wiring layer includes a plating film layer (i.e. plating layers 30/31) formed on the metal film layer (Fig. 2-3; Paragraph 0022, 0032-0035, 0039-0045).
Regarding Claim 4, Takenaka discloses that the embedded wiring layer is formed such that a smallest thickness of the wirings (i.e. wiring patterns (P)) in the embedded wiring layer (i.e. conductive circuit layers 22/24) is in a range of 5 µm to 10 µm (i.e. 5-15 µm), and the insulating layer is formed such that the maximum particle size (i.e. 0.5 µm or less) of the filler particles is 40% or less (i.e.
0.5
µ
m
o
r
l
e
s
s
5
µ
m
×
100
%
=
10
%
o
r
l
e
s
s
) of the smallest thickness of the wirings in the embedded wiring layer (Paragraphs 0022, 0023, 0050, 0056, 0057, 0061).
Regarding Claim 5, Takenaka discloses that the embedded wiring layer is formed such that the smallest line width (i.e. minimum width) of the plurality of wirings (i.e. wiring patterns (P)) in the embedded wiring layer (i.e. conductive circuit layers 22/24) is 5 µm (i.e. 5 µm) and that a smallest thickness of the plurality of wirings in the embedded wiring layer is 5 µm (i.e. 5 µm), and the insulating layer is formed such that the maximum particle size of the filler particles is 1 µm (i.e. 2 µm or less) (Paragraphs 0022, 0023, 0050, 0056, 0057, 0059, 0061).
Regarding Claim 6, Takenaka discloses that the insulating layer is formed such that a ratio of the filler particles having particle sizes of 25% or greater of the smallest line width (i.e. sizes larger than 15% of the minimum width) in the filler particles is 75% or less (Paragraph 0061). Takenaka states that it is possible for some particles of the inorganic filler 29 to sizes larger than 15% of the minimum width (W), but that substantially all of the particles of the inorganic filler 29 contained in the insulating resin layers (21, 23) are 15% or less of the minimum width (W) of the wiring patterns (P). Takenaka explicitly says that these larger fillers are exceptions. Therefore, one would conclude that the ratio of these larger particles within the total filler particles would be within the range of 75% or less.
Regarding Claim 7, Takenaka discloses that the embedded wiring layer includes a plating film layer (i.e. plating layers 30/31) formed on the metal film layer (Fig. 2-3; Paragraph 0022, 0032-0035, 0039-0045). The figures show that the inner surfaces of the groves occupied by the wiring are covered by the metal film layer and a plating layer is formed.
Regarding Claim 8, Takenaka discloses that the embedded wiring layer is formed such that a smallest thickness of the wirings (i.e. wiring patterns (P)) in the embedded wiring layer (i.e. conductive circuit layers 22/24) is in a range of 5 µm to 10 µm (i.e. 5-15 µm), and the insulating layer is formed such that the maximum particle size (i.e. 0.5 µm or less) of the filler particles is 40% or less (i.e.
0.5
µ
m
o
r
l
e
s
s
5
µ
m
×
100
%
=
10
%
o
r
l
e
s
s
) of the smallest thickness of the wirings in the embedded wiring layer (Paragraphs 0022, 0023, 0050, 0056, 0057, 0061).
Regarding Claim 9, Takenaka discloses that the embedded wiring layer is formed such that the smallest line width (i.e. minimum width) of the plurality of wirings (i.e. wiring patterns (P)) in the embedded wiring layer (i.e. conductive circuit layers 22/24) is 5 µm (i.e. 5 µm) and that a smallest thickness of the plurality of wirings in the embedded wiring layer is 5 µm (i.e. 5 µm), and the insulating layer is formed such that the maximum particle size of the filler particles is 1 µm (i.e. 2 µm or less) (Paragraphs 0022, 0023, 0050, 0056, 0057, 0059, 0061).
Regarding Claim 10, Takenaka discloses that the insulating layer is formed such that a ratio of the filler particles having particle sizes of 25% or greater of the smallest line width (i.e. sizes larger than 15% of the minimum width) in the filler particles is 75% or less (Paragraph 0061). Takenaka states that it is possible for some particles of the inorganic filler 29 to sizes larger than 15% of the minimum width (W), but that substantially all of the particles of the inorganic filler 29 contained in the insulating resin layers (21, 23) are 15% or less of the minimum width (W) of the wiring patterns (P). Takenaka explicitly says that these larger fillers are exceptions. Therefore, one would conclude that the ratio of these larger particles within the total filler particles would be within the range of 75% or less.
Regarding Claim 11, Takenaka discloses that the embedded wiring layer is formed such that a smallest thickness of the wirings (i.e. wiring patterns (P)) in the embedded wiring layer (i.e. conductive circuit layers 22/24) is in a range of 5 µm to 10 µm (i.e. 5-15 µm), and the insulating layer is formed such that the maximum particle size (i.e. 0.5 µm or less) of the filler particles is 40% or less (i.e.
0.5
µ
m
o
r
l
e
s
s
5
µ
m
×
100
%
=
10
%
o
r
l
e
s
s
) of the smallest thickness of the wirings in the embedded wiring layer (Paragraphs 0022, 0023, 0050, 0056, 0057, 0061).
Regarding Claim 12, Takenaka discloses that the embedded wiring layer is formed such that the smallest line width (i.e. minimum width) of the plurality of wirings (i.e. wiring patterns (P)) in the embedded wiring layer (i.e. conductive circuit layers 22/24) is 5 µm (i.e. 5 µm) and that a smallest thickness of the plurality of wirings in the embedded wiring layer is 5 µm (i.e. 5 µm), and the insulating layer is formed such that the maximum particle size of the filler particles is 1 µm (i.e. 2 µm or less) (Paragraphs 0022, 0023, 0050, 0056, 0057, 0059, 0061).
Regarding Claim 13, Takenaka discloses that the insulating layer is formed such that a ratio of the filler particles having particle sizes of 25% or greater of the smallest line width (i.e. sizes larger than 15% of the minimum width) in the filler particles is 75% or less (Paragraph 0061). Takenaka states that it is possible for some particles of the inorganic filler 29 to sizes larger than 15% of the minimum width (W), but that substantially all of the particles of the inorganic filler 29 contained in the insulating resin layers (21, 23) are 15% or less of the minimum width (W) of the wiring patterns (P). Takenaka explicitly says that these larger fillers are exceptions. Therefore, one would conclude that the ratio of these larger particles within the total filler particles would be within the range of 75% or less.
Regarding Claim 14, Takenaka discloses that the embedded wiring layer is formed such that the smallest line width (i.e. minimum width) of the plurality of wirings (i.e. wiring patterns (P)) in the embedded wiring layer (i.e. conductive circuit layers 22/24) is 5 µm (i.e. 5 µm) and that a smallest thickness of the plurality of wirings in the embedded wiring layer is 5 µm (i.e. 5 µm), and the insulating layer is formed such that the maximum particle size of the filler particles is 1 µm (i.e. 2 µm or less) (Paragraphs 0022, 0023, 0050, 0056, 0057, 0059, 0061).
Regarding Claim 15, Takenaka discloses that the insulating layer is formed such that a ratio of the filler particles having particle sizes of 25% or greater of the smallest line width (i.e. sizes larger than 15% of the minimum width) in the filler particles is 75% or less (Paragraph 0061). Takenaka states that it is possible for some particles of the inorganic filler 29 to sizes larger than 15% of the minimum width (W), but that substantially all of the particles of the inorganic filler 29 contained in the insulating resin layers (21, 23) are 15% or less of the minimum width (W) of the wiring patterns (P). Takenaka explicitly says that these larger fillers are exceptions. Therefore, one would conclude that the ratio of these larger particles within the total filler particles would be within the range of 75% or less.
Regarding Claim 16, Takenaka discloses that the insulating layer is formed such that a ratio of the filler particles having particle sizes of 25% or greater of the smallest line width (i.e. sizes larger than 15% of the minimum width) in the filler particles is 75% or less (Paragraph 0061). Takenaka states that it is possible for some particles of the inorganic filler 29 to sizes larger than 15% of the minimum width (W), but that substantially all of the particles of the inorganic filler 29 contained in the insulating resin layers (21, 23) are 15% or less of the minimum width (W) of the wiring patterns (P). Takenaka explicitly says that these larger fillers are exceptions. Therefore, one would conclude that the ratio of these larger particles within the total filler particles would be within the range of 75% or less.
Regarding Claim 17, Takenaka discloses that the embedded wiring layer is formed such that a smallest thickness of the wirings (i.e. wiring patterns (P)) in the embedded wiring layer (i.e. conductive circuit layers 22/24) is in a range of 5 µm to 10 µm (i.e. 5-15 µm), and the insulating layer is formed such that the maximum particle size (i.e. 0.5 µm or less) of the filler particles is 40% or less (i.e.
0.5
µ
m
o
r
l
e
s
s
5
µ
m
×
100
%
=
10
%
o
r
l
e
s
s
) of the smallest thickness of the wirings in the embedded wiring layer (Paragraphs 0022, 0023, 0050, 0056, 0057, 0061).
Regarding Claim 18, Takenaka discloses that the embedded wiring layer is formed such that the smallest line width (i.e. minimum width) of the plurality of wirings (i.e. wiring patterns (P)) in the embedded wiring layer (i.e. conductive circuit layers 22/24) is 5 µm (i.e. 5 µm) and that a smallest thickness of the plurality of wirings in the embedded wiring layer is 5 µm (i.e. 5 µm), and the insulating layer is formed such that the maximum particle size of the filler particles is 1 µm (i.e. 2 µm or less) (Paragraphs 0022, 0023, 0050, 0056, 0057, 0059, 0061).
Response to Arguments
Applicant's arguments filed 8/21/2025 have been fully considered but they are not persuasive. The Applicant argues that Takenaka does not teach or suggest “an embedded wiring layer comprising a plurality of wirings and embedded in the insulating layer such that the plurality of wirings is filling a plurality of grooves formed to extend in parallel on a surface of the insulating layer, respectively, and that the embedded wiring layer includes a metal film layer covering entire inner surfaces of the grooves” and “a via conductor formed in the insulating layer such that the via conductor is formed in a through hole penetrating through the insulating layer”. The Examiner respectfully disagrees and has clarified the rejection above. Particularly, conductive circuit layers 22 & 24 of the wiring patterns, via conductors 23D, & pads 26 along with metal film 41 are embedded within via holes 23H & holes where pads 26 are located in insulating resin layer 23 & solder resist layer 25, respectively as shown in Fig. 10. Fig. 10 also shows insulating resin layer 21 having an embedded conductive circuit layer that is not numbered. Furthermore, Takenaka discloses via conductors 23D formed in via holes 23H and via holes 23H and holes where pads 26 are located are formed to extend in parallel as shown on the left side in Fig. 2.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RHADAMES J ALONZO MILLER whose telephone number is (571)270-7829. The examiner can normally be reached Mon-Fri 10am-6pm PST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached on (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/RJA/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
Prosecution Insights