DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 19th, 2026 has been entered.
Claim Status
Claims 1, 6, 10-11, 20-23, 25-27 and 29-30 have been amended. Claims 2, 12 and 28 have been cancelled. Claims 1, 3-11, 13-27 and 29-30 remain pending and are ready for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-7, 10, 11-17 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Danielson et al. (US Publication No. 2019/0332317 -- "Danielson") in view of Monteleone et al. (US Publication No. 2019/0347012 – “Monteleone”) in further view of Kwon et al. (US Publication No. 2018/0113636 – “Kwon”).
Regarding claim 1, Danielson teaches A method, comprising: performing a first wear leveling operation at a memory system based at least in part on performing a first quantity of write operations at a plurality of blocks of memory cells of the memory system; (Danielson paragraph [0039], FIG. 4B illustrates an example of determining whether to store other data at a memory device based on the usage of the memory devices 450, in accordance with embodiments of the present disclosure. In the present illustration, the actual usage of a memory cell of memory device 420 is 94 write operations performed on a memory cell of memory device 420. Because the actual usage of the memory cell of memory device 420 is less than the usage threshold (e.g., 100 write operations) for memory device 420, data can be stored at the memory cell of the memory device 420. The actual usage of a memory cell of memory device 430, however, is 50 write operations performed on a memory cell of memory device 430. Because the actual usage of the memory cell (e.g., 50 write operations) exceeds the usage threshold (e.g., 50) for memory device 430, data is not stored at the memory cell of memory device 430. The process for a wear leveling operation (determining which memory blocks/cells are viable for storage and using them according to said determinations) can be based on various usage characteristics such as write operation quantity, as indicated here. For further details regarding the usage characteristic being used for wear leveling operations, see Danielson paragraphs [0022-0023], The controller 115 can include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory system 110, including handling communications between the memory system 110 and the host system 120. In some embodiments, the local memory 119 can include memory registers storing memory pointers, fetched data, etc. The local memory 119 can also include read-only memory (ROM) for storing micro-code. While the example memory system 110 in FIG. 1 has been illustrated as including the controller 115, in another embodiment of the present disclosure, a memory system 110 may not include a controller 115, and may instead rely upon external control (e.g., provided by an external host, or by a processor or controller separate from the memory system). In general, the controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 112A to 112N. The controller 115 can be responsible for other operations such as wear leveling operations) determining a second quantity of write operations in response to performing the first wear leveling operation; (Danielson paragraph [0034], At block 350, if a usage threshold of the first memory device and/or the second memory device has been exceeded, the subsequent data is not stored at the memory device that corresponds to the exceeded usage threshold. For example, if it is determined that the usage threshold for the first memory device has not been exceeded and the usage threshold for the second memory device has been exceeded, then subsequent data is not stored at the second memory device (e.g., the memory device corresponding to the exceeded usage threshold). As previously described, in one embodiment, the usage thresholds can correspond to the endurance of memory devices to reliably store data. Accordingly, the usage threshold of a memory device being exceeded can indicate that the memory device can no longer store data reliably and, therefore, subsequent data should no longer be stored at the memory device. In one embodiment, if the usage threshold of the memory device is exceeded, the memory device can begin to operate in a read-only mode. While operating in a read-only mode, data stored at the memory device can continue to be read (e.g., provided to the host system), but subsequent data received from the host system is not stored at the memory device. As taught in Danielson above, the second quantity of write operations is heavily determined by the results of the initial wear leveling operation) and determining to perform a second wear leveling operation at the memory system (Danielson paragraphs [0037-0038], FIG. 4A illustrates an example of determining whether to store data at a memory device based on the usage of the memory devices 400, in accordance with some embodiments of the present disclosure. Memory system 410 includes memory devices 420 and 430. In one embodiment, memory device 420 includes a first media type having a first endurance to store data and memory device 430 includes a second media type having a second endurance to store data. For illustrative purposes, memory device 420 has a usage threshold of 100 and memory device 430 has a usage threshold of 50. In one embodiment, the usage thresholds and actual usages can correspond to a number of bytes written to a memory cell of the memory device. In embodiments, the usage thresholds and actual usages can correspond to a number of write operations performed on a memory cell of the memory device. In the present illustration, the actual usage of a memory cell of memory device 420 is 82 write operations performed on a memory cell of memory device 420. Because the actual usage of the memory cell (e.g., 82 write operations) of memory device 420 is less than the usage threshold (e.g., 100 write operations) for memory device 420, data can be stored at memory device 420. The actual usage of a memory cell of memory device 430 is 37 write operations performed on a memory cell of memory device 430. Because the actual usage of the memory cell (e.g., 37 write operations) is less than the usage threshold (e.g., 50 write operations) for memory device 430, data can be stored at memory device 430. The wear leveling operation will determine the quantity of write operations that can be performed on a corresponding memory unit, as well as the determination of whether that usage characteristic (i.e., second quantity of write operations) exceeds a threshold resulting in a necessary wear leveling operation).
Danielson does not teach determining a second quantity of write operations, less than the first quantity of write operations; performing, after performing the first wear leveling operation, the determined second quantity of write operations at the plurality of blocks of memory cells; determining whether to perform a second wear leveling operation at the memory system based at least in part on performing the determined second quantity of write operations at the plurality of blocks of memory cells.
However, Monteleone teaches determining a second quantity of write operations, different than the first quantity of write operations; performing, after performing the first wear leveling operation, the determined second quantity of write operations at the memory system; (Monteleone paragraph [0018], In some examples, the memory 120 may be configured to track write operations performed by the memory 120. In particular, the memory 120 may track a “global write count,” or the number of write operations performed by the memory 120 since the memory 120 last performed a wear leveling operation. Once the global write count has exceeded a threshold, the memory 120 may recommend the host 110 provide a wear leveling command. In some instances, the memory 120 may selectively ignore wear leveling commands based on the global write count. The memory 120 may, for instance, ignore wear leveling commands if the global write count does not exceed a threshold. A second quantity of write commands may be tracked after performing a wear leveling operation) determining to perform a second wear leveling operation at the memory system based at least in part on performing the determined second quantity of write operations (Monteleone paragraph [0019], Additionally or alternatively, in some examples, the memory 120 may be configured to track a number of write operations performed on each block of an array associated with the memory 120. In particular, the memory 120 may track a “local write count” for each block, or a number of write operations performed by the memory 120 on each block since the memory 120 last performed a wear leveling operation. Once a local write count has exceeded a threshold, the memory 120 may recommend the host 110 provide a wear leveling command. The wear leveling operation may be performed based on a write count since the last wear leveling operation (i.e., second quantity of write operations).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Danielson with those of Monteleone. Monteleone teaches using a second quantity of write operations, tracked after performing a wear leveling operation, which can provide a more efficient wear leveling system minimizing processing demands while maximizing the lifespan of said memory (Monteleone paragraph [0037], Accordingly, the memory control unit 310 may perform a wear leveling operation such that the logical address LBAm may be associated with the physical address PBAM and thus the maximum cycled block of the array 504. Additionally, the logical address SPARE may be associated with the physical address PBAm and thus the minimum cycled block BLOCK3 of the array 504, and the logical address LBAM may be associated with the physical address PBAi and thus becoming the spare block of the array 504. Assigning addresses in this manner may, for instance, more evenly distribute write operations among blocks BLOCK0-BLOCK7 of the array 504 and thereby provide prolonged operation of the array 504).
Danielson in view of Monteleone does not teach determining a second quantity of write operations, less than the first quantity of write operations; performing … the determined second quantity of write operations at the plurality of blocks of memory cells; performing the determined second quantity of write operations at the plurality of blocks of memory cells.
However, Kwon teaches determining a second quantity of write operations, less than the first quantity of write operations; performing … the determined second quantity of write operations at the plurality of blocks of memory cells; performing the determined second quantity of write operations at the plurality of blocks of memory cells (Kwon paragraphs [0031-0032], Referring to FIG. 2, there is illustrated as an example a memory device 300 including M memory blocks BLOCK0 to BLOCKM, each of the memory blocks BLOCK0 to BLOCKM including N lines LINE1 to LINEN. In FIG. 2, reference numeral “WCNT” denotes the number of write operations, also referred to hereinafter as the write count. The counting unit 221 may count a write count WCNT for each of the memory blocks BLOCK0 to BLOCKM, and manage the write count WCNT for each of the memory blocks BLOCK0 to BLOCKM. The second wear-leveling unit 223 may perform a dynamic wear-leveling operation of detecting a hot memory block having the largest write count WCNT and a cold memory block having the lowest write count WCNT among the memory blocks BLOCK0 to BLOCKM, and swapping the hot memory block with the cold memory block. In addition, the first wear-leveling unit 222 may perform a static wear-leveling operation of shifting the first to Nth lines LINE1 to LINEN of each of the memory blocks BLOCK0 to BLOCKM in a regular cycle. For example, the first wear-leveling unit 222 may perform a start-gap wear leveling operation of setting and shifting a gap line on which a write operation is not performed, among the first to Nth lines LINE1 to LINEN, in a regular cycle. For a given memory block comprised of memory cells, the first write count can be determined (i.e., considered a hot memory block) resulting in a wear leveling operation. In response to the wear leveling, a second number of write counts less than the first (i.e., a cold block) can also be determined).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Danielson and Monteleone with those of Kwon. Kwon teaches performing wear leveling based on determined quantities of write operations on memory cells of a plurality of memory blocks, which can allow for more optimal wear spreading between the memory system (i.e., see Kwon paragraph [0005], Nonvolatile memory devices such as the RRAM, and the PCRAM have limited write endurance. The write endurance may be defined as the number of program/write cycles that are allowed for a memory block before a storage media loses its reliability. The write endurance may be calculated by estimating how often and how evenly the memory is used).
Claim 10 is the corresponding apparatus claim to method claim 1. It is rejected with the same references and rationale.
Regarding claim 3, Danielson in view of Monteleone in further view of Kwon teaches The method of claim 1, further comprising: determining whether to perform the first wear leveling operation in accordance with a first rate of evaluation that is associated with the first quantity of write operations, wherein performing the first wear leveling operation is based at least in part on determining to perform the first wear leveling operation; (Danielson paragraph [0018], However, as previously discussed, memory devices having different media types can have different endurances and different respective threshold for storing data at the memory devices. The data can be stored at the memory devices based on the determined usage thresholds. For example, if a first memory device of the memory system is at or near a first usage threshold that indicates that the first memory device is at or near a point where the first memory device can no longer reliably store data, then data can be stored at another memory device of the memory system. By providing data to the different memory devices of the memory system based on different determined usage thresholds, the wear (e.g., number of operations performed on a memory device and/or an amount of data written to the memory device) on the multiple memory devices of the memory system can be more evenly distributed, preventing the premature failure of a particular memory device of a memory system relative to the other memory devices of the memory system. The process of a wear leveling operation is directly tied to the quantity of the write operations performed) and determining whether to perform the second wear leveling operation in accordance with a second rate of evaluation, greater than the first rate of evaluation, that associated with the second quantity of write operations (Danielson paragraph [0028], At block 230, a first usage threshold is determined for the first memory device based on the first set of characteristics received at block 220 and a second usage threshold is determined for the second memory device based on the second set of characteristics received at block 220. In embodiments, the first usage threshold can correspond to an endurance of the first memory device to store data and the second usage threshold corresponds to an endurance for the second memory device to store data. In one embodiment, the first usage threshold and the second usage threshold can correspond to the amount of data that can be written to a memory cell of a corresponding memory device before the memory cell can be considered unreliable to store data. For example, the first usage threshold can correspond to 1,000,000 total bytes that can be written to a memory cell of the first memory device and the second usage threshold can correspond to 1,500,000 total bytes that can be written to a memory cell of the second memory device. In some embodiments, the first usage threshold and the second usage threshold can correspond to a number of write operations that can be performed on a memory cell of a corresponding memory device before the memory cell can be considered unreliable to store data. For example, the first usage threshold can correspond to 500,000 write operations that can be performed on a memory cell of the first memory device and the second usage threshold can correspond to 1,000,000 write operations that can be performed on a memory cell of the second memory device. The determination for the second wear leveling operation may require a greater number of second write operations to be performed).
Regarding claim 4, Danielson in view of Monteleone in further view of Kwon The method of claim 1, further comprising: receiving a first set of one or more commands from a host system; performing the first quantity of write operations based at least in part on the first set of one or more commands from the host system; and receiving a second set of one or more commands from the host system, wherein performing the second quantity of write operations is based at least in part on the second set of one or more commands from the host system (Danielson paragraph [0023], In general, the controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 112A to 112N. The controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical block address and a physical block address that are associated with the memory devices 112A to 112N. The controller 115 can further include host interface circuitry to communicate with the host system 120 via the physical host interface. The host interface circuitry can convert the commands received from the host system into command instructions to access the memory devices 112A to 112N as well as convert responses associated with the memory devices 112A to 112N into information for the host system 120. A plurality of first and second write operations may be received from the host by the memory device/controller and subsequently performed/executed).
Regarding claim 5, Danielson in view of Monteleone in further view of Kwon The method of claim 1, wherein write operations of the first quantity of write operations and write operations of the second quantity of write operations are associated with migrating data from memory cells of the memory system that are associated with a first storage density to memory cells of the memory system that are associated with a second storage density (Danielson paragraphs [0033-0034], At block 330, a determination is made as to whether a corresponding usage threshold of the first memory device or the second memory device has been exceeded. For purposes of the present disclosure, a usage threshold can be exceeded when a value is greater than or equal to the usage threshold. For example, if the first usage threshold for the first memory device is 1,000,000 total bytes written to a memory cell of the first memory device and a memory cell of the first memory device has had 1,000,000 total bytes written to the memory cell, then the first usage threshold has been exceeded. If a usage threshold for the first memory device and/or the second memory device has not been exceeded, then at block 340, subsequent data is stored at the first memory device or the second memory device. The subsequent data can be received from a host system for storage by the memory system. In one embodiment, if the usage thresholds for the memory devices have not been exceeded, the subsequent data can be stored at the first memory device or second memory device based on characteristics associated with the subsequent data. The storage density (i.e., the number of bits in a given allocation of memory storage) can be used to determine the write operation characteristics. Also see Danielson paragraphs [0015-0016], Generally, in order to obtain the different desired characteristics of memory devices, multiple conventional memory systems having different media types and associated characteristics can be used with a host system. For example, a host system can be coupled to a first conventional memory system having a first media type with a high data density, a second conventional memory system having a second media type with a high access speed, and a third conventional memory system having a third media type with a high endurance. However, using multiple memory systems to achieve the different desired characteristics for the storage of data is costly and inefficient as the host system would utilize additional connections to each of the different memory systems).
Regarding claim 6, Danielson in view of Monteleone in further view of Kwon The method of claim 1, further comprising: determining that a lowest quantity of program/erase cycles associated with a plurality of blocks of memory cells of the memory system satisfies a threshold, wherein performing the first wear leveling operation at the memory system is based at least in part on determining that the lowest quantity of program/erase cycles satisfies the threshold (Danielson paragraph [0013], Other characteristics of a memory device can be associated with the endurance of the memory device to store data. When data is written to and/or erased from a memory cell of a memory device, the memory cell can be damaged. As the number of write operations and/or erase operations performed on a memory cell increases, the probability that the data stored at the memory cell including an error increase as the memory cell is increasingly damaged. A characteristic associated with the endurance of the memory device is the number of write operations or a number of program/erase operations performed on a memory cell of the memory device. If a threshold number of write operations performed on the memory cell is exceeded, then data can no longer be reliably stored at the memory cell as the data can include a large number of errors that cannot be corrected. Different media types can also have difference endurances for storing data. For example, a first media type can have a threshold of 1,000,000 write operations, while a second media type can have a threshold of 2,000,000 write operations. Accordingly, the endurance of the first media type to store data is less than the endurance of the second media type to store data. Program/erase cycle data can be utilized to determine the appropriate wear leveling operations when compared to a threshold value).
Regarding claim 7, Danielson in view of Monteleone in further view of Kwon The method of claim 1, wherein performing the first wear leveling operation comprises: reading information from a first block of memory cells associated with a lowest quantity of program/erase cycles; and writing the information to a second block of memory cells different than the first block of memory cells (Danielson paragraph [0022], The controller 115 can communicate with the memory devices 112A to 112N to perform operations such as reading data, writing data, or erasing data at the memory devices 112A to 112N and other such operations. The controller 115 can include hardware such as one or more integrated circuits and/or discrete components, a buffer memory, or a combination thereof. The controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor. The controller 115 can include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory system 110, including handling communications between the memory system 110 and the host system 120. In some embodiments, the local memory 119 can include memory registers storing memory pointers, fetched data, etc. The local memory 119 can also include read-only memory (ROM) for storing micro-code. While the example memory system 110 in FIG. 1 has been illustrated as including the controller 115, in another embodiment of the present disclosure, a memory system 110 may not include a controller 115, and may instead rely upon external control (e.g., provided by an external host, or by a processor or controller separate from the memory system). The lowest quantity of program/erase cycles may be classified as a read-only memory unit resulting in a read operation being performed to transfer the corresponding data).
Regarding claim 11, Danielson teaches A method, comprising: performing a first quantity of write operations at a plurality of blocks of memory cells of a memory system; (see Danielson paragraph [0012] for memory system comprising blocks of memory cells) performing the second quantity of write operations at the plurality of blocks of memory cells greater than the first quantity, after performing the first quantity of write operations; (Danielson paragraph [0039], FIG. 4B illustrates an example of determining whether to store other data at a memory device based on the usage of the memory devices 450, in accordance with embodiments of the present disclosure. In the present illustration, the actual usage of a memory cell of memory device 420 is 94 write operations performed on a memory cell of memory device 420. Because the actual usage of the memory cell of memory device 420 is less than the usage threshold (e.g., 100 write operations) for memory device 420, data can be stored at the memory cell of the memory device 420. The actual usage of a memory cell of memory device 430, however, is 50 write operations performed on a memory cell of memory device 430. Because the actual usage of the memory cell (e.g., 50 write operations) exceeds the usage threshold (e.g., 50) for memory device 430, data is not stored at the memory cell of memory device 430. The process for a wear leveling operation (determining which memory blocks/cells are viable for storage and using them according to said determinations) can be based on various usage characteristics such as write operation quantity, as indicated here. For further details regarding the usage characteristic being used for wear leveling operations, see Danielson paragraphs [0022-0023], The controller 115 can include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory system 110, including handling communications between the memory system 110 and the host system 120. In some embodiments, the local memory 119 can include memory registers storing memory pointers, fetched data, etc. The local memory 119 can also include read-only memory (ROM) for storing micro-code. While the example memory system 110 in FIG. 1 has been illustrated as including the controller 115, in another embodiment of the present disclosure, a memory system 110 may not include a controller 115, and may instead rely upon external control (e.g., provided by an external host, or by a processor or controller separate from the memory system). In general, the controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 112A to 112N. The controller 115 can be responsible for other operations such as wear leveling operations).
Danielson does not teach performing a second quantity of write operations at the memory system greater than the first quantity, after performing the first quantity of write operations; determining to refrain from performing a first wear leveling operation at the memory system based at least in part on performing the first quantity of write operations at the memory system; determining a second quantity of write operations, greater than the first quantity of write operations, after determining to refrain from performing the first wear leveling operation; perform the second quantity of write operations at the plurality of blocks of memory cells; and determining whether to perform a second wear leveling operation at the memory system based at least in part on determining to refrain from performing the first wear leveling operation and performing the second quantity of write operations at the plurality of blocks of memory cells.
However, Monteleone teaches performing a second quantity of write operations at the memory system different than the first quantity, after performing the first quantity of write operations; determining to refrain from performing a first wear leveling operation at the memory system based at least in part on performing the first quantity of write operations at the memory system; (Monteleone paragraph [0018], In some examples, the memory 120 may be configured to track write operations performed by the memory 120. In particular, the memory 120 may track a “global write count,” or the number of write operations performed by the memory 120 since the memory 120 last performed a wear leveling operation. Once the global write count has exceeded a threshold, the memory 120 may recommend the host 110 provide a wear leveling command. In some instances, the memory 120 may selectively ignore wear leveling commands based on the global write count. The memory 120 may, for instance, ignore wear leveling commands if the global write count does not exceed a threshold. The wear leveling operation may be ignored based on a quantity of write operations not exceeding a threshold) determining a second quantity of write operations, greater than the first quantity of write operations, after determining to refrain from performing the first wear leveling operation; and determining to perform a second wear leveling operation at the memory system based at least in part on determining to refrain from performing the first wear leveling operation and based at least in part on performing the second quantity of write operations at the memory system (Monteleone paragraph [0019], Additionally or alternatively, in some examples, the memory 120 may be configured to track a number of write operations performed on each block of an array associated with the memory 120. In particular, the memory 120 may track a “local write count” for each block, or a number of write operations performed by the memory 120 on each block since the memory 120 last performed a wear leveling operation. Once a local write count has exceeded a threshold, the memory 120 may recommend the host 110 provide a wear leveling command, and in some instances, the memory 120 may selectively ignore wearing commands based on the local write count. In this manner, the memory 120 may recommend the host 110 provide a wear leveling command in response to performing an operation at a particular block (e.g., maximum cycled block) a particular number of times since last performing a wear leveling operation. If the wear leveling command is ignored, a second quantity of write operations may be tracked and if exceeding a determined amount, a wear leveling operation may be automatically performed).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Danielson with those of Monteleone. Monteleone teaches using a second quantity of write operations, tracked after performing a wear leveling operation, which can provide a more efficient wear leveling system minimizing processing demands while maximizing the lifespan of said memory (Monteleone paragraph [0037], Accordingly, the memory control unit 310 may perform a wear leveling operation such that the logical address LBAm may be associated with the physical address PBAM and thus the maximum cycled block of the array 504. Additionally, the logical address SPARE may be associated with the physical address PBAm and thus the minimum cycled block BLOCK3 of the array 504, and the logical address LBAM may be associated with the physical address PBAi and thus becoming the spare block of the array 504. Assigning addresses in this manner may, for instance, more evenly distribute write operations among blocks BLOCK0-BLOCK7 of the array 504 and thereby provide prolonged operation of the array 504).
Danielson in view of Monteleone does not teach determining a second quantity of write operations, greater than the first quantity of write operations, perform the second quantity of write operations at the plurality of blocks of memory cells; performing the second quantity of write operations at the plurality of blocks of memory cells (Kwon paragraphs [0031-0032], Referring to FIG. 2, there is illustrated as an example a memory device 300 including M memory blocks BLOCK0 to BLOCKM, each of the memory blocks BLOCK0 to BLOCKM including N lines LINE1 to LINEN. In FIG. 2, reference numeral “WCNT” denotes the number of write operations, also referred to hereinafter as the write count. The counting unit 221 may count a write count WCNT for each of the memory blocks BLOCK0 to BLOCKM, and manage the write count WCNT for each of the memory blocks BLOCK0 to BLOCKM. The second wear-leveling unit 223 may perform a dynamic wear-leveling operation of detecting a hot memory block having the largest write count WCNT and a cold memory block having the lowest write count WCNT among the memory blocks BLOCK0 to BLOCKM, and swapping the hot memory block with the cold memory block. In addition, the first wear-leveling unit 222 may perform a static wear-leveling operation of shifting the first to Nth lines LINE1 to LINEN of each of the memory blocks BLOCK0 to BLOCKM in a regular cycle. For example, the first wear-leveling unit 222 may perform a start-gap wear leveling operation of setting and shifting a gap line on which a write operation is not performed, among the first to Nth lines LINE1 to LINEN, in a regular cycle. For a given memory block comprised of memory cells, the first write count can be determined (i.e., considered a cold memory block) resulting in a wear leveling operation. In response to the wear leveling, a second number of write counts less than the first (i.e., a hot block) can also be determined).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Danielson and Monteleone with those of Kwon. Kwon teaches performing wear leveling based on determined quantities of write operations on memory cells of a plurality of memory blocks, which can allow for more optimal wear spreading between the memory system (i.e., see Kwon paragraph [0005], Nonvolatile memory devices such as the RRAM, and the PCRAM have limited write endurance. The write endurance may be defined as the number of program/write cycles that are allowed for a memory block before a storage media loses its reliability. The write endurance may be calculated by estimating how often and how evenly the memory is used).
Claim 20 is the corresponding apparatus claim to method claim 11. It is rejected with the same references and rationale.
Regarding claim 13, Danielson in view of Monteleone in further view of Kwon teaches The method of claim 11, further comprising: determining whether to perform the first wear leveling operation in accordance with a first rate of evaluation that is associated with the first quantity of write operations, wherein determining to refrain from performing the first wear leveling operation is based at least in part on the determining whether to perform the first wear leveling operation; (Danielson paragraph [0039], FIG. 4B illustrates an example of determining whether to store other data at a memory device based on the usage of the memory devices 450, in accordance with embodiments of the present disclosure. In the present illustration, the actual usage of a memory cell of memory device 420 is 94 write operations performed on a memory cell of memory device 420. Because the actual usage of the memory cell of memory device 420 is less than the usage threshold (e.g., 100 write operations) for memory device 420, data can be stored at the memory cell of the memory device 420. The actual usage of a memory cell of memory device 430, however, is 50 write operations performed on a memory cell of memory device 430. Because the actual usage of the memory cell (e.g., 50 write operations) exceeds the usage threshold (e.g., 50) for memory device 430, data is not stored at the memory cell of memory device 430. The process for a wear leveling operation (determining which memory blocks/cells are viable for storage and using them according to said determinations) can be based on various usage characteristics such as write operation quantity, as indicated here. For further details regarding the usage characteristic being used for wear leveling operations, see Danielson paragraphs [0022-0023], The controller 115 can include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory system 110, including handling communications between the memory system 110 and the host system 120. In some embodiments, the local memory 119 can include memory registers storing memory pointers, fetched data, etc. The local memory 119 can also include read-only memory (ROM) for storing micro-code. While the example memory system 110 in FIG. 1 has been illustrated as including the controller 115, in another embodiment of the present disclosure, a memory system 110 may not include a controller 115, and may instead rely upon external control (e.g., provided by an external host, or by a processor or controller separate from the memory system). In general, the controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 112A to 112N. The controller 115 can be responsible for other operations such as wear leveling operations) and determining whether to perform the second wear leveling operation in accordance with a second rate of evaluation, less than the first rate of evaluation, that is associated with the second quantity of write operations (Danielson paragraph [0029], In embodiments, multiple usage thresholds can be assigned to a memory device of the memory system. The multiple usage thresholds can be based on the endurance of the memory device to store data. For example, a first memory device can have an associated endurance of 1,000,000 total bytes written to a memory cell of the first memory device, at which point the first memory device can no longer store data. In one embodiment, the multiple usage thresholds can be a portion, such as a percentage, of the endurance of the first memory device to store data or the endurance of the first memory device to store data. For example, the first memory device can have one usage threshold corresponding to 900,000 total bytes written to a memory cell of the first memory device and another usage threshold corresponding to 1,000,000 total bytes written to the memory cell of the first memory device. In embodiments, the first usage threshold and second usage threshold can be determined based on a received input from a host system. In other embodiments, the first usage threshold and the second usage threshold may be based on a portion, such as a percentage, of the endurance of the first memory device and the second memory device to reliably store data. For example, if a memory cell of a memory device can have 1,000,000 total bytes written to the memory cell before the memory cell can no longer reliably store data, then the usage threshold for the memory device can be 900,000 total bytes written (e.g., 90%) to a memory cell of the memory device. The amount of write operations that can be performed is largely based on the memory device/memory units themselves, but can be adjusted based on the thresholds set, resulting in either a larger or lesser first quantity).
Regarding claim 14, Danielson in view of Monteleone in further view of Kwon teaches The method of claim 11, further comprising: receiving a first set of one or more commands from a host system, wherein performing the first quantity of write operations is based at least in part on the first set of one or more commands from the host system; and receiving a second set of one or more commands from the host system, wherein performing the second quantity of write operations is based at least in part on the second set of one or more commands from the host system (Danielson paragraph [0023], In general, the controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 112A to 112N. The controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical block address and a physical block address that are associated with the memory devices 112A to 112N. The controller 115 can further include host interface circuitry to communicate with the host system 120 via the physical host interface. The host interface circuitry can convert the commands received from the host system into command instructions to access the memory devices 112A to 112N as well as convert responses associated with the memory devices 112A to 112N into information for the host system 120. A plurality of first and second write operations may be received from the host by the memory device/controller and subsequently performed/executed).
Regarding claim 15, Danielson in view of Monteleone in further view of Kwon teaches The method of claim 11, wherein write operations of the first quantity of write operations and of the second quantity of write operations are associated with migrating data from memory cells of the memory system that are associated with a first storage density to memory cells of the memory system that are associated with a second storage density (Danielson paragraphs [0033-0034], At block 330, a determination is made as to whether a corresponding usage threshold of the first memory device or the second memory device has been exceeded. For purposes of the present disclosure, a usage threshold can be exceeded when a value is greater than or equal to the usage threshold. For example, if the first usage threshold for the first memory device is 1,000,000 total bytes written to a memory cell of the first memory device and a memory cell of the first memory device has had 1,000,000 total bytes written to the memory cell, then the first usage threshold has been exceeded. If a usage threshold for the first memory device and/or the second memory device has not been exceeded, then at block 340, subsequent data is stored at the first memory device or the second memory device. The subsequent data can be received from a host system for storage by the memory system. In one embodiment, if the usage thresholds for the memory devices have not been exceeded, the subsequent data can be stored at the first memory device or second memory device based on characteristics associated with the subsequent data. The storage density (i.e., the number of bits in a given allocation of memory storage) can be used to determine the write operation characteristics. Also see Danielson paragraphs [0015-0016], Generally, in order to obtain the different desired characteristics of memory devices, multiple conventional memory systems having different media types and associated characteristics can be used with a host system. For example, a host system can be coupled to a first conventional memory system having a first media type with a high data density, a second conventional memory system having a second media type with a high access speed, and a third conventional memory system having a third media type with a high endurance. However, using multiple memory systems to achieve the different desired characteristics for the storage of data is costly and inefficient as the host system would utilize additional connections to each of the different memory systems).
Regarding claim 16, Danielson in view of Monteleone in further view of Kwon teaches The method of claim 11, further comprising: determining that a lowest quantity of program/erase cycles associated with a plurality of blocks of memory cells of the memory system satisfies a threshold, wherein determining to perform the first wear leveling operation at a memory system is based at least in part on determining that the lowest quantity of program/erase cycles satisfies the threshold (Danielson paragraph [0013], Other characteristics of a memory device can be associated with the endurance of the memory device to store data. When data is written to and/or erased from a memory cell of a memory device, the memory cell can be damaged. As the number of write operations and/or erase operations performed on a memory cell increases, the probability that the data stored at the memory cell including an error increase as the memory cell is increasingly damaged. A characteristic associated with the endurance of the memory device is the number of write operations or a number of program/erase operations performed on a memory cell of the memory device. If a threshold number of write operations performed on the memory cell is exceeded, then data can no longer be reliably stored at the memory cell as the data can include a large number of errors that cannot be corrected. Different media types can also have difference endurances for storing data. For example, a first media type can have a threshold of 1,000,000 write operations, while a second media type can have a threshold of 2,000,000 write operations. Accordingly, the endurance of the first media type to store data is less than the endurance of the second media type to store data. Program/erase cycle data can be utilized to determine the appropriate wear leveling operations when compared to a threshold value).
Regarding claim 17, Danielson in view of Monteleone in further view of Kwon teaches The method of claim 11, wherein performing the first wear leveling operation comprises: reading information from a first block of memory cells associated with a lowest quantity of program/erase cycles; and writing the information to a second block of memory cells different than the first block of memory cells (Danielson paragraph [0022], The controller 115 can communicate with the memory devices 112A to 112N to perform operations such as reading data, writing data, or erasing data at the memory devices 112A to 112N and other such operations. The controller 115 can include hardware such as one or more integrated circuits and/or discrete components, a buffer memory, or a combination thereof. The controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor. The controller 115 can include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory system 110, including handling communications between the memory system 110 and the host system 120. In some embodiments, the local memory 119 can include memory registers storing memory pointers, fetched data, etc. The local memory 119 can also include read-only memory (ROM) for storing micro-code. While the example memory system 110 in FIG. 1 has been illustrated as including the controller 115, in another embodiment of the present disclosure, a memory system 110 may not include a controller 115, and may instead rely upon external control (e.g., provided by an external host, or by a processor or controller separate from the memory system). The lowest quantity of program/erase cycles may be classified as a read-only memory unit resulting in a read operation being performed to transfer the corresponding data).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Danielson in view of Monteleone in further view of Kwon as applied to claim 1 above, and further in view of Tai et al. (US Publication No. 2020/0065007 -- "Tai").
Regarding claim 8, Danielson in view of Monteleone in further view of Kwon and further in view of Tai teaches The method of claim 1, further comprising: performing the second wear leveling operation at the memory system based at least in part on determining to perform the second wear leveling operation; (Danielson paragraphs [0037-0038], FIG. 4A illustrates an example of determining whether to store data at a memory device based on the usage of the memory devices 400, in accordance with some embodiments of the present disclosure. Memory system 410 includes memory devices 420 and 430. In one embodiment, memory device 420 includes a first media type having a first endurance to store data and memory device 430 includes a second media type having a second endurance to store data. For illustrative purposes, memory device 420 has a usage threshold of 100 and memory device 430 has a usage threshold of 50. In one embodiment, the usage thresholds and actual usages can correspond to a number of bytes written to a memory cell of the memory device. In embodiments, the usage thresholds and actual usages can correspond to a number of write operations performed on a memory cell of the memory device. In the present illustration, the actual usage of a memory cell of memory device 420 is 82 write operations performed on a memory cell of memory device 420. Because the actual usage of the memory cell (e.g., 82 write operations) of memory device 420 is less than the usage threshold (e.g., 100 write operations) for memory device 420, data can be stored at memory device 420. The actual usage of a memory cell of memory device 430 is 37 write operations performed on a memory cell of memory device 430. Because the actual usage of the memory cell (e.g., 37 write operations) is less than the usage threshold (e.g., 50 write operations) for memory device 430, data can be stored at memory device 430. The wear leveling operation will determine the quantity of write operations that can be performed on a corresponding memory unit, as well as the determination of whether that usage characteristic (i.e., second quantity of write operations) exceeds a threshold resulting in a necessary wear leveling operation) determining a third quantity of write operations at the memory system, less than the second quantity of write operations, based at least in part on determining to perform the second wear leveling operation; and determining whether to perform a third wear leveling operation at the memory system based at least in part on performing the third quantity of write operations at the memory system (Tai paragraph [0015], Aspects of the disclosure address the above and other deficiencies by implementing multi-level wear leveling for non-volatile memory. In one implementation, multi-level wear leveling utilizes a hierarchy of levels of data units having different sizes. For example, a first level can represent individual data units, such as a data block or page of a memory component (which can also be referred to herein as a “management unit”), while a second level can represent a group of multiple data units (which can also be referred to herein as a “super management unit”). A third level can represent group of multiple groups of data units from the second level (i.e., a group of super management units). Depending on the embodiment, there can be any number of different levels in the hierarchy, each operating on successively larger groups of data units. Wear leveling can be performed at each level of the hierarchy using different wear leveling techniques and at different frequencies. For example, multi-level wear leveling can include wear leveling at the first level using algebraic mapping implemented by a first function every five minutes or every 1000 host writes, and wear leveling at the second level using algebraic mapping implemented by a second function every 30 minutes or every 5000 host writes. The second mapping function can be either the same or different than the first mapping function, depending on the embodiment. Wear leveling at the third level can be performed using algebraic mapping implemented by a third function or by using indirect fully associative mapping implemented by a look-up table every one hour or every 10,000 host writes. In other implementations, the wear leveling techniques and/or the associated frequencies can vary as appropriate. The multi-level wear leveling scheme described herein allows for efficient and effective wear leveling in memory sub-systems having high numbers of data units, such as when in-place data replacement media is used, and having large storage capacities without resulting in the look-up table used at the third level becoming excessively large in size. A third instance of wear-leveling may be performed if required, and can be based on a third set of write operations and the corresponding quantity (i.e., a predetermined threshold value)).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Danielson, Monteleone and Kwon with those of Tai. Tai teaches using a third wear leveling operation based on a third quantity of a set of write operations. The more frequently wear leveling operations are performed, the more likely the memory system as a whole is to have an extended lifespan and perform at an ideal level (Tai paragraph [0015], Aspects of the disclosure address the above and other deficiencies by implementing multi-level wear leveling for non-volatile memory. In one implementation, multi-level wear leveling utilizes a hierarchy of levels of data units having different sizes. For example, a first level can represent individual data units, such as a data block or page of a memory component (which can also be referred to herein as a “management unit”), while a second level can represent a group of multiple data units (which can also be referred to herein as a “super management unit”). A third level can represent group of multiple groups of data units from the second level (i.e., a group of super management units). Depending on the embodiment, there can be any number of different levels in the hierarchy, each operating on successively larger groups of data units. Wear leveling can be performed at each level of the hierarchy using different wear leveling techniques and at different frequencies. For example, multi-level wear leveling can include wear leveling at the first level using algebraic mapping implemented by a first function every five minutes or every 1000 host writes, and wear leveling at the second level using algebraic mapping implemented by a second function every 30 minutes or every 5000 host writes. The second mapping function can be either the same or different than the first mapping function, depending on the embodiment. Wear leveling at the third level can be performed using algebraic mapping implemented by a third function or by using indirect fully associative mapping implemented by a look-up table every one hour or every 10,000 host writes. In other implementations, the wear leveling techniques and/or the associated frequencies can vary as appropriate).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Danielson in view of Monteleone in further view of Kwon as applied to claim 1 above, and further in view of Tai and further in view of Franklin et al. (US Publication No. 2018/0285007 -- "Franklin").
Regarding claim 9, Danielson in view of Monteleone in further view of Kwon in further view of Tai teaches The method of claim 1, further comprising: performing, prior to performing the first quantity of write operations, a third quantity of write operations; (Danielson paragraph [0023], In general, the controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 112A to 112N. The controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical block address and a physical block address that are associated with the memory devices 112A to 112N. The controller 115 can further include host interface circuitry to communicate with the host system 120 via the physical host interface. The host interface circuitry can convert the commands received from the host system into command instructions to access the memory devices 112A to 112N as well as convert responses associated with the memory devices 112A to 112N into information for the host system 120. A plurality of first and second write operations may be received from the host by the memory device/controller and subsequently performed/executed) determining the first quantity of write operations at the memory system, greater than the third quantity of write operations, based at least in part on determining to not perform the third wear leveling operation; and determining whether to perform the first wear leveling operation at the memory system based at least in part on performing the first quantity of write operations at the memory system (Tai paragraph [0015], Aspects of the disclosure address the above and other deficiencies by implementing multi-level wear leveling for non-volatile memory. In one implementation, multi-level wear leveling utilizes a hierarchy of levels of data units having different sizes. For example, a first level can represent individual data units, such as a data block or page of a memory component (which can also be referred to herein as a “management unit”), while a second level can represent a group of multiple data units (which can also be referred to herein as a “super management unit”). A third level can represent group of multiple groups of data units from the second level (i.e., a group of super management units). Depending on the embodiment, there can be any number of different levels in the hierarchy, each operating on successively larger groups of data units. Wear leveling can be performed at each level of the hierarchy using different wear leveling techniques and at different frequencies. For example, multi-level wear leveling can include wear leveling at the first level using algebraic mapping implemented by a first function every five minutes or every 1000 host writes, and wear leveling at the second level using algebraic mapping implemented by a second function every 30 minutes or every 5000 host writes. The second mapping function can be either the same or different than the first mapping function, depending on the embodiment. Wear leveling at the third level can be performed using algebraic mapping implemented by a third function or by using indirect fully associative mapping implemented by a look-up table every one hour or every 10,000 host writes. In other implementations, the wear leveling techniques and/or the associated frequencies can vary as appropriate. The multi-level wear leveling scheme described herein allows for efficient and effective wear leveling in memory sub-systems having high numbers of data units, such as when in-place data replacement media is used, and having large storage capacities without resulting in the look-up table used at the third level becoming excessively large in size. A third instance of wear-leveling may be performed if required, and can be based on a third set of write operations and the corresponding quantity (i.e., a predetermined threshold value)).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Danielson and Monteleone and Kwon with those of Tai. Tai teaches using a third wear leveling operation based on a third quantity of a set of write operations. The more frequently wear leveling operations are performed, the more likely the memory system as a whole is to have an extended lifespan and perform at an ideal level (Tai paragraph [0015], Aspects of the disclosure address the above and other deficiencies by implementing multi-level wear leveling for non-volatile memory. In one implementation, multi-level wear leveling utilizes a hierarchy of levels of data units having different sizes. For example, a first level can represent individual data units, such as a data block or page of a memory component (which can also be referred to herein as a “management unit”), while a second level can represent a group of multiple data units (which can also be referred to herein as a “super management unit”). A third level can represent group of multiple groups of data units from the second level (i.e., a group of super management units). Depending on the embodiment, there can be any number of different levels in the hierarchy, each operating on successively larger groups of data units. Wear leveling can be performed at each level of the hierarchy using different wear leveling techniques and at different frequencies. For example, multi-level wear leveling can include wear leveling at the first level using algebraic mapping implemented by a first function every five minutes or every 1000 host writes, and wear leveling at the second level using algebraic mapping implemented by a second function every 30 minutes or every 5000 host writes. The second mapping function can be either the same or different than the first mapping function, depending on the embodiment. Wear leveling at the third level can be performed using algebraic mapping implemented by a third function or by using indirect fully associative mapping implemented by a look-up table every one hour or every 10,000 host writes. In other implementations, the wear leveling techniques and/or the associated frequencies can vary as appropriate).
Danielson in view of Monteleone in further view of Kwon in further view of Tai does not teach refraining from performing a third wear leveling operation at the memory system prior to performing the first wear leveling operation based at least in part on determining to not perform the third wear leveling operation.
However, Franklin teaches refraining from performing a third wear leveling operation at the memory system prior to performing the first wear leveling operation based at least in part on determining to not perform the third wear leveling operation (Franklin paragraph [0122], A means for selectively skipping wear leveling in response to receiving one or more refresh commands and/or triggers, in various embodiments, may include a maintenance component 150, a maintenance circuit 506, a wear leveling circuit 604, a refresh circuit 602, a retirement circuit 606, a read/write circuit 504, a device controller 126, an on-die controller 220, a state machine 222, an integrated circuit device, an FPGA, an ASIC, other logic hardware, and/or other executable code stored on a computer readable storage medium. Other embodiments may include similar and/or equivalent means for selectively skipping wear leveling in response to receiving one or more refresh commands and/or triggers. The wear level operations can be chosen to be skipped in certain circumstances).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Danielson, Monteleone, Kwon and Tai with those of Franklin. Franklin teaches a means for a memory apparatus to skip a potential wear leveling operation. This can be performed in the event that a wear leveling operation is determined to be redundant, unnecessary, or an operation performing a similar function is already scheduled (Franklin paragraph [0037], By performing a maintenance operation or portion thereof in response to a refresh command, instead of, or in addition to, performing the maintenance operation in the background, in some embodiments, a maintenance component 150 may allow a non-volatile memory element 123 and/or a non-volatile memory device 120 to operate synchronously (e.g., responding to a storage request such as a read or write request with little or no delay from performing a background maintenance operation and/or otherwise communicating synchronously with a host 110, a processor 111, or the like). Synchronous operation of a non-volatile memory device 120 and/or a non-volatile memory element 123, as used herein, comprises a non-volatile memory device 120 and/or a non-volatile memory element 123 recognizing control inputs (e.g., commands, data, addresses, or the like) in response to an external clock input (e.g., over a memory bus 125 or the like). Also see Franklin paragraph [0041], However, for compatibility with the same host memory controller and/or refresh command, in certain embodiments, a maintenance component 150 may perform one or more maintenance operations or a portion thereof on non-volatile memory cells of a non-volatile memory medium 122 of one or more non-volatile memory elements 123 in response to a refresh command. For example, a maintenance component 150 may instead, or on occasion, use or repurpose some or all of the refresh commands to perform a different maintenance operation for a type of memory medium 122 that doesn't require a volatile memory refresh operation such as storage class memory or other non-volatile memory, and/or may perform a different type of maintenance operation for a memory medium 122 that does require a volatile memory refresh operation (e.g., in addition to a volatile memory refresh operation), or the like).
Claim(s) 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Danielson in view of Monteleone in further view of Kwon as applied to claim 11 above, and further in view of Tai.
Regarding claim 18, Danielson in view of Monteleone in further view of Kwon in further view of Tai teaches The method of claim 11, further comprising: performing the second wear leveling operation at the memory system based at least in part on determining to perform the second wear leveling operation; (Danielson paragraph [0039], FIG. 4B illustrates an example of determining whether to store other data at a memory device based on the usage of the memory devices 450, in accordance with embodiments of the present disclosure. In the present illustration, the actual usage of a memory cell of memory device 420 is 94 write operations performed on a memory cell of memory device 420. Because the actual usage of the memory cell of memory device 420 is less than the usage threshold (e.g., 100 write operations) for memory device 420, data can be stored at the memory cell of the memory device 420. The actual usage of a memory cell of memory device 430, however, is 50 write operations performed on a memory cell of memory device 430. Because the actual usage of the memory cell (e.g., 50 write operations) exceeds the usage threshold (e.g., 50) for memory device 430, data is not stored at the memory cell of memory device 430. The process for a wear leveling operation (determining which memory blocks/cells are viable for storage and using them according to said determinations) can be based on various usage characteristics such as write operation quantity, as indicated here. For further details regarding the usage characteristic being used for wear leveling operations, see Danielson paragraphs [0022-0023], The controller 115 can include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory system 110, including handling communications between the memory system 110 and the host system 120. In some embodiments, the local memory 119 can include memory registers storing memory pointers, fetched data, etc. The local memory 119 can also include read-only memory (ROM) for storing micro-code. While the example memory system 110 in FIG. 1 has been illustrated as including the controller 115, in another embodiment of the present disclosure, a memory system 110 may not include a controller 115, and may instead rely upon external control (e.g., provided by an external host, or by a processor or controller separate from the memory system). In general, the controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 112A to 112N. The controller 115 can be responsible for other operations such as wear leveling operations) determining a third quantity of write operations at the memory system, less than the second quantity of write operations, based at least in part on determining to perform the second wear leveling operation; and determining whether to perform a third wear leveling operation at the memory system based at least in part on performing the third quantity of write operations at the memory system (Tai paragraph [0015], Aspects of the disclosure address the above and other deficiencies by implementing multi-level wear leveling for non-volatile memory. In one implementation, multi-level wear leveling utilizes a hierarchy of levels of data units having different sizes. For example, a first level can represent individual data units, such as a data block or page of a memory component (which can also be referred to herein as a “management unit”), while a second level can represent a group of multiple data units (which can also be referred to herein as a “super management unit”). A third level can represent group of multiple groups of data units from the second level (i.e., a group of super management units). Depending on the embodiment, there can be any number of different levels in the hierarchy, each operating on successively larger groups of data units. Wear leveling can be performed at each level of the hierarchy using different wear leveling techniques and at different frequencies. For example, multi-level wear leveling can include wear leveling at the first level using algebraic mapping implemented by a first function every five minutes or every 1000 host writes, and wear leveling at the second level using algebraic mapping implemented by a second function every 30 minutes or every 5000 host writes. The second mapping function can be either the same or different than the first mapping function, depending on the embodiment. Wear leveling at the third level can be performed using algebraic mapping implemented by a third function or by using indirect fully associative mapping implemented by a look-up table every one hour or every 10,000 host writes. In other implementations, the wear leveling techniques and/or the associated frequencies can vary as appropriate. The multi-level wear leveling scheme described herein allows for efficient and effective wear leveling in memory sub-systems having high numbers of data units, such as when in-place data replacement media is used, and having large storage capacities without resulting in the look-up table used at the third level becoming excessively large in size. A third instance of wear-leveling may be performed if required, and can be based on a third set of write operations and the corresponding quantity (i.e., a predetermined threshold value)).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Danielson, Monteleone and Kwon with those of Tai. Tai teaches using a third wear leveling operation based on a third quantity of a set of write operations. The more frequently wear leveling operations are performed, the more likely the memory system as a whole is to have an extended lifespan and perform at an ideal level (Tai paragraph [0015], Aspects of the disclosure address the above and other deficiencies by implementing multi-level wear leveling for non-volatile memory. In one implementation, multi-level wear leveling utilizes a hierarchy of levels of data units having different sizes. For example, a first level can represent individual data units, such as a data block or page of a memory component (which can also be referred to herein as a “management unit”), while a second level can represent a group of multiple data units (which can also be referred to herein as a “super management unit”). A third level can represent group of multiple groups of data units from the second level (i.e., a group of super management units). Depending on the embodiment, there can be any number of different levels in the hierarchy, each operating on successively larger groups of data units. Wear leveling can be performed at each level of the hierarchy using different wear leveling techniques and at different frequencies. For example, multi-level wear leveling can include wear leveling at the first level using algebraic mapping implemented by a first function every five minutes or every 1000 host writes, and wear leveling at the second level using algebraic mapping implemented by a second function every 30 minutes or every 5000 host writes. The second mapping function can be either the same or different than the first mapping function, depending on the embodiment. Wear leveling at the third level can be performed using algebraic mapping implemented by a third function or by using indirect fully associative mapping implemented by a look-up table every one hour or every 10,000 host writes. In other implementations, the wear leveling techniques and/or the associated frequencies can vary as appropriate).
Regarding claim 19, Danielson in view of Monteleone in further view of Kwon in further view of Tai teaches The method of claim 11, further comprising: refraining from performing the second wear leveling operation at the memory system based at least in part on determining to not perform the second wear leveling operation; (Monteleone paragraph [0019], Additionally or alternatively, in some examples, the memory 120 may be configured to track a number of write operations performed on each block of an array associated with the memory 120. In particular, the memory 120 may track a “local write count” for each block, or a number of write operations performed by the memory 120 on each block since the memory 120 last performed a wear leveling operation. Once a local write count has exceeded a threshold, the memory 120 may recommend the host 110 provide a wear leveling command, and in some instances, the memory 120 may selectively ignore wearing commands based on the local write count. In this manner, the memory 120 may recommend the host 110 provide a wear leveling command in response to performing an operation at a particular block (e.g., maximum cycled block) a particular number of times since last performing a wear leveling operation. If the wear leveling command is ignored, a second quantity of write operations may be tracked and if exceeding a determined amount, a wear leveling operation may be automatically performed) determining a third quantity of write operations at the memory system, greater than the second quantity of write operations, based at least in part on determining to not perform the second wear leveling operation; and determining whether to perform the wear leveling operation at the memory system based at least in part on performing the third quantity of write operations at the memory system (Tai paragraph [0015], Aspects of the disclosure address the above and other deficiencies by implementing multi-level wear leveling for non-volatile memory. In one implementation, multi-level wear leveling utilizes a hierarchy of levels of data units having different sizes. For example, a first level can represent individual data units, such as a data block or page of a memory component (which can also be referred to herein as a “management unit”), while a second level can represent a group of multiple data units (which can also be referred to herein as a “super management unit”). A third level can represent group of multiple groups of data units from the second level (i.e., a group of super management units). Depending on the embodiment, there can be any number of different levels in the hierarchy, each operating on successively larger groups of data units. Wear leveling can be performed at each level of the hierarchy using different wear leveling techniques and at different frequencies. For example, multi-level wear leveling can include wear leveling at the first level using algebraic mapping implemented by a first function every five minutes or every 1000 host writes, and wear leveling at the second level using algebraic mapping implemented by a second function every 30 minutes or every 5000 host writes. The second mapping function can be either the same or different than the first mapping function, depending on the embodiment. Wear leveling at the third level can be performed using algebraic mapping implemented by a third function or by using indirect fully associative mapping implemented by a look-up table every one hour or every 10,000 host writes. In other implementations, the wear leveling techniques and/or the associated frequencies can vary as appropriate. The multi-level wear leveling scheme described herein allows for efficient and effective wear leveling in memory sub-systems having high numbers of data units, such as when in-place data replacement media is used, and having large storage capacities without resulting in the look-up table used at the third level becoming excessively large in size. A third instance of wear-leveling may be performed if required, and can be based on a third set of write operations and the corresponding quantity (i.e., a predetermined threshold value)).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Danielson, Monteleone and Kwon with those of Tai. Tai teaches using a third wear leveling operation based on a third quantity of a set of write operations. The more frequently wear leveling operations are performed, the more likely the memory system as a whole is to have an extended lifespan and perform at an ideal level (Tai paragraph [0015], Aspects of the disclosure address the above and other deficiencies by implementing multi-level wear leveling for non-volatile memory. In one implementation, multi-level wear leveling utilizes a hierarchy of levels of data units having different sizes. For example, a first level can represent individual data units, such as a data block or page of a memory component (which can also be referred to herein as a “management unit”), while a second level can represent a group of multiple data units (which can also be referred to herein as a “super management unit”). A third level can represent group of multiple groups of data units from the second level (i.e., a group of super management units). Depending on the embodiment, there can be any number of different levels in the hierarchy, each operating on successively larger groups of data units. Wear leveling can be performed at each level of the hierarchy using different wear leveling techniques and at different frequencies. For example, multi-level wear leveling can include wear leveling at the first level using algebraic mapping implemented by a first function every five minutes or every 1000 host writes, and wear leveling at the second level using algebraic mapping implemented by a second function every 30 minutes or every 5000 host writes. The second mapping function can be either the same or different than the first mapping function, depending on the embodiment. Wear leveling at the third level can be performed using algebraic mapping implemented by a third function or by using indirect fully associative mapping implemented by a look-up table every one hour or every 10,000 host writes. In other implementations, the wear leveling techniques and/or the associated frequencies can vary as appropriate).
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Danielson et al. (US Publication No. 2019/0332317 -- "Danielson") in view of Monteleone et al. (US Publication No. 2019/0347012 – “Monteleone”) in further view of Zhu et al. (US Publication No. 2021/0064248 – “Zhu”).
Regarding claim 21, Danielson teaches A method, comprising: performing wear leveling at a plurality of blocks of memory cells of a memory system (see Danielson paragraph [0012] for memory system comprising blocks of memory cells) in accordance with a first rate, the first rate corresponding to a first quantity of access operations performed prior to performing wear leveling operations; determining that a wear characteristic of the plurality of blocks of memory cells memory system satisfies a threshold; (Danielson paragraph [0018], However, as previously discussed, memory devices having different media types can have different endurances and different respective threshold for storing data at the memory devices. The data can be stored at the memory devices based on the determined usage thresholds. For example, if a first memory device of the memory system is at or near a first usage threshold that indicates that the first memory device is at or near a point where the first memory device can no longer reliably store data, then data can be stored at another memory device of the memory system. By providing data to the different memory devices of the memory system based on different determined usage thresholds, the wear (e.g., number of operations performed on a memory device and/or an amount of data written to the memory device) on the multiple memory devices of the memory system can be more evenly distributed, preventing the premature failure of a particular memory device of a memory system relative to the other memory devices of the memory system. The wear leveling operations may be performed at a predetermined threshold level of wear in the memory system, wherein the rate of performing the wear leveling operation is set by the usage thresholds, also see Danielson paragraph [0023], In general, the controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 112A to 112N. The controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical block address and a physical block address that are associated with the memory devices 112A to 112N. The controller 115 can further include host interface circuitry to communicate with the host system 120 via the physical host interface. The host interface circuitry can convert the commands received from the host system into command instructions to access the memory devices 112A to 112N as well as convert responses associated with the memory devices 112A to 112N into information for the host system 120).
Danielson does not teach determining that a wear characteristic of the plurality of blocks of memory cells of the memory system satisfies a threshold based at least in part on a quantity of access operations between determining to refrain from performing a first wear leveling operation and determining to refrain from performing a second wear leveling operation satisfying a threshold quantity of access operations; performing the wear leveling at the plurality of blocks of memory cells of the memory system in accordance with a second rate of performing wear leveling operations based at least in part on determining that the wear characteristic satisfies the threshold, the second rate corresponding to a second quantity of access operations performed prior to performing the wear leveling operations, the second quantity different than the first quantity.
However, Monteleone teaches teach determining that a wear characteristic of the plurality of blocks of memory cells of the memory system satisfies a threshold based at least in part on a quantity of access operations between determining to refrain from performing a first wear leveling operation and determining to refrain from performing a second wear leveling operation satisfying a threshold quantity of access operations; (Monteleone paragraph [0019], Additionally or alternatively, in some examples, the memory 120 may be configured to track a number of write operations performed on each block of an array associated with the memory 120. In particular, the memory 120 may track a “local write count” for each block, or a number of write operations performed by the memory 120 on each block since the memory 120 last performed a wear leveling operation. Once a local write count has exceeded a threshold, the memory 120 may recommend the host 110 provide a wear leveling command, and in some instances, the memory 120 may selectively ignore wearing commands based on the local write count. In this manner, the memory 120 may recommend the host 110 provide a wear leveling command in response to performing an operation at a particular block (e.g., maximum cycled block) a particular number of times since last performing a wear leveling operation. The memory can repeatedly determine to refrain from performing the wear leveling operations, but can issue the wear leveling command based on a number of commands since the last wear leveling operation being performed being greater than a determined amount).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Danielson with those of Monteleone. Monteleone teaches using a second quantity of write operations, tracked after performing a wear leveling operation, which can provide a more efficient wear leveling system minimizing processing demands while maximizing the lifespan of said memory (Monteleone paragraph [0037], Accordingly, the memory control unit 310 may perform a wear leveling operation such that the logical address LBAm may be associated with the physical address PBAM and thus the maximum cycled block of the array 504. Additionally, the logical address SPARE may be associated with the physical address PBAm and thus the minimum cycled block BLOCK3 of the array 504, and the logical address LBAM may be associated with the physical address PBAi and thus becoming the spare block of the array 504. Assigning addresses in this manner may, for instance, more evenly distribute write operations among blocks BLOCK0-BLOCK7 of the array 504 and thereby provide prolonged operation of the array 504).
Danielson in view of Monteleone does not teach performing the wear leveling at the plurality of blocks of memory cells of the memory system in accordance with a second rate of performing wear leveling operations based at least in part on determining that the wear characteristic satisfies the threshold, the second rate corresponding to a second quantity of access operations performed prior to performing the wear leveling operations, the second quantity different than the first quantity.
However, Zhu teaches performing the wear leveling at the memory system in accordance with a second rate of performing wear leveling operations based at least in part on determining that the wear characteristic satisfies the threshold, the second rate corresponding to a second quantity of access operations performed prior to performing the wear leveling operations, the second quantity different than the first quantity. (Zhu paragraph [0014], Aspects of the present disclosure address the above and other deficiencies by having a memory sub-system that can perform or coordinate one or more wear leveling operations. Cold swapping of memory cells can include identifying memory cells for wear-leveling operations that are not being accessed as much as "hoť" memory cells for hot swapping described above. For example, the memory sub-system can count the number of write operations (e.g., write counts) performed on memory cells in a mapped region of SMUs (e.g., a region of the SMUs to which memory cells are actively being written). The memory sub-system can compare a minimum number of write operations performed on all SMUs in the mapped region (e.g., the minimum write count) with a minimum number of write operations (e.g., the minimum write count) performed on memory cells in an unmapped region of SMUs (e.g., a region of the SMUs to which memory cells are not actively being written). The memory sub-system can identify the SMU with the minimum write count in the unmapped region. In some cases, when the minimum write count of the SMU in the mapped region is less than the minimum write count of the SMU in the unmapped region, the memory sub-system can swap data stored in the two SMUs. In such cases, the memory sub-system can write to the formerly unmapped SMU (e.g., swapped to the mapped region), and the memory sub-system can stop writing to the formerly mapped SMU (e.g., swapped to the unmapped region). Performing such an operation can more evenly spread the wear between mapped and unmapped SMUs throughout the memory device. The write counts of the SMUs, however, can be difficult to track because the memory subsystem is constantly writing to many SMUs in the memory device. As such the write count can be constantly changing. Therefore, determining the SMU with the minimum write count can be take many clock cycles, in some cases, because the write counts of SMUs can be constantly changing, thereby causing frequent scans of the write counts. Furthermore, performing scans for the current write counts can introduce latency in the memory sub-system's operation because counting the current write count for all SMUS can use a large amount of data processing that can use processing resources of the memory sub-system. The frequency of second wear leveling operations can be correlated to clock cycles or write count thresholds).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Danielson and Monteleone with those of Zhu. Zhu teaches using a first and second quantity of write operations to determine whether to perform a first and second wear leveling operation, which can provide a more efficient wear leveling system minimizing processing demands while maximizing the lifespan of said memory (Zhu paragraph [0014], Aspects of the present disclosure address the above and other deficiencies by having a memory sub-system that can perform or coordinate one or more wear leveling operations. Cold swapping of memory cells can include identifying memory cells for wear-leveling operations that are not being accessed as much as “hot” memory cells for hot swapping described above. For example, the memory sub-system can count the number of write operations (e.g., write counts) performed on memory cells in a mapped region of SMUs (e.g., a region of the SMUs to which memory cells are actively being written). The memory sub-system can compare a minimum number of write operations performed on all SMUs in the mapped region (e.g., the minimum write count) with a minimum number of write operations (e.g., the minimum write count) performed on memory cells in an unmapped region of SMUs).
Claim(s) 22-27 and 29-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Danielson in view of Monteleone in further view of Zhu as applied to claim 21 above, and further in view of Franklin.
Regarding claim 22, Danielson in view of Monteleone in further view of Zhu in further view of Franklin teaches The method of claim 21, wherein: performing the wear leveling at the memory system in accordance with the first rate comprises evaluating, in accordance with the first rate, whether a lowest quantity of program/erase cycles associated with a plurality of blocks of memory cells of the memory system satisfies a second threshold; (Danielson paragraph [0013], Other characteristics of a memory device can be associated with the endurance of the memory device to store data. When data is written to and/or erased from a memory cell of a memory device, the memory cell can be damaged. As the number of write operations and/or erase operations performed on a memory cell increases, the probability that the data stored at the memory cell including an error increase as the memory cell is increasingly damaged. A characteristic associated with the endurance of the memory device is the number of write operations or a number of program/erase operations performed on a memory cell of the memory device. If a threshold number of write operations performed on the memory cell is exceeded, then data can no longer be reliably stored at the memory cell as the data can include a large number of errors that cannot be corrected. Different media types can also have difference endurances for storing data. For example, a first media type can have a threshold of 1,000,000 write operations, while a second media type can have a threshold of 2,000,000 write operations. Accordingly, the endurance of the first media type to store data is less than the endurance of the second media type to store data. The program/erase cycles can be set with a plurality of thresholds to utilize for operation selection and determination) and performing the wear leveling at the memory system in accordance with the second rate comprises evaluating, in accordance with the second rate, whether the lowest quantity of program/erase cycles associated with the plurality of blocks of memory cells of the memory system satisfies the second threshold (Franklin paragraph [0096], As described below with regard to the wear leveling circuit 604 of FIG. 6, in certain embodiments, the maintenance circuit 506 performs a maintenance operation comprising a memory wear leveling operation. For example, the maintenance circuit 506 may perform a memory wear leveling operation reading data from a region of a non-volatile memory element 123 and writing at least a portion of the read data to a different region of a non-volatile memory element 123 (e.g., providing wear leveling between different regions of one or more non-volatile memory elements 123, such as a block, a page, a word line, a die, a die plane, a chip, and/or another region of memory). For example, the maintenance circuit 506 may perform a memory wear leveling operation or other maintenance operations such as a garbage collection or storage capacity recovery operation to move valid data to a different region of memory while recovering storage capacity of unused or invalid data, rewriting data to a different region of memory to prevent data loss, or the like during a predefined period of time after the interface circuit 502 receives a refresh command (e.g., periodically in response to a predefined temperature condition, a predefined time condition, a predefined read disturb condition, a predefined write disturb condition, or the like being satisfied prior to the interface circuit 502 receiving the refresh command, or the like). The rate of performing wear leveling operations may differ from the first rate, and may be connected to the program/erase cycles of the unit, see Franklin paragraph [0098], In certain embodiments, the maintenance circuit 506 may selectively skip performance of one or more maintenance operations in response to one or more refresh commands. For example, the maintenance circuit 506 may refresh, wear level, and/or manage retirement for memory cells of the non-volatile memory medium 122 (e.g., one or more non-volatile memory elements 123) faster and/or in less time than is available during predefined refresh windows after refresh commands (e.g., since the refresh commands' period and/or a size of a refresh window may be selected based on one or more characteristics of volatile memory). To conserve power, during certain refresh periods of time after one or more refresh commands, the maintenance circuit 506 may selectively skip performance of a maintenance operation. For example, the maintenance circuit 506 may skip refresh cycles used for wear leveling swaps more often if a higher percentage of operations are reads instead of writes (e.g., reducing an urgency of wear leveling, or the like)).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Danielson, Monteleone and Zhu with those of Franklin. Franklin teaches using a different/distinct rate of performing wear leveling operations than the first rate as taught in Danielson., as well as the connection to the program/erase cycle count. The adjustment of the rate of wear leveling can be utilized to great effect to maximize the efficacy and results of the wear leveling operation. The usage rate among other various characteristics can be used to optimize the execution of the operation (Franklin paragraphs [0096-0097], As described below with regard to the wear leveling circuit 604 of FIG. 6, in certain embodiments, the maintenance circuit 506 performs a maintenance operation comprising a memory wear leveling operation. For example, the maintenance circuit 506 may perform a memory wear leveling operation reading data from a region of a non-volatile memory element 123 and writing at least a portion of the read data to a different region of a non-volatile memory element 123 (e.g., providing wear leveling between different regions of one or more non-volatile memory elements 123, such as a block, a page, a word line, a die, a die plane, a chip, and/or another region of memory). For example, the maintenance circuit 506 may perform a memory wear leveling operation or other maintenance operations such as a garbage collection or storage capacity recovery operation to move valid data to a different region of memory while recovering storage capacity of unused or invalid data, rewriting data to a different region of memory to prevent data loss, or the like during a predefined period of time after the interface circuit 502 receives a refresh command (e.g., periodically in response to a predefined temperature condition, a predefined time condition, a predefined read disturb condition, a predefined write disturb condition, or the like being satisfied prior to the interface circuit 502 receiving the refresh command, or the like). As described below with regard to the retirement circuit 606 of FIG. 6, in certain embodiments, the maintenance circuit 506 performs a maintenance operation comprising a replacement operation. For example, the maintenance circuit 506 may perform a replacement operation replacing and/or retiring a region of memory (e.g., failing and/or near failing memory cells, a region of memory satisfying an error threshold and/or another retirement threshold, or the like). The maintenance circuit 506 may logically remap spare or extra storage regions of a non-volatile memory element 123 to replace a different storage region of a non-volatile memory element 123, or the like).
Regarding claim 23, Danielson in view of Monteleone in further view of Zhu in further view of Franklin teaches The method of claim 21, wherein: performing the wear leveling at the memory system in accordance with the first rate comprises transferring, at a first rate that is less than or equal to the first rate, information from a respective blocks of memory cells associated with a lowest quantity of program/erase cycles to respective second blocks of memory cells; (Danielson paragraph [0022], The controller 115 can communicate with the memory devices 112A to 112N to perform operations such as reading data, writing data, or erasing data at the memory devices 112A to 112N and other such operations. The controller 115 can include hardware such as one or more integrated circuits and/or discrete components, a buffer memory, or a combination thereof. The controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor. The controller 115 can include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory system 110, including handling communications between the memory system 110 and the host system 120. In some embodiments, the local memory 119 can include memory registers storing memory pointers, fetched data, etc. The local memory 119 can also include read-only memory (ROM) for storing micro-code. While the example memory system 110 in FIG. 1 has been illustrated as including the controller 115, in another embodiment of the present disclosure, a memory system 110 may not include a controller 115, and may instead rely upon external control (e.g., provided by an external host, or by a processor or controller separate from the memory system). The lowest quantity of program/erase cycles may be classified as a read-only memory unit resulting in a read operation being performed to transfer the corresponding data) and performing the wear leveling at the memory system in accordance with the second rate comprises transferring, at a second rate that is less than or equal to the second rate, information from respective first blocks of memory cells associated with a lowest quantity of program/erase cycles to respective second blocks of memory cells (Franklin paragraph [0098], In certain embodiments, the maintenance circuit 506 may selectively skip performance of one or more maintenance operations in response to one or more refresh commands. For example, the maintenance circuit 506 may refresh, wear level, and/or manage retirement for memory cells of the non-volatile memory medium 122 (e.g., one or more non-volatile memory elements 123) faster and/or in less time than is available during predefined refresh windows after refresh commands (e.g., since the refresh commands' period and/or a size of a refresh window may be selected based on one or more characteristics of volatile memory). To conserve power, during certain refresh periods of time after one or more refresh commands, the maintenance circuit 506 may selectively skip performance of a maintenance operation. For example, the maintenance circuit 506 may skip refresh cycles used for wear leveling swaps more often if a higher percentage of operations are reads instead of writes (e.g., reducing an urgency of wear leveling, or the like). The first- and second-rate wear leveling operations may both be sent from the memory cells/units with the lowest quantity of program/erase cycles, see Franklin paragraph [0090], In certain embodiments, a predefined period of time during which a maintenance circuit 506 performs one or more maintenance operations may comprise up to a full refresh period or window (e.g., as defined for a volatile memory refresh, a volatile memory standard, or the like). In another embodiment, a predefined period of time during which a maintenance circuit 506 performs one or more maintenance operations (e.g., a maintenance period or window) may be defined as less than a full refresh period or window (e.g., to conserve power, to preserve a remaining battery life, because the one or more maintenance operations take less time than a full refresh period or window, or the like). In some embodiments, a maintenance circuit 506 may increase a duration of a maintenance period over time (e.g., based on a program/erase count or other age indicator for a non-volatile memory device 120, for a non-volatile memory element 123, for a region of a non-volatile memory element 123, or the like), to provide more maintenance over time as the non-volatile memory device 120 ages. In one embodiment, the read/write circuit 504 may perform read and/or write operations after a maintenance period even if a refresh period has not completed, if the maintenance period is defined to be shorter than the refresh period).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Danielson, Monteleone and Zhu with those of Franklin. Franklin teaches using a different/distinct rate of performing wear leveling operations than the first rate as taught in Danielson., as well as the connection to the program/erase cycle count. The memory cells are also designed to transfer data from the lowest program/erase cycle memory cells, which will help extend their lifespan (Franklin paragraphs [0096-0097], As described below with regard to the wear leveling circuit 604 of FIG. 6, in certain embodiments, the maintenance circuit 506 performs a maintenance operation comprising a memory wear leveling operation. For example, the maintenance circuit 506 may perform a memory wear leveling operation reading data from a region of a non-volatile memory element 123 and writing at least a portion of the read data to a different region of a non-volatile memory element 123 (e.g., providing wear leveling between different regions of one or more non-volatile memory elements 123, such as a block, a page, a word line, a die, a die plane, a chip, and/or another region of memory). For example, the maintenance circuit 506 may perform a memory wear leveling operation or other maintenance operations such as a garbage collection or storage capacity recovery operation to move valid data to a different region of memory while recovering storage capacity of unused or invalid data, rewriting data to a different region of memory to prevent data loss, or the like during a predefined period of time after the interface circuit 502 receives a refresh command (e.g., periodically in response to a predefined temperature condition, a predefined time condition, a predefined read disturb condition, a predefined write disturb condition, or the like being satisfied prior to the interface circuit 502 receiving the refresh command, or the like). As described below with regard to the retirement circuit 606 of FIG. 6, in certain embodiments, the maintenance circuit 506 performs a maintenance operation comprising a replacement operation. For example, the maintenance circuit 506 may perform a replacement operation replacing and/or retiring a region of memory (e.g., failing and/or near failing memory cells, a region of memory satisfying an error threshold and/or another retirement threshold, or the like). The maintenance circuit 506 may logically remap spare or extra storage regions of a non-volatile memory element 123 to replace a different storage region of a non-volatile memory element 123, or the like).
Regarding claim 24, Danielson in view of Monteleone in further view of Zhu in further view of Franklin teaches The method of claim 21, wherein determining that the wear characteristic of the memory system satisfies the threshold further comprises: determining to perform a transfer of information from a first block of memory cells associated with a first quantity of program/erase cycles to a second block of memory cells associated with a second quantity of program/erase cycles that is greater than the first quantity (Franklin paragraph [0103-0104], In one embodiment, the wear leveling circuit 604 is configured to perform a maintenance operation comprising a memory wear leveling operation. For example, the wear leveling circuit 604 may perform a memory wear leveling operation reading data from a region of a non-volatile memory element 123 and writing at least a portion of the read data to a different region of a non-volatile memory element 123 (e.g., providing wear leveling between different regions of one or more non-volatile memory elements 123, such as a block, a page, a word line, a die, a die plane, a chip, and/or another region of memory). For example, the wear leveling circuit 604 may perform a memory wear leveling operation such as a garbage collection or storage capacity recovery operation to move valid data to a different region of memory while recovering storage capacity of invalid data, rewriting data to a different region of memory to prevent data loss, or the like during a predefined period of time after the interface circuit 502 receives a refresh command (e.g., periodically in response to a predefined temperature condition, a predefined time condition, a predefined read disturb condition, a predefined write disturb condition, or the like being satisfied prior to the interface circuit 502 receiving the refresh command, or the like). In certain embodiments, when used in combination, the refresh circuit 602 may provide wear leveling within a region of a non-volatile memory medium 122 and the wear leveling circuit 604 may provide wear leveling between different regions of the non-volatile memory medium 122. The wear leveling circuit 604, in one embodiment, may copy and/or move data from a region of the non-volatile memory medium 122 that has been written less frequently than the refresh circuit 602 rotates or otherwise moves data within the region of the non-volatile memory medium 122, or the like. The data may be moved from a region with a lower program/erase cycle count to a higher one, through the use of wear leveling procedures).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Danielson, Monteleone and Zhu with those of Franklin. Franklin teaches using a different/distinct rate of performing wear leveling operations than the first rate as taught in Danielson., as well as the connection to the program/erase cycle count. The memory cells are also designed to transfer data from the lowest program/erase cycle memory cells, which will help extend their lifespan (Franklin paragraphs [0096-0097], As described below with regard to the wear leveling circuit 604 of FIG. 6, in certain embodiments, the maintenance circuit 506 performs a maintenance operation comprising a memory wear leveling operation. For example, the maintenance circuit 506 may perform a memory wear leveling operation reading data from a region of a non-volatile memory element 123 and writing at least a portion of the read data to a different region of a non-volatile memory element 123 (e.g., providing wear leveling between different regions of one or more non-volatile memory elements 123, such as a block, a page, a word line, a die, a die plane, a chip, and/or another region of memory). For example, the maintenance circuit 506 may perform a memory wear leveling operation or other maintenance operations such as a garbage collection or storage capacity recovery operation to move valid data to a different region of memory while recovering storage capacity of unused or invalid data, rewriting data to a different region of memory to prevent data loss, or the like during a predefined period of time after the interface circuit 502 receives a refresh command (e.g., periodically in response to a predefined temperature condition, a predefined time condition, a predefined read disturb condition, a predefined write disturb condition, or the like being satisfied prior to the interface circuit 502 receiving the refresh command, or the like). As described below with regard to the retirement circuit 606 of FIG. 6, in certain embodiments, the maintenance circuit 506 performs a maintenance operation comprising a replacement operation. For example, the maintenance circuit 506 may perform a replacement operation replacing and/or retiring a region of memory (e.g., failing and/or near failing memory cells, a region of memory satisfying an error threshold and/or another retirement threshold, or the like). The maintenance circuit 506 may logically remap spare or extra storage regions of a non-volatile memory element 123 to replace a different storage region of a non-volatile memory element 123, or the like).
Regarding claim 25, Danielson in view of Monteleone in further view of Zhu in further view of Franklin teaches The method of claim 21, further comprising: determining that the wear characteristic of the memory system satisfies a second threshold based at least in part on determining that a quantity of access operations between determining to perform a third wear leveling operation and determining to perform a fourth wear leveling operation satisfies a threshold quantity of access operations (Danielson paragraph [0013], Other characteristics of a memory device can be associated with the endurance of the memory device to store data. When data is written to and/or erased from a memory cell of a memory device, the memory cell can be damaged. As the number of write operations and/or erase operations performed on a memory cell increases, the probability that the data stored at the memory cell including an error increase as the memory cell is increasingly damaged. A characteristic associated with the endurance of the memory device is the number of write operations or a number of program/erase operations performed on a memory cell of the memory device. If a threshold number of write operations performed on the memory cell is exceeded, then data can no longer be reliably stored at the memory cell as the data can include a large number of errors that cannot be corrected. Different media types can also have difference endurances for storing data. For example, a first media type can have a threshold of 1,000,000 write operations, while a second media type can have a threshold of 2,000,000 write operations. Accordingly, the endurance of the first media type to store data is less than the endurance of the second media type to store data. The usage characteristic corresponding to access operations can be utilized for determining a plurality of wear leveling operations) performing the wear leveling at the memory system in accordance with a third rate, different than the second rate, (Franklin paragraphs [0096-0097], As described below with regard to the wear leveling circuit 604 of FIG. 6, in certain embodiments, the maintenance circuit 506 performs a maintenance operation comprising a memory wear leveling operation. For example, the maintenance circuit 506 may perform a memory wear leveling operation reading data from a region of a non-volatile memory element 123 and writing at least a portion of the read data to a different region of a non-volatile memory element 123 (e.g., providing wear leveling between different regions of one or more non-volatile memory elements 123, such as a block, a page, a word line, a die, a die plane, a chip, and/or another region of memory). For example, the maintenance circuit 506 may perform a memory wear leveling operation or other maintenance operations such as a garbage collection or storage capacity recovery operation to move valid data to a different region of memory while recovering storage capacity of unused or invalid data, rewriting data to a different region of memory to prevent data loss, or the like during a predefined period of time after the interface circuit 502 receives a refresh command (e.g., periodically in response to a predefined temperature condition, a predefined time condition, a predefined read disturb condition, a predefined write disturb condition, or the like being satisfied prior to the interface circuit 502 receiving the refresh command, or the like). As described below with regard to the retirement circuit 606 of FIG. 6, in certain embodiments, the maintenance circuit 506 performs a maintenance operation comprising a replacement operation. For example, the maintenance circuit 506 may perform a replacement operation replacing and/or retiring a region of memory (e.g., failing and/or near failing memory cells, a region of memory satisfying an error threshold and/or another retirement threshold, or the like). The maintenance circuit 506 may logically remap spare or extra storage regions of a non-volatile memory element 123 to replace a different storage region of a non-volatile memory element 123, or the like) based at least in part on determining that the wear characteristic satisfies the second threshold (Danielson paragraphs [0033-0034], At block 330, a determination is made as to whether a corresponding usage threshold of the first memory device or the second memory device has been exceeded. For purposes of the present disclosure, a usage threshold can be exceeded when a value is greater than or equal to the usage threshold. For example, if the first usage threshold for the first memory device is 1,000,000 total bytes written to a memory cell of the first memory device and a memory cell of the first memory device has had 1,000,000 total bytes written to the memory cell, then the first usage threshold has been exceeded. If a usage threshold for the first memory device and/or the second memory device has not been exceeded, then at block 340, subsequent data is stored at the first memory device or the second memory device. The subsequent data can be received from a host system for storage by the memory system. In one embodiment, if the usage thresholds for the memory devices have not been exceeded, the subsequent data can be stored at the first memory device or second memory device based on characteristics associated with the subsequent data. The storage density (i.e., the number of bits in a given allocation of memory storage) can be used to determine the write operation characteristics, as well as the rate of wear leveling operations being performed. Also see Danielson paragraphs [0015-0016], Generally, in order to obtain the different desired characteristics of memory devices, multiple conventional memory systems having different media types and associated characteristics can be used with a host system. For example, a host system can be coupled to a first conventional memory system having a first media type with a high data density, a second conventional memory system having a second media type with a high access speed, and a third conventional memory system having a third media type with a high endurance. However, using multiple memory systems to achieve the different desired characteristics for the storage of data is costly and inefficient as the host system would utilize additional connections to each of the different memory systems).
Regarding claim 26, Danielson in view of Monteleone in further view of Zhu in further view of Franklin teaches The method of claim 25, wherein the third rate is greater than the second rate (Danielson paragraph [0028], At block 230, a first usage threshold is determined for the first memory device based on the first set of characteristics received at block 220 and a second usage threshold is determined for the second memory device based on the second set of characteristics received at block 220. In embodiments, the first usage threshold can correspond to an endurance of the first memory device to store data and the second usage threshold corresponds to an endurance for the second memory device to store data. In one embodiment, the first usage threshold and the second usage threshold can correspond to the amount of data that can be written to a memory cell of a corresponding memory device before the memory cell can be considered unreliable to store data. For example, the first usage threshold can correspond to 1,000,000 total bytes that can be written to a memory cell of the first memory device and the second usage threshold can correspond to 1,500,000 total bytes that can be written to a memory cell of the second memory device. In some embodiments, the first usage threshold and the second usage threshold can correspond to a number of write operations that can be performed on a memory cell of a corresponding memory device before the memory cell can be considered unreliable to store data. For example, the first usage threshold can correspond to 500,000 write operations that can be performed on a memory cell of the first memory device and the second usage threshold can correspond to 1,000,000 write operations that can be performed on a memory cell of the second memory device. The determination for the second wear leveling operation may require a greater number of second write operations to be performed).
Regarding claim 27, Danielson in view of Monteleone in further view of Zhu in further view of Franklin teaches The method of claim 21, wherein determining that the wear characteristic of the memory system satisfies the threshold further comprises: determining to refrain from performing a transfer of information from a block of memory cells associated with a lowest quantity of program/erase cycles of the plurality of blocks of memory cells (Franklin paragraph [0122], A means for selectively skipping wear leveling in response to receiving one or more refresh commands and/or triggers, in various embodiments, may include a maintenance component 150, a maintenance circuit 506, a wear leveling circuit 604, a refresh circuit 602, a retirement circuit 606, a read/write circuit 504, a device controller 126, an on-die controller 220, a state machine 222, an integrated circuit device, an FPGA, an ASIC, other logic hardware, and/or other executable code stored on a computer readable storage medium. Other embodiments may include similar and/or equivalent means for selectively skipping wear leveling in response to receiving one or more refresh commands and/or triggers. The wear level operations can be chosen to be skipped in certain circumstances, wherein the transfer for the wear leveling procedure is done from lowest program/erase cycle count to a higher valued one (Franklin paragraph [0088], A refresh period and/or window, as used herein, comprises a predefined period of time. A refresh period, in certain embodiments, may be defined and/or measured relative to a refresh command, receipt of a refresh command, detection of a refresh command, or the like (e.g., a predefined period of time after the interface circuit 502 receives and/or detects a refresh command, or the like). A duration of a refresh period, in certain embodiments, is selected to provide enough time to refresh data of a predefined portion of a volatile memory (e.g., reading data from an active row of volatile memory, latching the data, and rewriting the data back to the active row of volatile memory). A duration of a refresh period may be defined and/or measured in time, in clock cycles, or the like. In one embodiment, a refresh period comprises a maximum amount of time during which the maintenance circuit 506 may perform one or more maintenance operations (e.g., and the maintenance circuit 506 may take less than a full refresh period to perform one or more maintenance operations, may selectively skip performing any maintenance operations during a commanded refresh period (e.g., on occasion determine to “no-op” and perform no operation), or the like)).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Danielson, Monteleone and Zhu with those of Franklin. Franklin teaches a means for a memory apparatus to skip a potential wear leveling operation. This can be performed in the event that a wear leveling operation is determined to be redundant, unnecessary, or an operation performing a similar function is already scheduled (Franklin paragraph [0037], By performing a maintenance operation or portion thereof in response to a refresh command, instead of, or in addition to, performing the maintenance operation in the background, in some embodiments, a maintenance component 150 may allow a non-volatile memory element 123 and/or a non-volatile memory device 120 to operate synchronously (e.g., responding to a storage request such as a read or write request with little or no delay from performing a background maintenance operation and/or otherwise communicating synchronously with a host 110, a processor 111, or the like). Synchronous operation of a non-volatile memory device 120 and/or a non-volatile memory element 123, as used herein, comprises a non-volatile memory device 120 and/or a non-volatile memory element 123 recognizing control inputs (e.g., commands, data, addresses, or the like) in response to an external clock input (e.g., over a memory bus 125 or the like). Also see Franklin paragraph [0041], However, for compatibility with the same host memory controller and/or refresh command, in certain embodiments, a maintenance component 150 may perform one or more maintenance operations or a portion thereof on non-volatile memory cells of a non-volatile memory medium 122 of one or more non-volatile memory elements 123 in response to a refresh command. For example, a maintenance component 150 may instead, or on occasion, use or repurpose some or all of the refresh commands to perform a different maintenance operation for a type of memory medium 122 that doesn't require a volatile memory refresh operation such as storage class memory or other non-volatile memory, and/or may perform a different type of maintenance operation for a memory medium 122 that does require a volatile memory refresh operation (e.g., in addition to a volatile memory refresh operation), or the like).
Regarding claim 29, Danielson in view of Monteleone in further view of Zhu in further view of Franklin teaches The method of claim 21, wherein the second rate is less than the first rate (Danielson paragraph [0028], At block 230, a first usage threshold is determined for the first memory device based on the first set of characteristics received at block 220 and a second usage threshold is determined for the second memory device based on the second set of characteristics received at block 220. In embodiments, the first usage threshold can correspond to an endurance of the first memory device to store data and the second usage threshold corresponds to an endurance for the second memory device to store data. In one embodiment, the first usage threshold and the second usage threshold can correspond to the amount of data that can be written to a memory cell of a corresponding memory device before the memory cell can be considered unreliable to store data. For example, the first usage threshold can correspond to 1,000,000 total bytes that can be written to a memory cell of the first memory device and the second usage threshold can correspond to 1,500,000 total bytes that can be written to a memory cell of the second memory device. In some embodiments, the first usage threshold and the second usage threshold can correspond to a number of write operations that can be performed on a memory cell of a corresponding memory device before the memory cell can be considered unreliable to store data. For example, the first usage threshold can correspond to 500,000 write operations that can be performed on a memory cell of the first memory device and the second usage threshold can correspond to 1,000,000 write operations that can be performed on a memory cell of the second memory device. The determination for the second wear leveling operation may require a greater number of second write operations to be performed).
Regarding claim 30, Danielson in view of Monteleone in further view of Zhu in further view of Franklin teaches The method of claim 21, wherein: performing the wear leveling at the memory system in accordance with the first rate is based at least in part on performing a first quantity of data migrations, between wear leveling operations, from memory cells of the memory system (Zhu paragraph [0014], Aspects of the present disclosure address the above and other deficiencies by having a memory sub-system that can perform or coordinate one or more wear leveling operations. Cold swapping of memory cells can include identifying memory cells for wear-leveling operations that are not being accessed as much as “hot” memory cells for hot swapping described above. For example, the memory sub-system can count the number of write operations (e.g., write counts) performed on memory cells in a mapped region of SMUs (e.g., a region of the SMUs to which memory cells are actively being written). The memory sub-system can compare a minimum number of write operations performed on all SMUs in the mapped region (e.g., the minimum write count) with a minimum number of write operations (e.g., the minimum write count) performed on memory cells in an unmapped region of SMUs (e.g., a region of the SMUs to which memory cells are not actively being written). The memory sub-system can identify the SMU with the minimum write count in the unmapped region. In some cases, when the minimum write count of the SMU in the mapped region is less than the minimum write count of the SMU in the unmapped region, the memory sub-system can swap data stored in the two SMUs. In such cases, the memory sub-system can write to the formerly unmapped SMU (e.g., swapped to the mapped region), and the memory sub-system can stop writing to the formerly mapped SMU (e.g., swapped to the unmapped region). Performing such an operation can more evenly spread the wear between mapped and unmapped SMUs throughout the memory device) that are associated with a first storage density to memory cells of the memory system that are associated with a second storage density; and performing the wear leveling at the memory system in accordance with the second rate is based at least in part on performing a second quantity of data migrations, between wear leveling operations, from the memory cells of the memory system that are associated with a first storage density to the memory cells of the memory system that are associated with a second storage density (Danielson paragraphs [0033-0034], At block 330, a determination is made as to whether a corresponding usage threshold of the first memory device or the second memory device has been exceeded. For purposes of the present disclosure, a usage threshold can be exceeded when a value is greater than or equal to the usage threshold. For example, if the first usage threshold for the first memory device is 1,000,000 total bytes written to a memory cell of the first memory device and a memory cell of the first memory device has had 1,000,000 total bytes written to the memory cell, then the first usage threshold has been exceeded. If a usage threshold for the first memory device and/or the second memory device has not been exceeded, then at block 340, subsequent data is stored at the first memory device or the second memory device. The subsequent data can be received from a host system for storage by the memory system. In one embodiment, if the usage thresholds for the memory devices have not been exceeded, the subsequent data can be stored at the first memory device or second memory device based on characteristics associated with the subsequent data. The storage density (i.e., the number of bits in a given allocation of memory storage) can be used to determine the write operation characteristics, as well as the rate of wear leveling operations being performed. Also see Danielson paragraphs [0015-0016], Generally, in order to obtain the different desired characteristics of memory devices, multiple conventional memory systems having different media types and associated characteristics can be used with a host system. For example, a host system can be coupled to a first conventional memory system having a first media type with a high data density, a second conventional memory system having a second media type with a high access speed, and a third conventional memory system having a third media type with a high endurance. However, using multiple memory systems to achieve the different desired characteristics for the storage of data is costly and inefficient as the host system would utilize additional connections to each of the different memory systems).
Response to Arguments
Applicant’s arguments, see pages 1-6 (numbered pages 11-16), filed December 23rd, 2025, with respect to the rejection(s) of claim(s) 1, 10-11 and 20 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Danielson et al. (US Publication No. 2019/0332317 -- "Danielson") in view of Monteleone et al. (US Publication No. 2019/0347012 – “Monteleone”) in further view of Kwon et al. (US Publication No. 2018/0113636 – “Kwon”).
The Kwon reference has been added to the 35 USC 103 Rejection of independent claims 1, 10-11 and 20. Kwon has been added to explicitly teach the concept of using different quantities of write operations on memory cells of a plurality of memory blocks in a memory system to determine performing wear leveling operations, in order to improve the reliability of the memory system, as described in further detail in the rejection above. In light of the newly added reference and rationale, the 35 U.S.C. 103 Rejection is maintained.
Applicant's arguments filed December 13th, 2025 with respect to Independent Claim 21 have been fully considered but they are not persuasive.
Applicant further argues:
“First, the Office Action has not shown how cold swapping data based on write counts-as described in Zhu-teaches or suggests "performing the wear leveling at the plurality of blocks of memory cells of the memory system in accordance with a second rate the second rate corresponding to a second quantity of access operations performed prior to performing the wear leveling operations, the second quantity different than the first quantity," as recited in amended independent claim 21. Indeed, Zhu's description of cold swapping data has not been shown to be relevant to adjusting a rate of wear leveling operations at a set of blocks. Second, the Office Action alleges that "the references cited, specifically the Zhu reference, explicitly disclose performing wear leveling based on write quantity operations, which can be set to be a threshold value, as well as categorized as "hot" or "cold" memory cells, referring to the rate at which write operations are performed." See Office Action p. 80 (citing Zhu 1 [0014]). The Office Action alleges that "[t]his leads to wear leveling being performed at different rates for the memory cells, depending on the quantity of write operations set, as well as the rate at which write operations are performed," stating that "[g]iven the above rationale and reasoning, the applicant's arguments regarding independent claim 21 are not considered to be persuasive and the 35 U.S.C. 103 Rejection is maintained." Id., pp. 80 and 81 (emphasis added). However, wear leveling operations are traditionally performed on "hot" and "cold" memory cells based on write cycles, not on relative quantities of wear leveling. Thus, it has not been shown that "hot" memory cells and "cold" memory cells are associated with different rates of wear leveling, corresponding to different quantities of access operations, as recited in amended independent claim 21.”
The examiner respectfully disagrees. The examiner asserts that the Zhu reference sufficiently teaches the above argued limitations, including the newly added limitation. The claim language recites a first and second rate of wear leveling being performed on the memory cells, with the applicant arguing that the rate of wear leveling is not connected to the “hot” and “cold” memory cells described in Zhu. However, the examiner notes that the Zhu reference explicitly teaches using write count thresholds as a means to initiate background operations, including wear leveling operations. This corresponds to a hot memory cell reaching a predetermined write count threshold faster, resulting in a higher rate of wear leveling. Similarly, a cold memory cell would reach the threshold count slower, resulting in a lower rate of wear leveling. In light of this interpretation, the applicant’s argument is not considered persuasive and the 35 USC 103 Rejection is maintained.
Conclusion
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/J.C.K./ Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/ Supervisory Patent Examiner, Art Unit 2133
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