DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Claims 1, 10-11, 17 and 20-21 have been amended. Claims 2, 12 and 28 remain cancelled. Claim 22 has been cancelled. Claims 1, 3-11, 13-21, 23-27 and 29-30 remain pending and are ready for examination.
Claim Objections
Claims 1, 10-11 and 20 objected to because of the following informalities: Claim 11, line 15 reads “performing the second quantity of write operations that satisfy the determined …”. The claim should read “... that satisfies the determined …” to bring the claim in line with the other uses of the term. Similar rationale applies to independent claims 1, 10 and 20.
Claims 23 objected to because of the following informalities: Claim 23, line 5 reads “transferring ... information from a respective blocks of memory cells …”. The claim should read “transferring … information from respective blocks of memory cells”, in line with the other claim limitations using this term.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 21, 23-27 and 29-30 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 21 is rejected due to lack of clarity regarding the threshold values introduced in the claim. The claim recites several different threshold values, including “a second threshold” which is introduced before any other threshold value (i.e., a first threshold). The claim also recites “determining that a wear characteristic … satisfies a threshold based at least in part on a quantity of access operations”. However, the same limitation recites “determining to refrain from performing a second wear leveling operation satisfying a threshold quantity of access operations”. This makes the claim unclear as to whether the threshold value here is referring to the previously introduced threshold value, or a unique threshold value. The claim further recites “performing … based at least in part on determining that the wear characteristic satisfies the threshold”. The examiner is unsure as to which threshold value this is referring to.
Following from independent claim 21, additional ambiguity is created regarding the interpretation of dependent claims 23-27 and 29-30. For example, claim 23 recites “performing … in accordance with the first rate, comprises transferring, at a first rate”. This reuse of the term makes it unclear if the first rate being described is the same first rate or a new rate, in which case the claim should be amended to recite that clearly. Further claim 23 also describes “information from respective first blocks of memory cells associated with a lowest quantity of program/erase cycles”. The concept of “lowest quantity of program/erase cycles” is now introduced in the amended independent claim, and it is unclear if these are the same lowest quantity. Similar issues are contained in the other dependent claims.
Appropriate clarification is required for a determination of allowability to be made on the claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-7, 10, 11-17 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Danielson et al. (US Publication No. 2019/0332317 -- "Danielson") in view of Onishi (US Publication No. 2022/0308766 – “Onishi”).
Regarding claim 1, Danielson teaches A method, comprising: performing a first wear leveling operation at a memory system based at least in part on performing a first quantity of write operations at a plurality of blocks of memory cells of the memory system (Danielson paragraph [0039], FIG. 4B illustrates an example of determining whether to store other data at a memory device based on the usage of the memory devices 450, in accordance with embodiments of the present disclosure. In the present illustration, the actual usage of a memory cell of memory device 420 is 94 write operations performed on a memory cell of memory device 420. Because the actual usage of the memory cell of memory device 420 is less than the usage threshold (e.g., 100 write operations) for memory device 420, data can be stored at the memory cell of the memory device 420. The actual usage of a memory cell of memory device 430, however, is 50 write operations performed on a memory cell of memory device 430. Because the actual usage of the memory cell (e.g., 50 write operations) exceeds the usage threshold (e.g., 50) for memory device 430, data is not stored at the memory cell of memory device 430. The process for a wear leveling operation (determining which memory blocks/cells are viable for storage and using them according to said determinations) can be based on various usage characteristics such as write operation quantity, as indicated here. For further details regarding the usage characteristic being used for wear leveling operations, see Danielson paragraphs [0022-0023], The controller 115 can include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory system 110, including handling communications between the memory system 110 and the host system 120. In some embodiments, the local memory 119 can include memory registers storing memory pointers, fetched data, etc. The local memory 119 can also include read-only memory (ROM) for storing micro-code. While the example memory system 110 in FIG. 1 has been illustrated as including the controller 115, in another embodiment of the present disclosure, a memory system 110 may not include a controller 115, and may instead rely upon external control (e.g., provided by an external host, or by a processor or controller separate from the memory system). In general, the controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 112A to 112N. The controller 115 can be responsible for other operations such as wear leveling operations) that satisfies a first threshold quantity of write operations; determining a second threshold quantity of write operations, less than the first threshold quantity of write operations (Danielson paragraph [0029], In embodiments, multiple usage thresholds can be assigned to a memory device of the memory system. The multiple usage thresholds can be based on the endurance of the memory device to store data. For example, a first memory device can have an associated endurance of 1,000,000 total bytes written to a memory cell of the first memory device, at which point the first memory device can no longer store data. In one embodiment, the multiple usage thresholds can be a portion, such as a percentage, of the endurance of the first memory device to store data or the endurance of the first memory device to store data. For example, the first memory device can have one usage threshold corresponding to 900,000 total bytes written to a memory cell of the first memory device and another usage threshold corresponding to 1,000,000 total bytes written to the memory cell of the first memory device. In embodiments, the first usage threshold and second usage threshold can be determined based on a received input from a host system. In other embodiments, the first usage threshold and the second usage threshold may be based on a portion, such as a percentage, of the endurance of the first memory device and the second memory device to reliably store data. For example, if a memory cell of a memory device can have 1,000,000 total bytes written to the memory cell before the memory cell can no longer reliably store data, then the usage threshold for the memory device can be 900,000 total bytes written (e.g., 90%) to a memory cell of the memory device. The memory system can utilize a plurality of different write quantity threshold values, where the write quantity threshold can be higher or lower based on various factors listed above) in response to performing the first wear leveling operation; (Danielson paragraph [0034], At block 350, if a usage threshold of the first memory device and/or the second memory device has been exceeded, the subsequent data is not stored at the memory device that corresponds to the exceeded usage threshold. For example, if it is determined that the usage threshold for the first memory device has not been exceeded and the usage threshold for the second memory device has been exceeded, then subsequent data is not stored at the second memory device (e.g., the memory device corresponding to the exceeded usage threshold). As previously described, in one embodiment, the usage thresholds can correspond to the endurance of memory devices to reliably store data. Accordingly, the usage threshold of a memory device being exceeded can indicate that the memory device can no longer store data reliably and, therefore, subsequent data should no longer be stored at the memory device. In one embodiment, if the usage threshold of the memory device is exceeded, the memory device can begin to operate in a read-only mode. While operating in a read-only mode, data stored at the memory device can continue to be read (e.g., provided to the host system), but subsequent data received from the host system is not stored at the memory device. As taught in Danielson above, the second quantity of write operations is determined by the results of the initial wear leveling operation) and determining to perform a second wear leveling operation at the memory system (Danielson paragraphs [0037-0038], FIG. 4A illustrates an example of determining whether to store data at a memory device based on the usage of the memory devices 400, in accordance with some embodiments of the present disclosure. Memory system 410 includes memory devices 420 and 430. In one embodiment, memory device 420 includes a first media type having a first endurance to store data and memory device 430 includes a second media type having a second endurance to store data. For illustrative purposes, memory device 420 has a usage threshold of 100 and memory device 430 has a usage threshold of 50. In one embodiment, the usage thresholds and actual usages can correspond to a number of bytes written to a memory cell of the memory device. In embodiments, the usage thresholds and actual usages can correspond to a number of write operations performed on a memory cell of the memory device. In the present illustration, the actual usage of a memory cell of memory device 420 is 82 write operations performed on a memory cell of memory device 420. Because the actual usage of the memory cell (e.g., 82 write operations) of memory device 420 is less than the usage threshold (e.g., 100 write operations) for memory device 420, data can be stored at memory device 420. The actual usage of a memory cell of memory device 430 is 37 write operations performed on a memory cell of memory device 430. Because the actual usage of the memory cell (e.g., 37 write operations) is less than the usage threshold (e.g., 50 write operations) for memory device 430, data can be stored at memory device 430. The wear leveling operation will determine the quantity of write operations that can be performed on a corresponding memory unit, as well as the determination of whether that usage characteristic (i.e., second quantity of write operations) exceeds a threshold resulting in a necessary wear leveling operation).
Danielson does not teach performing, after performing the first wear leveling operation, a second quantity of write operations, that satisfies the determined second threshold quantity of write operations, at the plurality of blocks of memory cells; determining whether to perform a second wear leveling operation at the memory system based at least in part on performing the second quantity of write operations that satisfy the determined second threshold quantity of write operations.
However, Onishi teaches performing, after performing the first wear leveling operation, a second quantity of write operations, that satisfies the determined second threshold quantity of write operations at the memory system; (Onishi paragraph [0046], For example, the first threshold and the second threshold are the thresholds on the number of the write operations. The first and second threshold are provided to be used by the wear leveling control circuit 23 to determine whether to perform the next (subsequent) wear leveling on a certain unit size for the semiconductor storage device 1. The second quantity of write operations may be performed subsequent to a first wear leveling operation, also see Onishi paragraph [0070], Next, in Step 43 (S43), the control circuit 22 or the wear leveling control circuit 23 calculates a difference. The control circuit 22 or the wear leveling control circuit 23 receives the updated number of the write operations (the updated count value) on the predetermined page PAG of the memory cell array 11B from the counter circuit 25. In addition, the control circuit 22 or the wear leveling control circuit 23 receives a wear leveling cycle, the first threshold, and the second threshold, which are stored in the setting information table 34 of the memory 32. The control circuit 22 or the wear leveling control circuit 23 calculates the difference using the updated number of the write operations and the wear leveling cycle. In the following description, as an example, the wear leveling cycle is 1,001 times, the first threshold is 900 times, and the second threshold is 1,000 times. As described above, the difference is the remainder when the count value after updating the number of the write operations is divided by the wear leveling cycle. A first and second quantity/number of write operations may be performed, also see Fig. 4; Ref #34, for the plurality of write count thresholds)) determining to perform a second wear leveling operation at the memory system based at least in part on performing the second quantity of write operations that satisfy the determined second threshold quantity of write operations (Onishi paragraph [0127], As an example, a throughput transition during the sequential write operation of the memory system 3 according to the first embodiment, the sequential write operation is repeatedly performed on all pages of the semiconductor storage device 1. Conditions under which the memory system 3 performs the wear leveling on a particular page are as follows: (1) the number of the write operations (the count value) on the page after the previous wear leveling is performed is 901 or more and 1,000 or less (that is, the first threshold has been set to 900, and the second threshold is set to 1,000), and (2) the wear leveling is performed for individual pages of the 99 host write pages. In the first embodiment, only the data write operations associated with a host write request from the host device 4 and the write operations associated with wear leveling are considered, and the data read operations associated with a host read request from the host device 4 and the data read operations associated with a refresh operation are not considered. The subsequent (i.e., second) wear leveling operation may be performed in the event that the second quantity of write operations reaches the second threshold value).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Danielson with those of Onishi. Onishi teaches using a dynamic form of wear leveling where multiple wear leveling operations can be performed based on various determined write quantity thresholds, which can result in more efficient and reliable wear leveling operations (i.e., see Onishi paragraph [0060], On the other hand, in the memory system 3 according to the first embodiment, the wear leveling control circuit 23 determines whether to perform the wear leveling on a certain unit of each semiconductor storage device 1 using two thresholds, and is thus likely to perform the wear leveling on the semiconductor storage devices 1A and 1B at different times. As a result, the wear leveling control circuit 23 can spread the timing for performing the wear leveling between the two thresholds for each unit of the semiconductor storage devices 1A and 1B. Therefore, the memory system 3 according to the first embodiment can reduce a possibility that the timing to perform the write operation on each unit of the semiconductor storage device 1 associated with the wear leveling may be concentrated at a particular period of time, and can thus prevent performance deterioration of the memory system).
Claim 10 is the corresponding apparatus claim to method claim 1. It is rejected with the same references and rationale.
Regarding claim 3, Danielson in view of Onishi teaches The method of claim 1, further comprising: determining whether to perform the first wear leveling operation in accordance with a first rate of evaluation that is associated with the first quantity of write operations, wherein performing the first wear leveling operation is based at least in part on determining to perform the first wear leveling operation; (Danielson paragraph [0018], However, as previously discussed, memory devices having different media types can have different endurances and different respective threshold for storing data at the memory devices. The data can be stored at the memory devices based on the determined usage thresholds. For example, if a first memory device of the memory system is at or near a first usage threshold that indicates that the first memory device is at or near a point where the first memory device can no longer reliably store data, then data can be stored at another memory device of the memory system. By providing data to the different memory devices of the memory system based on different determined usage thresholds, the wear (e.g., number of operations performed on a memory device and/or an amount of data written to the memory device) on the multiple memory devices of the memory system can be more evenly distributed, preventing the premature failure of a particular memory device of a memory system relative to the other memory devices of the memory system. The process of a wear leveling operation is directly tied to the quantity of the write operations performed) and determining whether to perform the second wear leveling operation in accordance with a second rate of evaluation, greater than the first rate of evaluation, that associated with the second quantity of write operations (Danielson paragraph [0028], At block 230, a first usage threshold is determined for the first memory device based on the first set of characteristics received at block 220 and a second usage threshold is determined for the second memory device based on the second set of characteristics received at block 220. In embodiments, the first usage threshold can correspond to an endurance of the first memory device to store data and the second usage threshold corresponds to an endurance for the second memory device to store data. In one embodiment, the first usage threshold and the second usage threshold can correspond to the amount of data that can be written to a memory cell of a corresponding memory device before the memory cell can be considered unreliable to store data. For example, the first usage threshold can correspond to 1,000,000 total bytes that can be written to a memory cell of the first memory device and the second usage threshold can correspond to 1,500,000 total bytes that can be written to a memory cell of the second memory device. In some embodiments, the first usage threshold and the second usage threshold can correspond to a number of write operations that can be performed on a memory cell of a corresponding memory device before the memory cell can be considered unreliable to store data. For example, the first usage threshold can correspond to 500,000 write operations that can be performed on a memory cell of the first memory device and the second usage threshold can correspond to 1,000,000 write operations that can be performed on a memory cell of the second memory device. The determination for the second wear leveling operation may require a greater number of second write operations to be performed).
Regarding claim 4, Danielson in view of Onishi teaches The method of claim 1, further comprising: receiving a first set of one or more commands from a host system; performing the first quantity of write operations based at least in part on the first set of one or more commands from the host system; and receiving a second set of one or more commands from the host system, wherein performing the second quantity of write operations is based at least in part on the second set of one or more commands from the host system (Danielson paragraph [0023], In general, the controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 112A to 112N. The controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical block address and a physical block address that are associated with the memory devices 112A to 112N. The controller 115 can further include host interface circuitry to communicate with the host system 120 via the physical host interface. The host interface circuitry can convert the commands received from the host system into command instructions to access the memory devices 112A to 112N as well as convert responses associated with the memory devices 112A to 112N into information for the host system 120. A plurality of first and second write operations may be received from the host by the memory device/controller and subsequently performed/executed).
Regarding claim 5, Danielson in view of Onishi teaches The method of claim 1, wherein write operations of the first quantity of write operations and write operations of the second quantity of write operations are associated with migrating data from memory cells of the memory system that are associated with a first storage density to memory cells of the memory system that are associated with a second storage density (Danielson paragraphs [0033-0034], At block 330, a determination is made as to whether a corresponding usage threshold of the first memory device or the second memory device has been exceeded. For purposes of the present disclosure, a usage threshold can be exceeded when a value is greater than or equal to the usage threshold. For example, if the first usage threshold for the first memory device is 1,000,000 total bytes written to a memory cell of the first memory device and a memory cell of the first memory device has had 1,000,000 total bytes written to the memory cell, then the first usage threshold has been exceeded. If a usage threshold for the first memory device and/or the second memory device has not been exceeded, then at block 340, subsequent data is stored at the first memory device or the second memory device. The subsequent data can be received from a host system for storage by the memory system. In one embodiment, if the usage thresholds for the memory devices have not been exceeded, the subsequent data can be stored at the first memory device or second memory device based on characteristics associated with the subsequent data. The storage density (i.e., the number of bits in a given allocation of memory storage) can be used to determine the write operation characteristics. Also see Danielson paragraphs [0015-0016], Generally, in order to obtain the different desired characteristics of memory devices, multiple conventional memory systems having different media types and associated characteristics can be used with a host system. For example, a host system can be coupled to a first conventional memory system having a first media type with a high data density, a second conventional memory system having a second media type with a high access speed, and a third conventional memory system having a third media type with a high endurance. However, using multiple memory systems to achieve the different desired characteristics for the storage of data is costly and inefficient as the host system would utilize additional connections to each of the different memory systems).
Regarding claim 6, Danielson in view of Onishi teaches The method of claim 1, further comprising: determining that a lowest quantity of program/erase cycles associated with a plurality of blocks of memory cells of the memory system satisfies a threshold, wherein performing the first wear leveling operation at the memory system is based at least in part on determining that the lowest quantity of program/erase cycles satisfies the threshold (Danielson paragraph [0013], Other characteristics of a memory device can be associated with the endurance of the memory device to store data. When data is written to and/or erased from a memory cell of a memory device, the memory cell can be damaged. As the number of write operations and/or erase operations performed on a memory cell increases, the probability that the data stored at the memory cell including an error increase as the memory cell is increasingly damaged. A characteristic associated with the endurance of the memory device is the number of write operations or a number of program/erase operations performed on a memory cell of the memory device. If a threshold number of write operations performed on the memory cell is exceeded, then data can no longer be reliably stored at the memory cell as the data can include a large number of errors that cannot be corrected. Different media types can also have difference endurances for storing data. For example, a first media type can have a threshold of 1,000,000 write operations, while a second media type can have a threshold of 2,000,000 write operations. Accordingly, the endurance of the first media type to store data is less than the endurance of the second media type to store data. Program/erase cycle data can be utilized to determine the appropriate wear leveling operations when compared to a threshold value).
Regarding claim 7, Danielson in view of Onishi teaches The method of claim 1, wherein performing the first wear leveling operation comprises: reading information from a first block of memory cells associated with a lowest quantity of program/erase cycles; and writing the information to a second block of memory cells different than the first block of memory cells (Danielson paragraph [0022], The controller 115 can communicate with the memory devices 112A to 112N to perform operations such as reading data, writing data, or erasing data at the memory devices 112A to 112N and other such operations. The controller 115 can include hardware such as one or more integrated circuits and/or discrete components, a buffer memory, or a combination thereof. The controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor. The controller 115 can include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory system 110, including handling communications between the memory system 110 and the host system 120. In some embodiments, the local memory 119 can include memory registers storing memory pointers, fetched data, etc. The local memory 119 can also include read-only memory (ROM) for storing micro-code. While the example memory system 110 in FIG. 1 has been illustrated as including the controller 115, in another embodiment of the present disclosure, a memory system 110 may not include a controller 115, and may instead rely upon external control (e.g., provided by an external host, or by a processor or controller separate from the memory system). The lowest quantity of program/erase cycles may be classified as a read-only memory unit resulting in a read operation being performed to transfer the corresponding data).
Regarding claim 11, Danielson teaches A method, comprising: performing a first quantity of write operations at a plurality of blocks of memory cells of a memory system; (see Danielson paragraph [0012] for memory system comprising blocks of memory cells) that satisfies a first threshold quantity of write operations; (Danielson paragraph [0029], In embodiments, multiple usage thresholds can be assigned to a memory device of the memory system. The multiple usage thresholds can be based on the endurance of the memory device to store data. For example, a first memory device can have an associated endurance of 1,000,000 total bytes written to a memory cell of the first memory device, at which point the first memory device can no longer store data. In one embodiment, the multiple usage thresholds can be a portion, such as a percentage, of the endurance of the first memory device to store data or the endurance of the first memory device to store data. For example, the first memory device can have one usage threshold corresponding to 900,000 total bytes written to a memory cell of the first memory device and another usage threshold corresponding to 1,000,000 total bytes written to the memory cell of the first memory device. In embodiments, the first usage threshold and second usage threshold can be determined based on a received input from a host system. In other embodiments, the first usage threshold and the second usage threshold may be based on a portion, such as a percentage, of the endurance of the first memory device and the second memory device to reliably store data. For example, if a memory cell of a memory device can have 1,000,000 total bytes written to the memory cell before the memory cell can no longer reliably store data, then the usage threshold for the memory device can be 900,000 total bytes written (e.g., 90%) to a memory cell of the memory device. The memory system can utilize a plurality of different write quantity threshold values, where the write quantity threshold can be higher or lower based on various factors listed above) performing the second quantity of write operations at the plurality of blocks of memory cells greater than the first quantity, after performing the first quantity of write operations; (Danielson paragraph [0039], FIG. 4B illustrates an example of determining whether to store other data at a memory device based on the usage of the memory devices 450, in accordance with embodiments of the present disclosure. In the present illustration, the actual usage of a memory cell of memory device 420 is 94 write operations performed on a memory cell of memory device 420. Because the actual usage of the memory cell of memory device 420 is less than the usage threshold (e.g., 100 write operations) for memory device 420, data can be stored at the memory cell of the memory device 420. The actual usage of a memory cell of memory device 430, however, is 50 write operations performed on a memory cell of memory device 430. Because the actual usage of the memory cell (e.g., 50 write operations) exceeds the usage threshold (e.g., 50) for memory device 430, data is not stored at the memory cell of memory device 430. The process for a wear leveling operation (determining which memory blocks/cells are viable for storage and using them according to said determinations) can be based on various usage characteristics such as write operation quantity, as indicated here. For further details regarding the usage characteristics being used for wear leveling operations, see Danielson paragraphs [0022-0023], The controller 115 can include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory system 110, including handling communications between the memory system 110 and the host system 120. In some embodiments, the local memory 119 can include memory registers storing memory pointers, fetched data, etc. The local memory 119 can also include read-only memory (ROM) for storing micro-code. While the example memory system 110 in FIG. 1 has been illustrated as including the controller 115, in another embodiment of the present disclosure, a memory system 110 may not include a controller 115, and may instead rely upon external control (e.g., provided by an external host, or by a processor or controller separate from the memory system). In general, the controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 112A to 112N. The controller 115 can be responsible for other operations such as wear leveling operations).
Danielson does not teach determining to refrain from performing a first wear leveling operation at the memory system based at least in part on performing the first quantity of write operations at the memory system; determining a second threshold quantity of write operations, greater than the first threshold quantity of write operations, after determining to refrain from performing the first wear leveling operation; perform a second quantity of write operations, that satisfies the determined second threshold quantity of write operations at the plurality of blocks of memory cells after performing the first quantity of write operations; and determining whether to perform a second wear leveling operation at the memory system based at least in part on determining to refrain from performing the first wear leveling operation and performing the second quantity of write operations that satisfy the determined second threshold quantity of write operations.
However, Onishi teaches determining to refrain from performing a first wear leveling operation at the memory system based at least in part on performing the first quantity of write operations at the memory system; (Onishi paragraphs [0045-0046], In the first embodiment, the condition or restriction set in advance for determining whether to perform the wear leveling is a threshold value for the total number of write operations. In the first embodiment, the setting information includes a cycle on which the wear leveling is to be performed (a wear leveling cycle), a first threshold, and a second threshold that is greater than the first threshold. For example, the first threshold and the second threshold are the thresholds on the number of the write operations. The first and second threshold are provided to be used by the wear leveling control circuit 23 to determine whether to perform the next (subsequent) wear leveling on a certain unit size for the semiconductor storage device 1. The wear leveling may be performed or refrained from performed based on how a current write quantity compared to a threshold value) determining a second threshold quantity of write operations, greater than the first threshold quantity of write operations, after determining to refrain from performing the first wear leveling operation; (Onishi paragraph [0127], As an example, a throughput transition during the sequential write operation of the memory system 3 according to the first embodiment, the sequential write operation is repeatedly performed on all pages of the semiconductor storage device 1. Conditions under which the memory system 3 performs the wear leveling on a particular page are as follows: (1) the number of the write operations (the count value) on the page after the previous wear leveling is performed is 901 or more and 1,000 or less (that is, the first threshold has been set to 900, and the second threshold is set to 1,000), and (2) the wear leveling is performed for individual pages of the 99 host write pages. In the first embodiment, only the data write operations associated with a host write request from the host device 4 and the write operations associated with wear leveling are considered, and the data read operations associated with a host read request from the host device 4 and the data read operations associated with a refresh operation are not considered. The second threshold of write quantities may be determined in response to refraining from performing a first wear leveling, based on a determined write count quantity) perform a second quantity of write operations, that satisfies the determined second threshold quantity of write operations at the plurality of blocks of memory cells after performing the first quantity of write operations; (Onishi paragraph [0046], For example, the first threshold and the second threshold are the thresholds on the number of the write operations. The first and second threshold are provided to be used by the wear leveling control circuit 23 to determine whether to perform the next (subsequent) wear leveling on a certain unit size for the semiconductor storage device 1. The second quantity of write operations may be performed subsequent to a first wear leveling operation, also see Onishi paragraph [0070], Next, in Step 43 (S43), the control circuit 22 or the wear leveling control circuit 23 calculates a difference. The control circuit 22 or the wear leveling control circuit 23 receives the updated number of the write operations (the updated count value) on the predetermined page PAG of the memory cell array 11B from the counter circuit 25. In addition, the control circuit 22 or the wear leveling control circuit 23 receives a wear leveling cycle, the first threshold, and the second threshold, which are stored in the setting information table 34 of the memory 32. The control circuit 22 or the wear leveling control circuit 23 calculates the difference using the updated number of the write operations and the wear leveling cycle. In the following description, as an example, the wear leveling cycle is 1,001 times, the first threshold is 900 times, and the second threshold is 1,000 times. As described above, the difference is the remainder when the count value after updating the number of the write operations is divided by the wear leveling cycle. A first and second quantity/number of write operations may be performed, also see Fig. 4; Ref #34, for the plurality of write count thresholds)) and determining whether to perform a second wear leveling operation at the memory system based at least in part on determining to refrain from performing the first wear leveling operation and performing the second quantity of write operations that satisfy the determined second threshold quantity of write operations (Onishi paragraph [0152], With reference to FIG. 14, an example of the throughput transition during the sequential write operation of the memory system 3 according to the third embodiment will be described. In the memory system 3 according to the third embodiment, the wear leveling are performed on a particular page when the following conditions are met: (1) the number of the write operations (count value) on the page after the previous wear leveling is performed is 901 or more and 1,000 times or less (that is, the first threshold is 900, and the second threshold is 1,000), and (2) performing the wear leveling for each write request from the host device 4 with a wear leveling performance probability of 4%. In the description of the example of the throughput transition of the sequential write operation of the memory system 3 according to the third embodiment, points different from those in the example of the throughput transition of the sequential write operation of the memory system 3 according to the first embodiment will mainly be described. The second wear leveling may be performed in response to a second quantity of write operations exceeding a second write count quantity).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Danielson with those of Onishi. Onishi teaches using a dynamic form of wear leveling where multiple wear leveling operations can be performed based on various determined write quantity thresholds, which can result in more efficient and reliable wear leveling operations (i.e., see Onishi paragraph [0060], On the other hand, in the memory system 3 according to the first embodiment, the wear leveling control circuit 23 determines whether to perform the wear leveling on a certain unit of each semiconductor storage device 1 using two thresholds, and is thus likely to perform the wear leveling on the semiconductor storage devices 1A and 1B at different times. As a result, the wear leveling control circuit 23 can spread the timing for performing the wear leveling between the two thresholds for each unit of the semiconductor storage devices 1A and 1B. Therefore, the memory system 3 according to the first embodiment can reduce a possibility that the timing to perform the write operation on each unit of the semiconductor storage device 1 associated with the wear leveling may be concentrated at a particular period of time, and can thus prevent performance deterioration of the memory system).
Claim 20 is the corresponding apparatus claim to method claim 11. It is rejected with the same references and rationale.
Regarding claim 13, Danielson in view of Onishi teaches The method of claim 11, further comprising: determining whether to perform the first wear leveling operation in accordance with a first rate of evaluation that is associated with the first quantity of write operations, wherein determining to refrain from performing the first wear leveling operation is based at least in part on the determining whether to perform the first wear leveling operation; (Danielson paragraph [0039], FIG. 4B illustrates an example of determining whether to store other data at a memory device based on the usage of the memory devices 450, in accordance with embodiments of the present disclosure. In the present illustration, the actual usage of a memory cell of memory device 420 is 94 write operations performed on a memory cell of memory device 420. Because the actual usage of the memory cell of memory device 420 is less than the usage threshold (e.g., 100 write operations) for memory device 420, data can be stored at the memory cell of the memory device 420. The actual usage of a memory cell of memory device 430, however, is 50 write operations performed on a memory cell of memory device 430. Because the actual usage of the memory cell (e.g., 50 write operations) exceeds the usage threshold (e.g., 50) for memory device 430, data is not stored at the memory cell of memory device 430. The process for a wear leveling operation (determining which memory blocks/cells are viable for storage and using them according to said determinations) can be based on various usage characteristics such as write operation quantity, as indicated here. For further details regarding the usage characteristic being used for wear leveling operations, see Danielson paragraphs [0022-0023], The controller 115 can include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory system 110, including handling communications between the memory system 110 and the host system 120. In some embodiments, the local memory 119 can include memory registers storing memory pointers, fetched data, etc. The local memory 119 can also include read-only memory (ROM) for storing micro-code. While the example memory system 110 in FIG. 1 has been illustrated as including the controller 115, in another embodiment of the present disclosure, a memory system 110 may not include a controller 115, and may instead rely upon external control (e.g., provided by an external host, or by a processor or controller separate from the memory system). In general, the controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 112A to 112N. The controller 115 can be responsible for other operations such as wear leveling operations) and determining whether to perform the second wear leveling operation in accordance with a second rate of evaluation, less than the first rate of evaluation, that is associated with the second quantity of write operations (Danielson paragraph [0029], In embodiments, multiple usage thresholds can be assigned to a memory device of the memory system. The multiple usage thresholds can be based on the endurance of the memory device to store data. For example, a first memory device can have an associated endurance of 1,000,000 total bytes written to a memory cell of the first memory device, at which point the first memory device can no longer store data. In one embodiment, the multiple usage thresholds can be a portion, such as a percentage, of the endurance of the first memory device to store data or the endurance of the first memory device to store data. For example, the first memory device can have one usage threshold corresponding to 900,000 total bytes written to a memory cell of the first memory device and another usage threshold corresponding to 1,000,000 total bytes written to the memory cell of the first memory device. In embodiments, the first usage threshold and second usage threshold can be determined based on a received input from a host system. In other embodiments, the first usage threshold and the second usage threshold may be based on a portion, such as a percentage, of the endurance of the first memory device and the second memory device to reliably store data. For example, if a memory cell of a memory device can have 1,000,000 total bytes written to the memory cell before the memory cell can no longer reliably store data, then the usage threshold for the memory device can be 900,000 total bytes written (e.g., 90%) to a memory cell of the memory device. The amount of write operations that can be performed is largely based on the memory device/memory units themselves, but can be adjusted based on the thresholds set, resulting in either a larger or lesser first quantity).
Regarding claim 14, Danielson in view of Onishi teaches The method of claim 11, further comprising: receiving a first set of one or more commands from a host system, wherein performing the first quantity of write operations is based at least in part on the first set of one or more commands from the host system; and receiving a second set of one or more commands from the host system, wherein performing the second quantity of write operations is based at least in part on the second set of one or more commands from the host system (Danielson paragraph [0023], In general, the controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 112A to 112N. The controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical block address and a physical block address that are associated with the memory devices 112A to 112N. The controller 115 can further include host interface circuitry to communicate with the host system 120 via the physical host interface. The host interface circuitry can convert the commands received from the host system into command instructions to access the memory devices 112A to 112N as well as convert responses associated with the memory devices 112A to 112N into information for the host system 120. A plurality of first and second write operations may be received from the host by the memory device/controller and subsequently performed/executed).
Regarding claim 15, Danielson in view of Onishi teaches The method of claim 11, wherein write operations of the first quantity of write operations and of the second quantity of write operations are associated with migrating data from memory cells of the memory system that are associated with a first storage density to memory cells of the memory system that are associated with a second storage density (Danielson paragraphs [0033-0034], At block 330, a determination is made as to whether a corresponding usage threshold of the first memory device or the second memory device has been exceeded. For purposes of the present disclosure, a usage threshold can be exceeded when a value is greater than or equal to the usage threshold. For example, if the first usage threshold for the first memory device is 1,000,000 total bytes written to a memory cell of the first memory device and a memory cell of the first memory device has had 1,000,000 total bytes written to the memory cell, then the first usage threshold has been exceeded. If a usage threshold for the first memory device and/or the second memory device has not been exceeded, then at block 340, subsequent data is stored at the first memory device or the second memory device. The subsequent data can be received from a host system for storage by the memory system. In one embodiment, if the usage thresholds for the memory devices have not been exceeded, the subsequent data can be stored at the first memory device or second memory device based on characteristics associated with the subsequent data. The storage density (i.e., the number of bits in a given allocation of memory storage) can be used to determine the write operation characteristics. Also see Danielson paragraphs [0015-0016], Generally, in order to obtain the different desired characteristics of memory devices, multiple conventional memory systems having different media types and associated characteristics can be used with a host system. For example, a host system can be coupled to a first conventional memory system having a first media type with a high data density, a second conventional memory system having a second media type with a high access speed, and a third conventional memory system having a third media type with a high endurance. However, using multiple memory systems to achieve the different desired characteristics for the storage of data is costly and inefficient as the host system would utilize additional connections to each of the different memory systems).
Regarding claim 16, Danielson in view of Onishi teaches The method of claim 11, further comprising: determining that a lowest quantity of program/erase cycles associated with a plurality of blocks of memory cells of the memory system satisfies a threshold, wherein determining to perform the first wear leveling operation at a memory system is based at least in part on determining that the lowest quantity of program/erase cycles satisfies the threshold (Danielson paragraph [0013], Other characteristics of a memory device can be associated with the endurance of the memory device to store data. When data is written to and/or erased from a memory cell of a memory device, the memory cell can be damaged. As the number of write operations and/or erase operations performed on a memory cell increases, the probability that the data stored at the memory cell including an error increase as the memory cell is increasingly damaged. A characteristic associated with the endurance of the memory device is the number of write operations or a number of program/erase operations performed on a memory cell of the memory device. If a threshold number of write operations performed on the memory cell is exceeded, then data can no longer be reliably stored at the memory cell as the data can include a large number of errors that cannot be corrected. Different media types can also have difference endurances for storing data. For example, a first media type can have a threshold of 1,000,000 write operations, while a second media type can have a threshold of 2,000,000 write operations. Accordingly, the endurance of the first media type to store data is less than the endurance of the second media type to store data. Program/erase cycle data can be utilized to determine the appropriate wear leveling operations when compared to a threshold value).
Regarding claim 17, Danielson in view of Onishi teaches The method of claim 11, wherein performing the first wear leveling operation comprises: reading information from a first block of memory cells associated with a lowest quantity of program/erase cycles; and writing the information to a second block of memory cells different than the first block of memory cells (Danielson paragraph [0022], The controller 115 can communicate with the memory devices 112A to 112N to perform operations such as reading data, writing data, or erasing data at the memory devices 112A to 112N and other such operations. The controller 115 can include hardware such as one or more integrated circuits and/or discrete components, a buffer memory, or a combination thereof. The controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor. The controller 115 can include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory system 110, including handling communications between the memory system 110 and the host system 120. In some embodiments, the local memory 119 can include memory registers storing memory pointers, fetched data, etc. The local memory 119 can also include read-only memory (ROM) for storing micro-code. While the example memory system 110 in FIG. 1 has been illustrated as including the controller 115, in another embodiment of the present disclosure, a memory system 110 may not include a controller 115, and may instead rely upon external control (e.g., provided by an external host, or by a processor or controller separate from the memory system). The lowest quantity of program/erase cycles may be classified as a read-only memory unit resulting in a read operation being performed to transfer the corresponding data).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Danielson in view of Onishi as applied to claim 1 above, and further in view of Tai et al. (US Publication No. 2020/0065007 -- "Tai").
Regarding claim 8, Danielson in view of Onishi further in view of Tai teaches The method of claim 1, further comprising: performing the second wear leveling operation at the memory system based at least in part on determining to perform the second wear leveling operation; (Danielson paragraphs [0037-0038], FIG. 4A illustrates an example of determining whether to store data at a memory device based on the usage of the memory devices 400, in accordance with some embodiments of the present disclosure. Memory system 410 includes memory devices 420 and 430. In one embodiment, memory device 420 includes a first media type having a first endurance to store data and memory device 430 includes a second media type having a second endurance to store data. For illustrative purposes, memory device 420 has a usage threshold of 100 and memory device 430 has a usage threshold of 50. In one embodiment, the usage thresholds and actual usages can correspond to a number of bytes written to a memory cell of the memory device. In embodiments, the usage thresholds and actual usages can correspond to a number of write operations performed on a memory cell of the memory device. In the present illustration, the actual usage of a memory cell of memory device 420 is 82 write operations performed on a memory cell of memory device 420. Because the actual usage of the memory cell (e.g., 82 write operations) of memory device 420 is less than the usage threshold (e.g., 100 write operations) for memory device 420, data can be stored at memory device 420. The actual usage of a memory cell of memory device 430 is 37 write operations performed on a memory cell of memory device 430. Because the actual usage of the memory cell (e.g., 37 write operations) is less than the usage threshold (e.g., 50 write operations) for memory device 430, data can be stored at memory device 430. The wear leveling operation will determine the quantity of write operations that can be performed on a corresponding memory unit, as well as the determination of whether that usage characteristic (i.e., second quantity of write operations) exceeds a threshold resulting in a necessary wear leveling operation) determining a third quantity of write operations at the memory system, less than the second quantity of write operations, based at least in part on determining to perform the second wear leveling operation; and determining whether to perform a third wear leveling operation at the memory system based at least in part on performing the third quantity of write operations at the memory system (Tai paragraph [0015], Aspects of the disclosure address the above and other deficiencies by implementing multi-level wear leveling for non-volatile memory. In one implementation, multi-level wear leveling utilizes a hierarchy of levels of data units having different sizes. For example, a first level can represent individual data units, such as a data block or page of a memory component (which can also be referred to herein as a “management unit”), while a second level can represent a group of multiple data units (which can also be referred to herein as a “super management unit”). A third level can represent group of multiple groups of data units from the second level (i.e., a group of super management units). Depending on the embodiment, there can be any number of different levels in the hierarchy, each operating on successively larger groups of data units. Wear leveling can be performed at each level of the hierarchy using different wear leveling techniques and at different frequencies. For example, multi-level wear leveling can include wear leveling at the first level using algebraic mapping implemented by a first function every five minutes or every 1000 host writes, and wear leveling at the second level using algebraic mapping implemented by a second function every 30 minutes or every 5000 host writes. The second mapping function can be either the same or different than the first mapping function, depending on the embodiment. Wear leveling at the third level can be performed using algebraic mapping implemented by a third function or by using indirect fully associative mapping implemented by a look-up table every one hour or every 10,000 host writes. In other implementations, the wear leveling techniques and/or the associated frequencies can vary as appropriate. The multi-level wear leveling scheme described herein allows for efficient and effective wear leveling in memory sub-systems having high numbers of data units, such as when in-place data replacement media is used, and having large storage capacities without resulting in the look-up table used at the third level becoming excessively large in size. A third instance of wear-leveling may be performed if required, and can be based on a third set of write operations and the corresponding quantity (i.e., a predetermined threshold value)).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Danielson and Onishi with those of Tai. Tai teaches using a third wear leveling operation based on a third quantity of a set of write operations. The more frequently wear leveling operations are performed, the more likely the memory system as a whole is to have an extended lifespan and perform at an ideal level (Tai paragraph [0015], Aspects of the disclosure address the above and other deficiencies by implementing multi-level wear leveling for non-volatile memory. In one implementation, multi-level wear leveling utilizes a hierarchy of levels of data units having different sizes. For example, a first level can represent individual data units, such as a data block or page of a memory component (which can also be referred to herein as a “management unit”), while a second level can represent a group of multiple data units (which can also be referred to herein as a “super management unit”). A third level can represent group of multiple groups of data units from the second level (i.e., a group of super management units). Depending on the embodiment, there can be any number of different levels in the hierarchy, each operating on successively larger groups of data units. Wear leveling can be performed at each level of the hierarchy using different wear leveling techniques and at different frequencies. For example, multi-level wear leveling can include wear leveling at the first level using algebraic mapping implemented by a first function every five minutes or every 1000 host writes, and wear leveling at the second level using algebraic mapping implemented by a second function every 30 minutes or every 5000 host writes. The second mapping function can be either the same or different than the first mapping function, depending on the embodiment. Wear leveling at the third level can be performed using algebraic mapping implemented by a third function or by using indirect fully associative mapping implemented by a look-up table every one hour or every 10,000 host writes. In other implementations, the wear leveling techniques and/or the associated frequencies can vary as appropriate).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Danielson in view of Onishi as applied to claim 1 above, and further in view of Tai and further in view of Franklin et al. (US Publication No. 2018/0285007 -- "Franklin").
Regarding claim 9, Danielson in view of Onishi in further view of Tai teaches The method of claim 1, further comprising: performing, prior to performing the first quantity of write operations, a third quantity of write operations; (Danielson paragraph [0023], In general, the controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 112A to 112N. The controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical block address and a physical block address that are associated with the memory devices 112A to 112N. The controller 115 can further include host interface circuitry to communicate with the host system 120 via the physical host interface. The host interface circuitry can convert the commands received from the host system into command instructions to access the memory devices 112A to 112N as well as convert responses associated with the memory devices 112A to 112N into information for the host system 120. A plurality of first and second write operations may be received from the host by the memory device/controller and subsequently performed/executed) determining the first quantity of write operations at the memory system, greater than the third quantity of write operations, based at least in part on determining to not perform the third wear leveling operation; and determining whether to perform the first wear leveling operation at the memory system based at least in part on performing the first quantity of write operations at the memory system (Tai paragraph [0015], Aspects of the disclosure address the above and other deficiencies by implementing multi-level wear leveling for non-volatile memory. In one implementation, multi-level wear leveling utilizes a hierarchy of levels of data units having different sizes. For example, a first level can represent individual data units, such as a data block or page of a memory component (which can also be referred to herein as a “management unit”), while a second level can represent a group of multiple data units (which can also be referred to herein as a “super management unit”). A third level can represent group of multiple groups of data units from the second level (i.e., a group of super management units). Depending on the embodiment, there can be any number of different levels in the hierarchy, each operating on successively larger groups of data units. Wear leveling can be performed at each level of the hierarchy using different wear leveling techniques and at different frequencies. For example, multi-level wear leveling can include wear leveling at the first level using algebraic mapping implemented by a first function every five minutes or every 1000 host writes, and wear leveling at the second level using algebraic mapping implemented by a second function every 30 minutes or every 5000 host writes. The second mapping function can be either the same or different than the first mapping function, depending on the embodiment. Wear leveling at the third level can be performed using algebraic mapping implemented by a third function or by using indirect fully associative mapping implemented by a look-up table every one hour or every 10,000 host writes. In other implementations, the wear leveling techniques and/or the associated frequencies can vary as appropriate. The multi-level wear leveling scheme described herein allows for efficient and effective wear leveling in memory sub-systems having high numbers of data units, such as when in-place data replacement media is used, and having large storage capacities without resulting in the look-up table used at the third level becoming excessively large in size. A third instance of wear-leveling may be performed if required, and can be based on a third set of write operations and the corresponding quantity (i.e., a predetermined threshold value)).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Danielson and Onishi with those of Tai. Tai teaches using a third wear leveling operation based on a third quantity of a set of write operations. The more frequently wear leveling operations are performed, the more likely the memory system as a whole is to have an extended lifespan and perform at an ideal level (Tai paragraph [0015], Aspects of the disclosure address the above and other deficiencies by implementing multi-level wear leveling for non-volatile memory. In one implementation, multi-level wear leveling utilizes a hierarchy of levels of data units having different sizes. For example, a first level can represent individual data units, such as a data block or page of a memory component (which can also be referred to herein as a “management unit”), while a second level can represent a group of multiple data units (which can also be referred to herein as a “super management unit”). A third level can represent group of multiple groups of data units from the second level (i.e., a group of super management units). Depending on the embodiment, there can be any number of different levels in the hierarchy, each operating on successively larger groups of data units. Wear leveling can be performed at each level of the hierarchy using different wear leveling techniques and at different frequencies. For example, multi-level wear leveling can include wear leveling at the first level using algebraic mapping implemented by a first function every five minutes or every 1000 host writes, and wear leveling at the second level using algebraic mapping implemented by a second function every 30 minutes or every 5000 host writes. The second mapping function can be either the same or different than the first mapping function, depending on the embodiment. Wear leveling at the third level can be performed using algebraic mapping implemented by a third function or by using indirect fully associative mapping implemented by a look-up table every one hour or every 10,000 host writes. In other implementations, the wear leveling techniques and/or the associated frequencies can vary as appropriate).
Danielson in view of Onishi in further view of Tai does not teach refraining from performing a third wear leveling operation at the memory system prior to performing the first wear leveling operation based at least in part on determining to not perform the third wear leveling operation.
However, Franklin teaches refraining from performing a third wear leveling operation at the memory system prior to performing the first wear leveling operation based at least in part on determining to not perform the third wear leveling operation (Franklin paragraph [0122], A means for selectively skipping wear leveling in response to receiving one or more refresh commands and/or triggers, in various embodiments, may include a maintenance component 150, a maintenance circuit 506, a wear leveling circuit 604, a refresh circuit 602, a retirement circuit 606, a read/write circuit 504, a device controller 126, an on-die controller 220, a state machine 222, an integrated circuit device, an FPGA, an ASIC, other logic hardware, and/or other executable code stored on a computer readable storage medium. Other embodiments may include similar and/or equivalent means for selectively skipping wear leveling in response to receiving one or more refresh commands and/or triggers. The wear level operations can be chosen to be skipped in certain circumstances).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Danielson, Onishi, and Tai with those of Franklin. Franklin teaches a means for a memory apparatus to skip a potential wear leveling operation. This can be performed in the event that a wear leveling operation is determined to be redundant, unnecessary, or an operation performing a similar function is already scheduled (Franklin paragraph [0037], By performing a maintenance operation or portion thereof in response to a refresh command, instead of, or in addition to, performing the maintenance operation in the background, in some embodiments, a maintenance component 150 may allow a non-volatile memory element 123 and/or a non-volatile memory device 120 to operate synchronously (e.g., responding to a storage request such as a read or write request with little or no delay from performing a background maintenance operation and/or otherwise communicating synchronously with a host 110, a processor 111, or the like). Synchronous operation of a non-volatile memory device 120 and/or a non-volatile memory element 123, as used herein, comprises a non-volatile memory device 120 and/or a non-volatile memory element 123 recognizing control inputs (e.g., commands, data, addresses, or the like) in response to an external clock input (e.g., over a memory bus 125 or the like). Also see Franklin paragraph [0041], However, for compatibility with the same host memory controller and/or refresh command, in certain embodiments, a maintenance component 150 may perform one or more maintenance operations or a portion thereof on non-volatile memory cells of a non-volatile memory medium 122 of one or more non-volatile memory elements 123 in response to a refresh command. For example, a maintenance component 150 may instead, or on occasion, use or repurpose some or all of the refresh commands to perform a different maintenance operation for a type of memory medium 122 that doesn't require a volatile memory refresh operation such as storage class memory or other non-volatile memory, and/or may perform a different type of maintenance operation for a memory medium 122 that does require a volatile memory refresh operation (e.g., in addition to a volatile memory refresh operation), or the like).
Claim(s) 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Danielson in view of Onishi as applied to claim 11 above, and further in view of Tai.
Regarding claim 18, Danielson in view of Onishi in further view of Tai teaches The method of claim 11, further comprising: performing the second wear leveling operation at the memory system based at least in part on determining to perform the second wear leveling operation; (Danielson paragraph [0039], FIG. 4B illustrates an example of determining whether to store other data at a memory device based on the usage of the memory devices 450, in accordance with embodiments of the present disclosure. In the present illustration, the actual usage of a memory cell of memory device 420 is 94 write operations performed on a memory cell of memory device 420. Because the actual usage of the memory cell of memory device 420 is less than the usage threshold (e.g., 100 write operations) for memory device 420, data can be stored at the memory cell of the memory device 420. The actual usage of a memory cell of memory device 430, however, is 50 write operations performed on a memory cell of memory device 430. Because the actual usage of the memory cell (e.g., 50 write operations) exceeds the usage threshold (e.g., 50) for memory device 430, data is not stored at the memory cell of memory device 430. The process for a wear leveling operation (determining which memory blocks/cells are viable for storage and using them according to said determinations) can be based on various usage characteristics such as write operation quantity, as indicated here. For further details regarding the usage characteristic being used for wear leveling operations, see Danielson paragraphs [0022-0023], The controller 115 can include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory system 110, including handling communications between the memory system 110 and the host system 120. In some embodiments, the local memory 119 can include memory registers storing memory pointers, fetched data, etc. The local memory 119 can also include read-only memory (ROM) for storing micro-code. While the example memory system 110 in FIG. 1 has been illustrated as including the controller 115, in another embodiment of the present disclosure, a memory system 110 may not include a controller 115, and may instead rely upon external control (e.g., provided by an external host, or by a processor or controller separate from the memory system). In general, the controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 112A to 112N. The controller 115 can be responsible for other operations such as wear leveling operations) determining a third quantity of write operations at the memory system, less than the second quantity of write operations, based at least in part on determining to perform the second wear leveling operation; and determining whether to perform a third wear leveling operation at the memory system based at least in part on performing the third quantity of write operations at the memory system (Tai paragraph [0015], Aspects of the disclosure address the above and other deficiencies by implementing multi-level wear leveling for non-volatile memory. In one implementation, multi-level wear leveling utilizes a hierarchy of levels of data units having different sizes. For example, a first level can represent individual data units, such as a data block or page of a memory component (which can also be referred to herein as a “management unit”), while a second level can represent a group of multiple data units (which can also be referred to herein as a “super management unit”). A third level can represent group of multiple groups of data units from the second level (i.e., a group of super management units). Depending on the embodiment, there can be any number of different levels in the hierarchy, each operating on successively larger groups of data units. Wear leveling can be performed at each level of the hierarchy using different wear leveling techniques and at different frequencies. For example, multi-level wear leveling can include wear leveling at the first level using algebraic mapping implemented by a first function every five minutes or every 1000 host writes, and wear leveling at the second level using algebraic mapping implemented by a second function every 30 minutes or every 5000 host writes. The second mapping function can be either the same or different than the first mapping function, depending on the embodiment. Wear leveling at the third level can be performed using algebraic mapping implemented by a third function or by using indirect fully associative mapping implemented by a look-up table every one hour or every 10,000 host writes. In other implementations, the wear leveling techniques and/or the associated frequencies can vary as appropriate. The multi-level wear leveling scheme described herein allows for efficient and effective wear leveling in memory sub-systems having high numbers of data units, such as when in-place data replacement media is used, and having large storage capacities without resulting in the look-up table used at the third level becoming excessively large in size. A third instance of wear-leveling may be performed if required, and can be based on a third set of write operations and the corresponding quantity (i.e., a predetermined threshold value)).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Danielson and Onishi with those of Tai. Tai teaches using a third wear leveling operation based on a third quantity of a set of write operations. The more frequently wear leveling operations are performed, the more likely the memory system as a whole is to have an extended lifespan and perform at an ideal level (Tai paragraph [0015], Aspects of the disclosure address the above and other deficiencies by implementing multi-level wear leveling for non-volatile memory. In one implementation, multi-level wear leveling utilizes a hierarchy of levels of data units having different sizes. For example, a first level can represent individual data units, such as a data block or page of a memory component (which can also be referred to herein as a “management unit”), while a second level can represent a group of multiple data units (which can also be referred to herein as a “super management unit”). A third level can represent group of multiple groups of data units from the second level (i.e., a group of super management units). Depending on the embodiment, there can be any number of different levels in the hierarchy, each operating on successively larger groups of data units. Wear leveling can be performed at each level of the hierarchy using different wear leveling techniques and at different frequencies. For example, multi-level wear leveling can include wear leveling at the first level using algebraic mapping implemented by a first function every five minutes or every 1000 host writes, and wear leveling at the second level using algebraic mapping implemented by a second function every 30 minutes or every 5000 host writes. The second mapping function can be either the same or different than the first mapping function, depending on the embodiment. Wear leveling at the third level can be performed using algebraic mapping implemented by a third function or by using indirect fully associative mapping implemented by a look-up table every one hour or every 10,000 host writes. In other implementations, the wear leveling techniques and/or the associated frequencies can vary as appropriate).
Regarding claim 19, Danielson in view of Onishi in further view of Tai teaches The method of claim 11, further comprising: refraining from performing the second wear leveling operation at the memory system based at least in part on determining to not perform the second wear leveling operation; (Danielson paragraph [0033], The subsequent data can be received from a host system for storage by the memory system. In one embodiment, if the usage thresholds for the memory devices have not been exceeded, the subsequent data can be stored at the first memory device or second memory device based on characteristics associated with the subsequent data. Further detail with regards to storing data based on characteristics associated with the data will be discussed below. If the wear leveling command is ignored, a second quantity of write operations may be tracked and if exceeding a determined amount, a wear leveling operation may be automatically performed) determining a third quantity of write operations at the memory system, greater than the second quantity of write operations, based at least in part on determining to not perform the second wear leveling operation; and determining whether to perform the wear leveling operation at the memory system based at least in part on performing the third quantity of write operations at the memory system (Tai paragraph [0015], Aspects of the disclosure address the above and other deficiencies by implementing multi-level wear leveling for non-volatile memory. In one implementation, multi-level wear leveling utilizes a hierarchy of levels of data units having different sizes. For example, a first level can represent individual data units, such as a data block or page of a memory component (which can also be referred to herein as a “management unit”), while a second level can represent a group of multiple data units (which can also be referred to herein as a “super management unit”). A third level can represent group of multiple groups of data units from the second level (i.e., a group of super management units). Depending on the embodiment, there can be any number of different levels in the hierarchy, each operating on successively larger groups of data units. Wear leveling can be performed at each level of the hierarchy using different wear leveling techniques and at different frequencies. For example, multi-level wear leveling can include wear leveling at the first level using algebraic mapping implemented by a first function every five minutes or every 1000 host writes, and wear leveling at the second level using algebraic mapping implemented by a second function every 30 minutes or every 5000 host writes. The second mapping function can be either the same or different than the first mapping function, depending on the embodiment. Wear leveling at the third level can be performed using algebraic mapping implemented by a third function or by using indirect fully associative mapping implemented by a look-up table every one hour or every 10,000 host writes. In other implementations, the wear leveling techniques and/or the associated frequencies can vary as appropriate. The multi-level wear leveling scheme described herein allows for efficient and effective wear leveling in memory sub-systems having high numbers of data units, such as when in-place data replacement media is used, and having large storage capacities without resulting in the look-up table used at the third level becoming excessively large in size. A third instance of wear-leveling may be performed if required, and can be based on a third set of write operations and the corresponding quantity (i.e., a predetermined threshold value)).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Danielson and Onishi with those of Tai. Tai teaches using a third wear leveling operation based on a third quantity of a set of write operations. The more frequently wear leveling operations are performed, the more likely the memory system as a whole is to have an extended lifespan and perform at an ideal level (Tai paragraph [0015], Aspects of the disclosure address the above and other deficiencies by implementing multi-level wear leveling for non-volatile memory. In one implementation, multi-level wear leveling utilizes a hierarchy of levels of data units having different sizes. For example, a first level can represent individual data units, such as a data block or page of a memory component (which can also be referred to herein as a “management unit”), while a second level can represent a group of multiple data units (which can also be referred to herein as a “super management unit”). A third level can represent group of multiple groups of data units from the second level (i.e., a group of super management units). Depending on the embodiment, there can be any number of different levels in the hierarchy, each operating on successively larger groups of data units. Wear leveling can be performed at each level of the hierarchy using different wear leveling techniques and at different frequencies. For example, multi-level wear leveling can include wear leveling at the first level using algebraic mapping implemented by a first function every five minutes or every 1000 host writes, and wear leveling at the second level using algebraic mapping implemented by a second function every 30 minutes or every 5000 host writes. The second mapping function can be either the same or different than the first mapping function, depending on the embodiment. Wear leveling at the third level can be performed using algebraic mapping implemented by a third function or by using indirect fully associative mapping implemented by a look-up table every one hour or every 10,000 host writes. In other implementations, the wear leveling techniques and/or the associated frequencies can vary as appropriate).
Response to Arguments
Applicant’s arguments, see pages 1-5 (numbered pages 10-15), filed July 1st, 2026, with respect to the rejection(s) of claim(s) 1, 10-11 and 20 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Danielson et al. (US Publication No. 2019/0332317 -- "Danielson") in view of Onishi (US Publication No. 2022/0308766 – “Onishi”).
In response to the applicant’s amendments and corresponding arguments, the Onishi reference has been added. The Onishi reference is cited to disclose the concept of performing a first/second wear leveling based on a first and second write threshold quantity values, in relation to a performed write quantities and previous wear leveling operations, as described in further detail above. The examiner notes that claim 21 is currently rejected under 35 U.S.C. 112(b) and requires clarifying amendments for a determination of allowability to be made.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.C.K./ Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/ Supervisory Patent Examiner, Art Unit 2133
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