Prosecution Insights
Last updated: April 19, 2026
Application No. 17/811,846

PROGRAMMABLE FINITE FIELD GENERATOR FOR MEMORY

Non-Final OA §101§103
Filed
Jul 11, 2022
Examiner
BUI, KENNY KIM
Art Unit
2182
Tech Center
2100 — Computer Architecture & Software
Assignee
Micron Technology, Inc.
OA Round
1 (Non-Final)
60%
Grant Probability
Moderate
1-2
OA Rounds
4y 0m
To Grant
85%
With Interview

Examiner Intelligence

Grants 60% of resolved cases
60%
Career Allow Rate
6 granted / 10 resolved
+5.0% vs TC avg
Strong +25% interview lift
Without
With
+25.0%
Interview Lift
resolved cases with interview
Typical timeline
4y 0m
Avg Prosecution
27 currently pending
Career history
37
Total Applications
across all art units

Statute-Specific Performance

§101
29.8%
-10.2% vs TC avg
§103
38.3%
-1.7% vs TC avg
§102
7.7%
-32.3% vs TC avg
§112
22.6%
-17.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 10 resolved cases

Office Action

§101 §103
DETAILED ACTION The Office Action is sent in response to Applicant’s Communication received on 07/11/2022 for application number 17/811,846. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Oath/declaration, and Claims. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitations of: generating, based on performing one or more iterations of updating the set of values, a first sequence comprising a concatenation of first bits from values stored in the first register. outputting a second sequence comprising a concatenation of second bits from the values stored in the first register. the first bits comprise least significant bits of the values stored in the first register during one or more iterations of updating the set of values; and the second bits comprise most significant bits of the values stored in the first register during one or more iterations of updating the set of values. must be shown or the features canceled from the claims. No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification The disclosure is objected to because of the following informalities: Par.9, ll.15, “varying quantities substantially random” should read as “varying quantities of substantially random”. Appropriate correction is required. Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-25 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. Under the Alice Framework Step 1, claims 1-13 recite a method and, therefore, is a process. claims 14-21 recites an apparatus and, therefore, is a machine. Claims 22-25 recites a non-transitory computer-readable medium and, therefore, is an article of manufacture. Under the Alice Framework Step 2A prong 1, claim 14 recites An apparatus, comprising: an array of configuration registers configured to store coefficient values indicating Galois Field multipliers; a set of registers coupled with the array of configuration registers and configured to store a set of values; and a controller coupled with array of configuration registers and the set of registers, the controller configured to update the set of values stored in the set of registers, wherein to update the set of values, the controller is further configured to: perform, according to the Galois Field multipliers indicated by the coefficient values, a set of Galois Field multiplication operations on the set of values stored in the set of registers to generate a set of multiplied values, perform a Galois Field summation operation on one or more of the set of multiplied values to generate an updated value, store the updated value in a first register in the set of registers based on performing the Galois Field summation operation, and shift the set of values stored in the set of registers from the first register to remaining registers in the set of registers. The above underlined limitations are related to generating streams of pseudo random numbers using Galois Field operations which amount to “mathematical calculations and relationships that fall under the “mathematical concepts” of abstract ideas (see at least specification paragraphs 35-37, 39-48, and 50-51). Accordingly, the claim recites an abstract idea. Under the Alice Framework Step 2A prong 2, claim 14 recites the following additional elements: “an array of configuration registers configured to store coefficient values indicating Galois Field multipliers”, “a set of registers coupled with the array of configuration registers and configured to store a set of values”, “a controller coupled with array of configuration registers and the set of registers, the controller configured to”, and “store the updated value in a first register in the set of registers based on performing the Galois Field summation operation”. However, the additional elements of Galois Field multipliers, an array of configuration registers, a set of registers, and a controller are recited at a high-level of generality (i.e., as a generic computer components storing data for the math; as a generic computer components storing data for computing Galois Field multiplications; and as a generic computer component for executing instructions to perform the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “an array of configuration registers configured to store coefficient values indicating Galois Field multipliers”, “a set of registers… configured to store a set of values”, and “store the updated value in a first register in the set of registers based on performing the Galois Field summation operation” are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application. Under the Alice Framework Step 2B, claim 14 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of Galois Field multipliers, an array of configuration registers, a set of registers, and a controller are recited at a high-level of generality (i.e., as a generic computer components storing data for the math; as a generic computer components storing data for computing Galois Field multiplications; and as a generic computer component for executing instructions to perform the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “an array of configuration registers configured to store coefficient values…”, “a set of registers… configured to store a set of values”, and “store the updated value in a first register in the set of registers based on performing the Galois Field summation operation” are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea. Under the Alice Framework Step 2A prong 1, Claims 15-21 recite further steps and details to generating streams of pseudo random numbers using Galois Field operations which amount to “mathematical calculations and relationships that fall under the “mathematical concepts” of abstract ideas Regarding Claim 15, it is directed to storing the data for the second Galois Field multipliers to update the values. Accordingly, the claims recites an abstract idea. Under the Alice Framework Step 2A prong 2, claim 15 recites the following additional elements: “store… second coefficient values in the array of configuration registers” and “second Galois Field multipliers”. However, the additional element of second Galois Field multipliers are recited at a high-level of generality (i.e., as a generic computer components storing data for computing Galois Field multiplications) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional element of “store… second coefficient values in the array of configuration registers” are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application. Under the Alice Framework Step 2B, claim 15 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of second Galois Field multipliers are recited at a high-level of generality (i.e., as a generic computer components storing data for computing Galois Field multiplications) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional element of “store… second coefficient values in the array of configuration registers” are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea. Regarding Claim 16, it is directed to the above multipliers computing operations of a given order of Galois Fields. Claim 16 does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recites an abstract idea. Regarding claims 17-20, it is directed to generating an lower order Galois field given an high order Galois field. Claims 17-20 does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recites an abstract idea. Regarding claim 20, it is directed to the output of the Galois Field operations for random number generation. Claim 20 does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recites an abstract idea. Regarding claim 21, it is directed to another set of claim 14. AS such, it follows from claim 14. Accordingly, the claims recites an abstract idea. Under the Alice Framework Step 2A prong 2, claim 21 recites the following additional elements: “store second coefficient values in a second array of configuration registers, the second coefficient values indicating second Galois Field multipliers”, “store a second set of values in a second set of registers”, and “store the second updated value in a second register in the second set of registers…”. However, the additional elements of second Galois Field multipliers, a second array of configuration registers, and a second set of registers are recited at a high-level of generality (i.e., as a generic computer components storing data for the math; and as a generic computer components storing data for computing Galois Field multiplications;) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “store second coefficient values in a second array of configuration registers, the second coefficient values…”, “store a second set of values in a second set of registers”, and “store the second updated value in a second register in the second set of registers…”are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application. Under the Alice Framework Step 2B, claim 14 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of second Galois Field multipliers, a second array of configuration registers, and a second set of registers are recited at a high-level of generality (i.e., as a generic computer components storing data for the math; and as a generic computer components storing data for computing Galois Field multiplications;) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “store second coefficient values in a second array of configuration registers, the second coefficient values…”, “store a second set of values in a second set of registers”, and “store the second updated value in a second register in the second set of registers…”are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea. Regarding claims 1-3, 5-7, 10, and 11 are directed to claims 14-21 respectively. A mere change in statutory class is obvious. As such, claims 1-3, 5-7, 10, and 11 are rejected for the reasons given above Under the Alice Framework Step 2A prong 1, Claims 4, 8-9, and 12-13 recite further steps and details to generating streams of pseudo random numbers using Galois Field operations which amount to “mathematical calculations and relationships that fall under the “mathematical concepts” of abstract ideas Regarding Claim 4, it is directed to storing the bits of the Galois Field and the relation between the number of bits and the Galois Field. Accordingly, the claims recites an abstract idea. Under the Alice Framework Step 2A prong 2, claim 4 recites the following additional elements: “each register in the set of registers is for storing a quantity of bits”. However, the additional element of each register are recited at a high-level of generality (i.e., as a generic computer components storing data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional element of “storing a quantity of bits” are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application. Under the Alice Framework Step 2B, claim 4 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of each register are recited at a high-level of generality (i.e., as a generic computer components storing data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional element of “storing a quantity of bits” are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea. Regarding Claim 8, it is directed to generating a seed sequence based on Galois Fields and performing operations using the seed. Claim 8 does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recites an abstract idea. Regarding Claim 9, it is directed to generating broad spectrum noise based on Galois Fields. Claim 9 does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recites an abstract idea. Regarding claim 12, is merely applying clock signals for the math to operate properly. Accordingly, the claims recites an abstract idea. Under the Alice Framework Step 2A prong 2, claim 12 recites the following additional elements: “updating the set of values stored in the set of registers is based on a clock signal changing from a first value to a second value”. However, the additional element of updating the set of values stored in the set of registers is based on a clock signal changing from a first value to a second value is recited at a high-level of generality (i.e., as a generic computer components for computing the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application. Under the Alice Framework Step 2B, claim 12 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of updating the set of values stored in the set of registers is based on a clock signal changing from a first value to a second value is recited at a high-level of generality (i.e., as a generic computer components for computing the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea. Regarding claim 13, is merely applying a finite field generator to compute the math. Accordingly, the claims recites an abstract idea. Under the Alice Framework Step 2A prong 2, claim 12 recites the following additional elements: “a finite field generator”. However, the additional element of a finite field generator is recited at a high-level of generality (i.e., as a generic computer components for computing the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application. Under the Alice Framework Step 2B, claim 12 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of a finite field generator is recited at a high-level of generality (i.e., as a generic computer components for computing the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea. Under the Alice Framework Step 2A prong 1, claim 22 recites A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor to: store coefficient values in an array of configuration registers, the coefficient values indicating Galois Field multipliers; store a set of values in a set of registers based on storing the coefficient values; and update the set of values stored in the set of registers, wherein the instructions to update the set of values are executable by the processor to: perform, according to the Galois Field multipliers indicated by the coefficient values, a set of Galois Field multiplication operations on the set of values stored in the set of registers to generate a set of multiplied values, perform a Galois Field summation operation on one or more of the set of multiplied values to generate an updated value, store the updated value in a first register in the set of registers based on performing the Galois Field summation operation, and shift the set of values stored in the set of registers from the first register to remaining registers in the set of registers. The above underlined limitations are related to generating streams of pseudo random numbers using Galois Field operations which amount to “mathematical calculations and relationships that fall under the “mathematical concepts” of abstract ideas (see at least specification paragraphs 35-37, 39-48, and 50-51). Accordingly, the claim recites an abstract idea. Under the Alice Framework Step 2A prong 2, claim 22 recites the following additional elements: “the code comprising instructions “, “store coefficient values in an array of configuration registers, the coefficient values indicating Galois Field multipliers”, “store a set of values in a set of registers based on storing the coefficient values”, “the instructions to update the set of values are executable by the processor to”, and “store the updated value in a first register in the set of registers based on performing the Galois Field summation operation”. However, the additional elements of the code comprising instructions, Galois Field multipliers, an array of configuration registers, a set of registers, and a processor are recited at a high-level of generality (i.e., as a generic computer components storing data for storing instructions; as a generic computer components storing data for the math; as a generic computer components storing data for computing Galois Field multiplications; and as a generic computer component for executing instructions to perform the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “store coefficient values in an array of configuration registers…”, “store a set of values in a set of registers based on storing the coefficient values”, and “store the updated value in a first register in the set of registers based on performing the Galois Field summation operation” are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application. Under the Alice Framework Step 2B, claim 22 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of the code comprising instructions, Galois Field multipliers, an array of configuration registers, a set of registers, and a processor are recited at a high-level of generality (i.e., as a generic computer components storing data for storing instructions; as a generic computer components storing data for the math; as a generic computer components storing data for computing Galois Field multiplications; and as a generic computer component for executing instructions to perform the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “store coefficient values in an array of configuration registers…”, “store a set of values in a set of registers based on storing the coefficient values”, and “store the updated value in a first register in the set of registers based on performing the Galois Field summation operation” are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea. Claims 23-25 are directed to claims 15-17, respectively. A mere change in statutory class is obvious. As such, claims 23-25 are rejected for the reasons given above. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1, 12, 13, 14, 17, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Rose (US 6,490,357 B1), and in view of Patterson et al. (NPL: “Computer Organization and Design MIPS Edition: The Hardware/Software Interface (5th ed.)”), hereinafter Patterson. Regarding claim 14, Rose discloses: An apparatus comprising: memory configured to store coefficient values indicating Galois Field Multipliers ["each element and coefficient of the recurrence relation occupying one byte of memory" Col.4,ll.51-55]; a set of registers coupled with the array of configuration registers and configured to store a set of values [Fig.1 12A-12K, 14A-14K]; and a controller configured to update the set of values stored in the set of registers, wherein to update the set of values, the controller is further configured to ["This results in each element and coefficient of the recurrence relation occupying one byte of memory. Byte manipulations can be performed efficiently by the processor." Col.4, ll.43-57; "Processor 22 is the hardware which performs the manipulation required by the generator" Col.5, ll.3-4]: perform, according to the Galois Field multipliers indicated by the coefficient values, a set of Galois Field multiplication operations on the set of values stored in the set of registers to generate a set of multiplied values [Fig.1, Galois Field multipliers 14, see Col.4-5,ll.65-14], perform a Galois Field summation operation on one or more of the set of multiplied values to generate an updated value [Fig.1, Galois field Adders 16, see Col.4-5,ll.65-14], store the updated value in a first register in the set of registers based on performing the Galois Field summation operation [Fig.1, outputs of the adders 16 are placed into register 12k], and shift the set of values stored in the set of registers from the first register to remaining registers in the set of registers ["Linear feedback shift register (LFSR) is based on a recurrence relation over the Galois field," Col.4, ll.15-31; Fig1, shows register 12 shifting data through]. However, Rose does not explicitly disclose an array of configuration registers configured to store coefficient values indicating Galois Field Multipliers In the analogous art of computer architecture, Patterson teaches using set of registers to store multi-bit data [“We can use an array of D flip-flops to build a register that can hold a multibit datum, such as a byte or word… A register file consists of a set of registers that can be read and written by supplying a register number to be accessed... an array of registers built from D flip-flops” p.B-54] It would have been obvious to one of ordinary skill in the art, having the teachings of Rose and Patterson before him before the effective filing date of the claimed invention to modify the memory taught by Rose to include a register for storing data taught by Patterson, in order to implement multi-bit storage with single clock cycle control [Patterson: p.B-54-B-56]. Regarding claim 17, Rose and Patterson disclose the invention substantially as claimed. See the discussion of claim 14 above. Rose further discloses generate, based on performing one or more iterations of updating the set of values, a first sequence comprising a concatenation of first bits from values stored in the first register [Fig.1;“where Sn+k is the output element, Cj is a constant coefficient, k is the order of the recurrence relation, and n is an index in time… In the preferred embodiment, a Galois field with 256 elements ( GF(2^8)) is utilized. This results, in each element and coefficient of the recurrence relation occupying one byte of memory.” Col.4 22-35] Claim 1 is directed to claim 14. A mere change in statutory class is obvious. As such claim 1 is rejected for the reasons given above. Regarding claim 22, Rose discloses a non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor [“Controller 20 connects to processor 22 and comprises the set of instructions which directs the operations of processor 22. Thus, controller 20 can comprise a software program or a set of microcodes… The instructions and tables can be stored in read-only memory,” Col.4-5,ll.65-5] The remaining limitations are directed to claim 14. A mere change in statutory class is obvious. As such claim 22 is rejected for the reasons given above. Regarding claim 12, Rose and Patterson disclose the invention substantially as claimed. See the discussion of claim 1 above. Rose discloses that registers are clocked [“Stuttering is the process whereby the register is clocked in a variable and unpredictable manner.”] Patterson also teaches that registers are clocked [“a clock that controls the writing into the register”] Regarding claim 13, Rose and Patterson disclose the invention substantially as claimed. See the discussion of claim 1 above. Rose discloses that the set of registers are associated with a finite field [“the finite field selected is the Galois field with 256 elements (GF(2^8)) or other Galois fields with 2^n elements” col.4,ll.43-50] Claims 11 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Rose and Patterson, and in view of Farrugia (US 2013/0191427 A1). Regarding claim 21, Rose and Patterson disclose the invention substantially as claimed. See the discussion of claim 14 above. Rose and Patterson does not explicitly disclose the additional limitations of claim 21 In the analogous art of Random number generation, Farrugia teaches using multiple pseudo-random number generators in parallel [Figs.2/3; and par. 33,36,37,47, and 62] It would have been obvious to one of ordinary skill in the art, having the teachings of Rose, Patterson, and Farrugia before him before the effective filing date of the claimed invention to include modify the system of the combination of Rose and Patterson, to include multiple LFSRs generators as disclosed by Farrugia, in order to, allow for parallel generation of random numbers clocked at the same time and allow for different lengths/orders of LFSRs to improve flexibility [par. 33,36,37,47, and 62]. The combination of Rose, Patterson, and Farrugia discloses the additional limitations of claim 21. Claim 11 is directed to claim 21. A mere change in statutory class is obvious. As such, claim 11 is rejected for the reasons given above. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Milovanovic et al. (NPL: “CONCURRENT GENERATION OF PSEUDO RANDOM NUMBERS WITH LFSR OF FIBONACCI AND GALOIS TYPE”) that discloses multiple parallel output LFSR. See figure 4. Ying et al. (NPL: “Asymmetry dual-LFSR reseeding for low power BIST”) that discloses different order LSFRs. See figure 4. Ruha et al. (US 6,445,318 B1) discloses noise generation for spread spectrum using multiple LSFR and combining LSFRs. See figs.3 and 7. Lan et al. (US 5,812,438 A) discloses breaking down GF(n) into sub-GF(n). See Abstract. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenny K. Bui whose telephone number is (571)270-0604. The examiner can normally be reached 8:00 am to 3:00 pm on Monday, 8:00 am to 4:00 pm on Tuesday to Friday ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew T Caldwell can be reached at (571)272-3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KENNY K. BUI/Patent Examiner, Art Unit 2182 0604 /ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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Prosecution Timeline

Jul 11, 2022
Application Filed
Feb 07, 2026
Non-Final Rejection — §101, §103 (current)

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