DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to amendment filed on 11/14/2025.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/14/2025 has been entered.
Response to Amendment
By this amendment, claims 1, 6, and 22 are amended. Claims 19-21 are canceled. Claims 23-25 are newly added claims. Therefore, claims 1-3, 5-7, 9-16, 18, and 22-25 are pending. Any objections and rejections not repeated below is withdrawn due to Applicant's amendment.
Response to Arguments
Applicant's arguments filed 11/14/2025 have been fully considered but they are not persuasive. Applicant argues in substance:
Applicant respectfully submits that at least the following features A-C of amended claim 1 are not disclosed in LIAO: 1) "the routing structure component is only provided in the general-purpose processing core" 2) "a bus directly coupling a routing structure component to the first on-chip cache without coupling any other cache" 3) "transferring, by a control unit in the dedicated acceleration core, an instruction completion indication of a predetermined co-processing unit."…
That is, the Office Action argues that the access control module in LIAO controls data access and that each unit in LIAO has a corresponding access control module.
Applicant respectfully submits that amended claim 1 is novel over LIAO at least because it recites "the routing structure component is only provided in the general-purpose processing core" and not in the dedicated acceleration core. Therefore LIAO is structurally different, as it fails to disclose the asymmetric location of the routing structure as recited in claim 1.
The Office Action states that LIAO discloses L1 cache (for each computation unit) and a L2 cache, and accessing one via the other. Further, the Office Action argues that the claims do not exclude accessing the cache via other caches. Amended claim 1 also recites "a bus directly coupling a routing structure component to the first on-chip cache without coupling any other cache," which is not disclosed by LIAO…
Applicant respectfully disagrees. LIAO does not disclose that there is a control unit in the dedicated acceleration core. Specifically, paragraph [0042] of LIAO cited merely discloses in-use functions of the task synchronization module, but is silent about the location (claim feature: in the dedicated acceleration core). However, POSITA would understand that paragraph [0042] discloses a centralized task synchronization module i.e. one task synchronization module per processor. Absent further structure or disclosure in LIAO, this should be so that the task
synchronization module can perform its functions stated in para. [0042], i.e. that the task synchronization module can freely communicate (i.e. receive inquiries and send notifications) with all types of cores…
Secondly, LIAO paragraph [0006] is silent about the location of the task synchronization module as being "in the dedicated acceleration core" as recited in claim 1. LIAO does not disclose that the task synchronization module is uniquely associated with or co-located in one core or even in one processing unit.
Therefore LIAO fails to disclose all of the limitations of claim 1, and so claim 1 is novel over LIAO.
Thus, Applicant respectfully submits that LIAO fails to disclose all of the limitations of amended claim 1. For at least similar reasons, Applicant respectfully submits that LIAO fails to disclose the limitations of amended claim 6. Accordingly, claims 1 and 6 are patentable over LIAO.
With regard to point (a), Examiner agrees with Applicant to withdraw prior art rejections from independent claims 1 and 6 (and respective dependent claims). In particular, the prior arts do not disclose the limitations “in response to determining that the instruction completion indication is received, acquiring, by the general-purpose processing core, data from a first on-chip cache inside the dedicated acceleration core through a data path for completing the computing task, the data path being configured to couple the general-purpose processing core to the first on-chip cache, wherein the data path is a bus directly coupling a routing structure component to the first on-chip cache without coupling any other cache, and the routing structure component is only provided in the general-purpose processing core and is coupled directly to the at least one processing unit of the general-purpose processing core” in claim 1; and the limitations “a data path, comprising a bus configured to directly couple the routing structure component to the first on-chip cache so that the at least one general-purpose processing unit can access the first on-chip cache without passing through any other cache, wherein the routing structure component is only provided in the general-purpose processing core” in claim 6.
However, as independent claim 14 was not amended similarly to claims 1 and 6, claims 14-16 and 18 are still rejected for the reasons in this Office Action’s 102 rejection below. Regarding Applicant’s arguments, LIAO still discloses the limitations of claim 14, wherein [0006] “…each of the computation units corresponding to a task queue, a storage unit, and a controller. The controller includes a task scheduling module, a task synchronization module and an access control module …”, [0040] “…The storage unit may be configured to store data required by the computation units to execute the computation subtasks. In some embodiments, the storage unit may include a cache memory such as L1 cache and/or L2 cache…”, [0044] “…As shown in FIG. 2C, in the interactive cooperation mode, the computation units need to wait for each other during execution, for example, particularly when the TU lacks certain capabilities but the CU is used for compensation, or when the CU lacks processing capabilities but the TU is used. In this mode, the data dependence and synchronization are realized on a cache memory (e.g., L2 cache) with a limited size, so as to minimize the latency time and improve the throughput of the TU/CU. For example, the cache temporarily storing the results generated by the TU is read by the CU to execute a user-defined operation, and the result is also stored in the cache for further reading by the TU…”. In other words, each computation unit (core) contains a task synchronization module (control unit), an access control module (routing structure component), and a storage unit (L1 cache), and all computation units of various types can share data and thus also access other computation units’ L1 caches via a L2 cache to maintain cache coherency. Furthermore, claim 14 does not exclude using a shared memory to access other core caches. Argument has not been found to be persuasive.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 14-16 and 18 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by LIAO et al. Pub. No. US 2021/0073170 Al (hereafter LIAO).
Regarding claim 14, LIAO anticipates the invention as claimed, including: An electronic device, comprising: at least one heterogeneous multi-core processor according to claim 6 ([0040] “FIG. 1 shows an on-chip heterogeneous AI processor according to an embodiment provided herein. The on-chip heterogeneous AI processor includes at least two different architectural types of computation units…”); and a memory connected to the at least one heterogeneous multi-core processor, wherein the memory stores one or more computer instructions executable by the at least one heterogeneous multi-core processor ([0040] “…The storage unit may be configured to store data required by the computation units to execute the computation subtasks. In some embodiments, the storage unit may include a cache memory such as L1 cache and/or L2 cache, and an on-chip memory such as a Scratch-pad Memory (SPM)…”), wherein the one or more computer instructions, when executed by the at least one heterogeneous multi-core processor, cause the electronic device to perform operations for processing a computing task by the at least one heterogeneous multi-core processor, the at least one heterogeneous multi-core processor comprising a general-purpose processing core and a dedicated acceleration core ([0040] “FIG. 1 shows an on-chip heterogeneous AI processor according to an embodiment provided herein. The on-chip heterogeneous AI processor includes at least two different architectural types of computation units. For example, a first type of computation units may be TUs and a second type of computation units may be CUs…”, Note: A CU computation unit is the general-purpose processing core, and a TU computation unit is the dedicated acceleration core), and the operations comprising: for a predetermined type of computing task, allocating a plurality of instruction blocks in the computing task to the general-purpose processing core and the dedicated acceleration core ([0046] “…Meanwhile, the computation subtasks tu1, tu2, ... , tu5, such as matrices, vectors and convolution, which may be suitable for execution by the TU computation units, are allocated to the task queue of the TU computation unit; and, the computation subtasks that are not supported by the TU computation unit and the user-defined computation subtasks cu1, cu2, cuN, cuN+1, cuN+2 are allocated to the task queue of the CU computation unit…”, Note: The subtasks are the plurality of instruction blocks allocated to a CU computation unit (general-purpose processing core) and a TU computation unit (dedicated acceleration core) based on subtask type); transferring, by a control unit in the dedicated acceleration core, an instruction completion indication of a predetermined co-processing unit coupled thereto to at least one processing unit of the general-purpose processing core through a signal path, the signal path being configured to couple the at least one general-purpose processing unit to the control unit ([0042] “…the task synchronization module can send an event notification to the relevant task queue and/or record the execution state of this computation subtask for subsequent inquiries … an inquiry may be sent to the task synchronization module regarding whether the subtask(s) on which the current subtask depends has been executed. If the subtask(s) has not been executed, the current subtask may need to wait.”, Note: The task synchronization module’s functions include the control unit’s functions, the event notification is the instruction completion indication, and event notifications are sent by the task synchronization module to task queues of computation units (general-purpose processing cores and dedicated acceleration cores) to notify and allow dependent subtasks on different computation units to execute); and in response to determining that the instruction completion indication is received, acquiring, by the general-purpose processing core, data from a first on-chip cache inside the dedicated acceleration core through a data path for completing the computing task, the data path being configured to couple the general-purpose processing core to the first on-chip cache ([0046] “…a certain task in the task queue can be set to be event-dependent by a hardware-level event synchronization technology, so that the data generated by other types of computation units can be read from a certain region of the cache or the on-chip memory when a certain event notification is received.”, Note: The event notification is the instruction completion indication, and the other types of computation units are the general-purpose processing cores and the dedicated acceleration cores); wherein acquiring the data comprises: sending an access address for the data to a routing structure component in the general-purpose processing core ([0045] “…In some embodiments, the access control module can also be configured to determine … the storage location and storage format of the intermediate results generated by the computation units…”, Note: Storage location is the access address, the access control module is the routing structure component, and the access control module must receive storage locations (access addresses) from computation units (general-purpose processing cores and the dedicated acceleration cores)); determining, by the routing structure component, to access a second on-chip cache inside the general-purpose processing core or the first on-chip cache based on the access address ([0040] “…The storage unit may be configured to store data required by the computation units to execute the computation subtasks. In some embodiments, the storage unit may include a cache memory such as L1 cache and/or L2 cache…”, [0045] “…In some embodiments, the access control module can also be configured to determine … the storage location and storage format of the intermediate results generated by the computation units…”, [0045] “With continued reference to FIG. 1, the access control module in the controller is mainly responsible for transporting and controlling the data involved in the computation subtasks…”, Note: The access control module is the routing structure component, and the access control module controls data access of computation units (general-purpose processing cores and the dedicated acceleration cores) where storage location is a L1 cache (for each computation unit) and L2 cache); and in response to determining to access the first on-chip cache, acquiring the data from the access address in the first on-chip cache ([0045] “…For example, the access control module can prefetch … the data involved in the computation subtasks from the off-chip memory to the on-chip memory and/or the cache memory through an access interface…”, Note: Data is received from cache).
Regarding claim 15, LIAO anticipates: The device according to claim 14, wherein allocating the plurality of instruction blocks in the computing task to the general-purpose processing core and the dedicated acceleration core comprises: allocating the plurality of instruction blocks to the general-purpose processing core and the dedicated acceleration core based on core identifiers ([0046] “…Meanwhile, the computation subtasks tu1, tu2, ... , tu5, such as matrices, vectors and convolution, which may be suitable for execution by the TU computation units, are allocated to the task queue of the TU computation unit; and, the computation subtasks that are not supported by the TU computation unit and the user-defined computation subtasks cu1, cu2, cuN, cuN+1, cuN+2 are allocated to the task queue of the CU computation unit…”, Note: The subtasks are the plurality of instruction blocks allocated to a CU computation unit (general-purpose processing core) and a TU computation unit (dedicated acceleration core) wherein subtasks are allocated to/by respective task queues of computation units which are the core identifiers).
Regarding claim 16, LIAO anticipates: The device according to claim 14, wherein transferring the instruction completion indication to the general-purpose processing core comprises: copying the instruction completion indication by a summarization and distribution component in the general-purpose processing core for sending to the at least one general-purpose processing unit ([0042] “…the task synchronization module can send an event notification to the relevant task queue and/or record the execution state of this computation subtask for subsequent inquiries … an inquiry may be sent to the task synchronization module regarding whether the subtask(s) on which the current subtask depends has been executed. If the subtask(s) has not been executed, the current subtask may need to wait.”, Note: The task synchronization module’s functions include the summarization and distribution component’s functions such as sending event notifications (instruction completion indications) to task queues of different computation units (general-purpose processing cores and dedicated acceleration cores) to notify and allow dependent subtasks to execute).
Regarding claim 18, LIAO anticipates: The device according to claim 14, the operations further comprising: in response to that the at least one general-purpose processing unit completes an instruction block operation, sending an instruction completion indication to a summarization and distribution component ([0042] “…the task synchronization module can send an event notification to the relevant task queue and/or record the execution state of this computation subtask for subsequent inquiries … an inquiry may be sent to the task synchronization module regarding whether the subtask(s) on which the current subtask depends has been executed. If the subtask(s) has not been executed, the current subtask may need to wait.”, Note: The task synchronization module’s functions include the summarization and distribution component’s functions, and event notifications are the instruction completion indications that are sent to computation units (general-purpose processing cores and the dedicated acceleration cores) by the task synchronization module when other computation units are inquired about subtasks completions); and summarizing the instruction completion indication by the summarization and distribution component for sending to the predetermined co-processing unit ([0042] “…the task synchronization module can send an event notification to the relevant task queue and/or record the execution state of this computation subtask for subsequent inquiries … an inquiry may be sent to the task synchronization module regarding whether the subtask(s) on which the current subtask depends has been executed. If the subtask(s) has not been executed, the current subtask may need to wait.”, Note: The task synchronization module’s functions include the summarization and distribution component’s functions, and event notifications are the instruction completion indications that are sent to computation units (general-purpose processing cores and the dedicated acceleration cores) by the task synchronization module).
Allowable Subject Matter
Claims 1-3, 5-7, 9-13, and 22-25 do not have prior art rejections because prior arts, either alone or in combination, does not render obvious, nor anticipate the combination of claimed elements recited in the independent claims. In particular, the prior arts do not disclose the limitations “in response to determining that the instruction completion indication is received, acquiring, by the general-purpose processing core, data from a first on-chip cache inside the dedicated acceleration core through a data path for completing the computing task, the data path being configured to couple the general-purpose processing core to the first on-chip cache, wherein the data path is a bus directly coupling a routing structure component to the first on-chip cache without coupling any other cache, and the routing structure component is only provided in the general-purpose processing core and is coupled directly to the at least one processing unit of the general-purpose processing core” in claim 1; and the limitations “a data path, comprising a bus configured to directly couple the routing structure component to the first on-chip cache so that the at least one general-purpose processing unit can access the first on-chip cache without passing through any other cache, wherein the routing structure component is only provided in the general-purpose processing core” in claim 6.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. In particular, US 20170109214 A1 is cited because it discloses heterogeneous processor cores that execute dependent CPU and GPU tasks. In addition, US 2018/0074727 Al is cited because it discloses processor cores with individual private caches.
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/J.C.T./Examiner, Art Unit 2196
/APRIL Y BLAIR/Supervisory Patent Examiner, Art Unit 2196