DETAILED ACTION
Response to Arguments
Applicant argues that the prior art of does not teach the newly amended claim limitation of wherein said array of probabilistic bit circuits is an array of probabilistic bit cells based on spin-orbit torque devices, each probabilistic bit cell in the array comprises a spin-orbit torque magnetic tunnel junction, the spin-orbit torque magnetic tunnel junction comprises at least one input terminal and at least one ground terminal, a voltage pulse is applied to each input terminal to regulate a current density gradient of a patterning electrode, and the current density gradient is used to determine a magnetization flip probability of the spin-orbit torque magnetic tunnel junction. See pgs., 7-8 of Applicant’s Remarks submitted on 02/10/2026.
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged by Applicant’s arguments submitted on 02/10/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/10/2026 has been entered.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. CN 202110821974, filed on 07/20/2021.
Specification
The disclosure is objected to because of the following informalities:
Para 0035 contains the following grammatical mistake: “However, there does not any application of SOT devices....”
Para 0057 contains the following grammatical mistake: “deviceground”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al., US 11,698,945 B2(“Chou”) in view of Wang, Zhi, et al. "Novel probability flipping method for ising annealing chip using circuit unreliability." Microelectronics Journal 105 (2020)(“Wang”) and in view of Zand, Ramtin, et al. "Low-energy deep belief networks using intrinsic sigmoidal spintronic-based probabilistic neurons." Proceedings of the 2018 Great Lakes Symposium on VLSI. 2018 (“Zand”)
Regarding claim 1, Chou teaches a method for optimizing problem-solving based on probabilistic bit circuits, comprising:
performing a modeling transformation on an objective problem to obtain a corresponding Hamiltonian relationship(Chou, col. 5-6, see also figs. 1A-1D, “The Ising Hamiltonian is given by the following equation:
H
=
-
∑
i
,
j
V
J
i
j
s
i
s
j
-
∑
i
V
h
i
s
i
where V represents the number of nodes in a particular problem set,
J
i
j
represents the weight values interconnecting
the nodes, and s=
[
s
i
…
s
v
]
represents the solution space where
s
i
is a binary spin state…[p]rocesses that can find the lowest energy state of the Ising Hamiltonian can, by extension, be used to solve other CO [that is Combinatorial optimization] problems[performing a modeling transformation on an objective problem to obtain a corresponding Hamiltonian relationship].”);
obtaining a column Hamiltonian of said probabilistic bit circuit based on said Hamiltonian relationship(Chou, col. 9, see also fig. 5A, “FIG. 5A also shows a differential analog multiply and accumulate circuit 510 that applies signals into input nodes ViL and ViR of each oscillator. The coupling coefficient polarity is controlled by the polarity of the output of a
corresponding differential summing amplifier 512…to the nodes ViR and ViL. Each differential summing amplifier 512 is in parallel with a corresponding feedback resistor,
R
F
B
=
1
k
Ω
. Digital potentiometers…R12 through R34 control the individual gains of each of the input oscillator signals… [t]he analog coupling coefficients from the Ising Hamiltonian (
J
i
j
)
are mapped linearly to the ratio of the gains between the various oscillators[obtaining a column Hamiltonian of said probabilistic bit circuit based on said Hamiltonian relationship]. The digital potentiometers employed here have 1024 tap points, with a maximum resistance of 20 k
Ω
.”);
While Chou does teach probabilistic bit circuits Chou does not teach: and performing parallel annealing iterations on multicolumn Hamiltonian based on row-flipping operations to obtain an updated probabilistic bit configuration, so as to achieve optimization of said objective problem, initializing an array of probabilistic bit circuits based on a row-flipping operation on said probabilistic bit circuits to read an initial state of probabilistic bit cell prior to the start of the annealing iteration; determining a configuration corresponding to a column Hamiltonian with the smallest value among parallel column Hamiltonian; and performing a parallel annealing iteration on said probabilistic bit circuit for said configuration.
However, Wang teaches:
and performing parallel annealing iterations on multicolumn Hamiltonian based on row-flipping operations [on said probabilistic bit circuits] to obtain an updated probabilistic bit configuration, so as to achieve optimization of said objective problem(Wang, pgs., 2-4, see also figs. 1 and 6, “Fig. 1 shows the topological structure of Ising annealing chip. It is constructed by the connection of spin nodes. Each spin node includes memory and annealing calculation logic… [a]nnealing calculation logic are used for local search to find a state that makes the local energy lower. The probability flipping can be implemented by intentionally inducing error to the memory that stores spins. Spin nodes that are not interconnected to each other can update their spin states simultaneously. Therefore, half of spin nodes can update their spin states in parallel[and performing parallel annealing iterations on multicolumn Hamiltonian to obtain an updated probabilistic bit configuration,], which speeds up the ground state search process[so as to achieve optimization of said objective problem]… [i]n 8-T SRAM, two access transistors are added to the conventional 6-T SRAM to meet the requirement of new cell ratio by adjusting the size of transistors AL2 and AR2… [a] new word line is also added, which is used exclusively for inducing error to the 8-T SRAM[row-flipping operations].”),1
wherein in said performing parallel annealing iterations on said multicolumn Hamiltonian based on row-flipping operations on said probabilistic bit circuits to obtain an updated probabilistic bit configuration, comprising: initializing an array of probabilistic bit circuits based on a row-flipping operation on said probabilistic bit circuits to read an initial state of probabilistic bit cell prior to the start of the annealing iteration(Wang, pg. 4, see also figs. 1 and 6, “We modeled the relationship between read upset rate and pre-charge bitline voltage in different cell ratios by using HSPICE simulation in 65 nm technology, and developed a simulator to model Ising annealing chip. The probabilistic flipping of 8-T SRAM under different pre-charge voltage in the simulator is derived from the simulation results of HSPICE… [t]herefore, the probability to flip the spin state in Ising annealing chip can be controlled by reading the SRAM cell with different pre-charge voltage. The read upset rate can meet the requirement of probability flipping when the cell ratio is 1 and the precharge bitline voltage is between 1.2 V and 4 V… [t]he initial states of all spins are randomly determined[initializing an array of probabilistic bit circuits based on a row-flipping operation on said probabilistic bit circuits to read an initial state of probabilistic bit cell prior to the start of the annealing iteration].”);
determining a configuration corresponding to a column Hamiltonian with the smallest value among parallel column Hamiltonian; and performing a parallel annealing iteration on said probabilistic bit circuit for said configuration(Wang, pgs. 4-5, see also fig. 8b, “One step of annealing means that all spins have performed local search and probability flipping once. The initial states of all spins are randomly determined. The total spin number is 20 k and the ratio of interaction coefficient r is 0.5 in Fig. 8. The system will fall into local optimum soon if there is no probability flipping, which means next state of the spin is determined only by local search. By intentionally inducing memory error with circuit unreliability, it can help to escape from local optimum for ising annealing chip, which gets lower energy than local search at the end of the ground state search process[determining a configuration corresponding to a column Hamiltonian with the smallest value among parallel column Hamiltonian]” & Wang, pgs., 2-4, see also figs. 1 and 6, “Fig. 1 shows the topological structure of Ising annealing chip. It is constructed by the connection of spin nodes…[t]he probability flipping can be implemented by intentionally inducing error to the memory that stores spins. Spin nodes that are not interconnected to each other can update their spin states simultaneously. Therefore, half of spin nodes can update their spin states in parallel, which speeds up the ground state search process[and performing a parallel annealing iteration on said probabilistic bit circuit for said configuration].”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chou with the teachings of Wang the motivation to do so would be to alter the traditional Ising annealing structure to include probabilistic spins to escape local solutions during simulated annealing(Wang, pg., 1, “In this paper, we propose a novel probability flipping method to realize Ising annealing chip by using circuit unreliability. The spins and coefficients of Ising model are stored in 8-T SRAM and 6-T SRAM respectively. The cell ratio of 8-T SRAM is adjusted to make it susceptible to circuit noise. Memory error is intentionally induced by reading the cell with high pre-charge bitline voltage and read upset rate can be controlled by the value of pre-charge voltage. The novel approach only probabilistically induces memory error to the cells that store spins in the annealing
process but have no influence on the coefficients. Results show that circuit unreliability can help Ising annealing chip escape from local optimum in the ground state search process….”).
While Chou in view of Wang does teach probabilistic bit circuits Chou in view of Wang does not teach: wherein said array of probabilistic bit circuits is an array of probabilistic bit cells based on spin-orbit torque devices, each probabilistic bit cell in the array comprises a spin-orbit torque magnetic tunnel junction, the spin-orbit torque magnetic tunnel junction comprises at least one input terminal and at least one ground terminal, a voltage pulse is applied to each input terminal to regulate a current density gradient of a patterning electrode, and the current density gradient is used to determine a magnetization flip probability of the spin-orbit torque magnetic tunnel junction.
However, Zand teaches:
wherein said array of probabilistic bit circuits is an array of probabilistic bit cells based on spin-orbit torque devices(Zand, pgs., 2-3, see also figs. 1 and 3, “The activation function is achieved by a spintronic building block that has been used in the design of probabilistic spin logic devices... [t]he basic functionality of the p-bit shown in Fig. 1... [t]his device consists of a 3-terminal, spin-Hall driven MTJ... [f]igure 3 shows the structure of the weighted array proposed herein to implement the RBM architecture...as well as the p-bit based activation functions[wherein said array of probabilistic bit circuits is an array of probabilistic bit cells based on spin-orbit torque devices].” ),
each probabilistic bit cell in the array comprises a spin-orbit torque magnetic tunnel junction, the spin-orbit torque magnetic tunnel junction comprises at least one input terminal and at least one ground terminal(Zand, pgs., 2-3, see also figs. 1 and 3, “The activation function is achieved by a spintronic building block that has been used in the design of probabilistic spin logic devices... [t]he basic functionality of the p-bit shown in Fig. 1... [t]his device consists of a 3-terminal, spin-Hall driven MTJ[each probabilistic bit cell in the array comprises a spin-orbit torque magnetic tunnel junction, the spin-orbit torque magnetic tunnel junction comprises at least one input terminal and at least one ground terminal]....”),
a voltage pulse is applied to each input terminal to regulate a current density gradient of a patterning electrode, and the current density gradient is used to determine a magnetization flip probability of the spin-orbit torque magnetic tunnel junction(Zand, pgs., 2-3, see also figs. 1 and 3, “[A] small read voltage
V
R
is applied between the
V
+
and
V
-
terminals through a reference resistance... adjusted to the average conductance of the MTJ... [t]his voltage becomes an input to the CMOS inverters that are biased at the middle point of their DC operating point, creating a stochastic output whose probability can be tuned by the input charge current[a voltage pulse is applied to each input terminal to regulate a current density gradient of a patterning electrode, and the current density gradient is used to determine a magnetization flip probability of the spin-orbit torque magnetic tunnel junction].”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chou in view of Wang with the teachings of Zand the motivation to do so would be to use low energy hardware to implement neural networks such as restricted Boltzmann machines(RBM) to overcome traditional bottle necks found in Von-Neumann based architectures(Zand, pg., 1, “Most RBM and DBN research has focused on software implementations, which provides flexibility, but requires significant execution time and energy due to large matrix multiplications that are relatively inefficient when implemented on standard Von-Neumann architectures due to the memory-processor bandwidth
bottleneck when compared to hardware-based in-memory computing approaches... the work presented herein overcomes many of the preceding challenges by utilizing a novel spintronic p-bit device that leverages intrinsic thermal noise within low energy barrier nanomagnets to provide a natural building block for RBMs within a compact and low-energy package”).
Regarding claim 2, Chou in view of Wang and Zand teaches the method according to the claim 1, wherein in said obtaining said column Hamiltonian of said probabilistic bit circuit based on said Hamiltonian relationship, comprising:
applying said Hamiltonian relationship to a plurality of columns of probabilistic bit cells of said probabilistic bit circuit(Chou, col. 9, see also fig. 5A, “FIG. 5A also shows a differential analog multiply and accumulate circuit 510 that applies signals into input nodes ViL and ViR of each oscillator. The coupling coefficient polarity is controlled by the polarity of the output of a corresponding differential summing amplifier 512…to the nodes ViR and ViL. Each differential summing amplifier 512 is in parallel with a corresponding feedback resistor,
R
F
B
=
1
k
Ω
. Digital potentiometers…R12 through R34 control the individual gains of each of the input oscillator signals… [t]he analog coupling coefficients from the Ising Hamiltonian (
J
i
j
)
are mapped linearly to the ratio of the gains between the various oscillators[applying said Hamiltonian relationship to a plurality of columns of probabilistic bit cells of said probabilistic bit circuit]. The digital potentiometers employed here have 1024 tap points, with a maximum resistance of 20 k
Ω
”),
wherein said column Hamiltonian is a parallel annealed iterative branch of said Hamiltonian relationship(Wang, pgs., 2-4, see also figs. 1 and 6, “Fig. 1 shows the topological structure of Ising annealing chip. It is constructed by the connection of spin nodes. Each spin node includes memory and annealing calculation logic… [a]nnealing calculation logic are used for local search to find a state that makes the local energy lower. The probability flipping can be implemented by intentionally inducing error to the memory that stores spins. Spin nodes that are not interconnected to each other can update their spin states simultaneously. Therefore, half of spin nodes can update their spin states in parallel, which speeds up the ground state search process. The ground state or near-ground state will be found when the annealing temperature T arrives at the end of the search[is a parallel annealed iterative branch of said Hamiltonian relationship].”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chou with the above teachings of Wang for the same rationale stated at Claim 1.
Regarding claim 3, Chou in view of Wang and Zand teaches the method according to the claim 1, wherein in said performing said modeling transformation on said objective problem to obtain said corresponding Hamiltonian relationship, comprising:
transforming said objective problem into an objective mathematical problem through modeling transformation(Chou, col. 5-6, see also figs. 1A-1D, “The Ising Hamiltonian is given by the following equation:
H
=
-
∑
i
,
j
V
J
i
j
s
i
s
j
-
∑
i
V
h
i
s
i
where V represents the number of nodes in a particular problem set,
J
i
j
represents the weight values interconnecting
the nodes, and s=
[
s
i
…
s
v
]
represents the solution space where
s
i
is a binary spin state… [o]ne common benchmark optimization problem, known as the MAX-CUT problem, is defined by finding a bisection of an undirected graph which maximizes the cut set. This problem can be mapped directly to the Ising Hamiltonian above[transforming said objective problem into an objective mathematical problem through modeling transformation], with the solution to the problem being represented by the state s which minimizes H. A particular problem of interest is typically defined by a graph G(V,E), where V represents the number of vertices and E represents the number of edges.”);
mapping nodes of said objective mathematical problem to columns of probabilistic bit cells of said probabilistic bit circuit, and determining said column Hamiltonian based on a predetermined Hamiltonian relationship and a configuration of said columns of probabilistic bit cells(Chou, col. 9, see also fig. 5A, “FIG. 5A also shows a differential analog multiply and accumulate circuit 510 that applies signals into input nodes ViL and ViR of each oscillator. The coupling coefficient polarity is controlled by the polarity of the output of a corresponding differential summing amplifier 512…to the nodes ViR and ViL. Each differential summing amplifier 512 is in parallel with a corresponding feedback resistor,
R
F
B
=
1
k
Ω
. Digital potentiometers…R12 through R34 control the individual gains of each of the input oscillator signals… [t]he analog coupling coefficients from the Ising Hamiltonian (
J
i
j
)
are mapped linearly to the ratio of the gains between the various oscillators[mapping nodes of said objective mathematical problem to columns of probabilistic bit cells of said probabilistic bit circuit, and determining said column Hamiltonian based on a predetermined Hamiltonian relationship and a configuration of said columns of probabilistic bit cells]. The digital potentiometers employed here have 1024 tap points, with a maximum resistance of 20 k
Ω
.”);
and determining interdependencies between said probabilistic bit cells in column of probabilistic bit cells based on said Hamiltonian relationship(Chou, cols. 12-14, see also figs. 5A, 10A, and 12A-D, “FIG. 10A shows a schematic of an experimental setup 1000 for measuring performance of the four-node system 500 in FIG. 5A… FIG. 12E illustrates the case where are all four nodes are fully connected (i.e., all six binary connection weights are set to 1). According to the Ising Hamiltonian, a total of six degenerate states are possible with this weight setting. Because the phases in this experiment are relative to oscillator O1, there are three possible degenerate solutions of the four oscillators: {0°, 0°, 180°, 180° }, {0°, 180°, 180°, 0° },
and {0°, 180°, 0°, 180° }. After 1000 trials, state {0°, 0°, 180°, 180° } is achieved 91.6% of the time and state {0°, 180°, 0°, 180° } is achieved 8.4% of the time[and determining interdependencies between said probabilistic bit cells in column of probabilistic bit cells based on said Hamiltonian relationship]. No incorrect solutions were achieved.” ).
Regarding claim 5, Chou in view of Wang and Zand teaches the method according to claim 1, wherein in said initializing said array of probabilistic bit circuits based on a row-flipping operation on said probabilistic bit circuits, comprising: performing a row flipping operation with 50% probability on said array of probabilistic bit circuits(Wang, pg., 4, see also fig. 1, 6, and 7, “We modeled the relationship between read upset rate and pre-charge bitline voltage in different cell ratios by using HSPICE simulation in 65 nm technology, and developed a simulator to model Ising annealing chip[on said array of probabilistic bit circuits]. The probabilistic flipping of 8-T SRAM under different pre-charge voltage in the simulator is derived from the simulation results of HSPICE. Fig. 7 shows the relationship between read upset rate and pre-charge bitline voltage in different cell ratios.” & Wang, pg., 4, As fig. 7d details:
PNG
media_image1.png
314
497
media_image1.png
Greyscale
The read upset rate which is the row flipping operation is hit 50% of the time when the pre-charge bitline voltage is above 4.5V and the cell ratio is 0.8[performing a row flipping operation with 50% probability].),2
Claims 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al., US 11,698,945 B2(“Chou”) in view of Wang, Zhi, et al. "Novel probability flipping method for ising annealing chip using circuit unreliability." Microelectronics Journal 105 (2020)(“Wang”) and in view of Zand, Ramtin, et al. "Low-energy deep belief networks using intrinsic sigmoidal spintronic-based probabilistic neurons." Proceedings of the 2018 Great Lakes Symposium on VLSI. 2018 (“Zand”) and further in view of Borders, William A., et al. "Integer factorization using stochastic magnetic tunnel junctions." Nature 573.7774 (2019)(“Borders”)
Regarding claim 6, Chou in view of Wang and Zand teaches the method according to claim 1, but does not teach: wherein in said performing said parallel annealing iteration on said probabilistic bit circuit for said configuration, comprising: determining a row writing probability corresponding to said configuration based on an interdependence between said configuration corresponding to the column Hamiltonian with the smallest value and a column of said probabilistic bit cell; and sequentially performing, based on the row-flipping operation on said probabilistic bit circuit, a write operation to rows of probabilistic bit cells of said probabilistic bit circuit according to said row write probability, so as to iterate over a configuration of corresponding columns of probabilistic bit cells.
However, Borders teaches:
determining a row writing probability corresponding to said configuration based on an interdependence between said configuration corresponding to the column Hamiltonian with the smallest value and a column of said probabilistic bit cell(Borders, pg., 395, “The mapped classical system is simulated by first obtaining the current vector
I
i
for the ith p-bit in the system[with the smallest value and a column of said probabilistic bit cell] from the classical Hamiltonian in equation (9) by
I
i
=
-
∂
H
c
∂
m
i
[determining a row writing probability corresponding to said configuration based on an interdependence between said configuration corresponding to the column Hamiltonian].”);
and sequentially performing, based on the row-flipping operation on said probabilistic bit circuit, a write operation to rows of probabilistic bit cells of said probabilistic bit circuit according to said row write probability, so as to iterate over a configuration of corresponding columns of probabilistic bit cells(Borders, pg., 395-396, “the current vector
I
i
for the ith p-bit in the system from the classical Hamiltonian in equation (9) by
I
i
=
-
∂
H
c
∂
m
i
[according to said row write probability]. The same inverse temperature, β = 25 is chosen with r = 45 replicas and all p-bits are sequentially updated according to
m
i
=
s
g
n
[
tanh
β
I
i
-
r
a
n
d
(
-
1
,
1
)
]
where rand is a number that is uniformly distributed between -1 and +1… N = 2
×
10
6
time steps are chosen and a probability of each state is obtained using time averaging of the state of the system for the entire duration N of the simulation over all replicas r[and sequentially performing, based on the row-flipping operation on said probabilistic bit circuit, a write operation to rows of probabilistic bit cells of said probabilistic bit circuit so as to iterate over a configuration of corresponding columns of probabilistic bit cells].”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chou in view of Wang and Zand with the teachings of Borders the motivation to do so would be to use probabilistic computing to implement algorithms based on adiabatic quantum computing such as integer factorization(Borders, pg., 390, “The field of adiabatic quantum computing9 (AQC) solves complex optimization problems by constructing networks of qubits in which the inter-qubit interactions are engineered to make the overall energy E reflect the cost function for the problem. One such algorithm frames integer factorization of a given number F as an optimization problem… [t]his algorithm does not require coherence, but needs auxiliary bits to represent many-body interactions when implemented using AQC. In probabilistic computing, many-body interactions are implemented electrically, removing the need for extra components.”).
Regarding claim 7, Chou in view of Wang, Zand, and Borders teaches the method according to claim 6, further comprising:
reading an updated state of probabilistic bit cell in said array of the probabilistic bit circuits(Borders, pg., 391, see also figs. 3a and Extended data fig. 2, “Experimentally we connect eight p-bits following a general architecture …[of] (Fig. 3a). A microcontroller reads the output voltage of each p-bit and is programmed to calculate the inputs
I
i
for a given cost function E[reading an updated state of probabilistic bit cell in said array of the probabilistic bit circuits].”)
after each of said parallel annealing iterations(Wang, pgs., 2-4, see also figs. 1 and 6, “Fig. 1 shows the topological structure of Ising annealing chip. It is constructed by the connection of spin nodes. Each spin node includes memory and annealing calculation logic… [a]nnealing calculation logic are used for local search to find a state that makes the local energy lower[after each of said parallel annealing iterations].”);
and determining an updated column Hamiltonian based on said updated state of probabilistic bit cell(Borders, pg., 391, see also figs. 3a and Extended data fig. 2, “Together, the microcontroller and DAC function as the synaptic weight logic that determines
I
i
…and feeding back analogue inputs[and determining an updated column Hamiltonian based on said updated state of probabilistic bit cell]”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chou with the above teachings of Wang for the same rationale stated at Claim 1.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chou in view of Wang and Zand and with the above teaching of Borders for the same rational stated at claim 6.
Regarding claim 8, Chou in view of Wang, Zand and Borders teaches the method according to the claim 7, wherein performing a parallel annealing iteration on said column Hamiltonian to determine probabilistic bit configuration, comprising:
determining a probabilistic bit configuration corresponding to said updated column Hamiltonian when a minimum value of said updated column Hamiltonian is either a fixed value or fluctuant in a very small range; and performing parallel annealing iterations on said updated column Hamiltonian when the minimum value of said updated column Hamiltonian is neither a fixed value nor fluctuant in a very small range(Wang, pgs., 4-5, see also fig. 8(b), “Fig. 8 shows the energy history of the ground state search process by using different probability flipping methods… [o]ne step of annealing means that all spins have performed local search and probability flipping once. The initial states of all spins are randomly determined. The total spin number is 20 k… [b]y intentionally inducing memory error with circuit unreliability, it can help to escape from local optimum for ising annealing chip, which gets lower energy than local search at the end of the ground state search process… presented relative energy as a metric to compare the quality of the solution for different problems. It can be defined by:
R
S
=
E
(
S
)
E
(
S
l
s
)
where S is the final spin state of the system derived from different
methods, and
S
l
s
is the final spin state by only using local search. The solution is better if the relative energy is higher” & Wang, pgs., 4-5, As fig. 8(b) details:
PNG
media_image2.png
288
440
media_image2.png
Greyscale
From steps 0-8000, the minimum value of said updated column Hamiltonian is neither a fixed value nor fluctuant in a very small range since the energy ranges from above -10000 to -20000, it is not until after steps 8000 that said updated column Hamiltonian is either a fixed value or fluctuant in a very small range of -24162[determining a probabilistic bit configuration corresponding to said updated column Hamiltonian when a minimum value of said updated column Hamiltonian is either a fixed value or fluctuant in a very small range; and performing parallel annealing iterations on said updated column Hamiltonian when the minimum value of said updated column Hamiltonian is neither a fixed value nor fluctuant in a very small range]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chou with the above teachings of Wang for the same rationale stated at Claim 1.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al., US 11,698,945 B2(“Chou”) in view of Wang, Zhi, et al. "Novel probability flipping method for Ising annealing chip using circuit unreliability." Microelectronics Journal 105 (2020)(“Wang”) and in view of Zand, Ramtin, et al. "Low-energy deep belief networks using intrinsic sigmoidal spintronic-based probabilistic neurons." Proceedings of the 2018 Great Lakes Symposium on VLSI. 2018 (“Zand”) and in view of Borders, William A., et al. "Integer factorization using stochastic magnetic tunnel junctions." Nature 573.7774 (2019)(“Borders”) and further in view of Konwar, Shruti, et al. "Adiabatic logic based low power multiplexer and demultiplexer." 2014 International Conference on Computer Communication and Informatics. IEEE, 2014(“Konwar”)
Regarding claim 9, Chou in view of Wang and Zand teach a system for optimizing problem-solving based on probabilistic bit circuits, which is applied to implement the method according to claim 1, comprising:
probabilistic bit circuits for parallel probabilistic operations(Chou, col. 9, see also fig. 5A, “FIG. 5A also shows a differential analog multiply and accumulate circuit 510 that applies signals into input nodes ViL and ViR of each oscillator. The coupling coefficient polarity is controlled by the polarity of the output of a corresponding differential summing amplifier 512…to the nodes ViR and ViL. Each differential summing amplifier 512 is in parallel with a corresponding feedback resistor,
R
F
B
=
1
k
Ω
[probabilistic bit circuits for parallel probabilistic operations]. Digital potentiometers…R12 through R34 control the individual gains of each of the input oscillator signals….”);
While Chou in view of Wang and Zand teach probabilistic bit circuits Chou in view of Wang do not teach: an analog-to-digital converter for converting a plurality of signals from the output of said multiplexer to digital signals; a processor for processing the digital signal converted by said analog-to-digital converter to determine a column Hamiltonian, and for determining a flipping probability value of said row probability bits corresponding to said column Hamiltonian;
a digital-to-analog converter for converting the flipping probability value obtained by said processor into an analog signal; a multiplexer for outputting a plurality of signals read from said probabilistic bit circuits; and a demultiplexer for following up the analog signal converted by said digital-to-analog converter for probabilistic bit reading and writing operations.
However, Borders teaches:
an analog-to-digital converter for converting a plurality of signals [from the output of said multiplexer] to digital signals; a processor for processing the digital signal converted by said analog-to-digital converter to determine a column Hamiltonian, and for determining a flipping probability value of said row probability bits corresponding to said column Hamiltonian; a digital-to-analog converter for converting the flipping probability value obtained by said processor into an analog signal (Borders, pg., 394, see also Extended Data Fig. 2, “We have constructed our p-circuits following the general architecture described previously which is shown in Extended Data Fig. 2. An Arduino microcontroller (Mega 2560) is used to read the output voltages of each p-bit as binary inputs and is programmed to implement the synaptic weights.3 [an analog-to-digital converter for converting a plurality of signals to digital signals; a processor for processing the digital signal converted by said analog-to-digital converter to determine a column Hamiltonian, and for determining a flipping probability value of said row probability bits corresponding to said column Hamiltonian]These are then converted into analogue voltages using a DAC (PMOD DA4) that has eight channels, each with 12-bit resolution. The DAC also has an internal 2.5 V reference allowing a resolution of 2.5/4096 ≈ 6.1 mV[a digital-to-analog converter for converting the flipping probability value obtained by said processor into an analog signal].”);4
[a multiplexer for outputting a plurality of signals]read from said probabilistic bit circuits(Borders, pg., 391, see also Fig. 3(a), “Experimentally we connect eight p-bits following a general architecture presented previously…(Fig. 3a). A microcontroller reads the output voltage of each p-bit[read from said probabilistic bit circuits]….”);5
[and a demultiplexer for following up the analog signal] converted by said digital-to-analog converter for probabilistic bit reading and writing operations(Borders, pg., 391, see also Fig. 3(a), “The result is converted into analogue voltages using a digital-to-analogue converter (DAC). Together, the microcontroller and DAC function as the synaptic weight logic that determines
I
i
, reading in digital outputs from the p-bits and feeding back analogue inputs[converted by said digital-to-analog converter for probabilistic bit reading and writing operations]….”).6
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chou in view of Wang and Zand with the teachings of Borders the motivation to do so would be to use probabilistic computing to implement algorithms based on adiabatic quantum computing such as integer factorization(Borders, pg., 390, “The field of adiabatic quantum computing9 (AQC) solves complex optimization problems by constructing networks of qubits in which the inter-qubit interactions are engineered to make the overall energy E reflect the cost function for the problem. One such algorithm frames integer factorization of a given number F as an optimization problem… [t]his algorithm does not require coherence, but needs auxiliary bits to represent many-body interactions when implemented using AQC. In probabilistic computing, many-body interactions are implemented electrically, removing the need for extra components.”).
While Chou in view of Wang, Zand and Borders teach read from said probabilistic bit circuits, converted by said digital-to-analog converter for probabilistic bit reading and writing operations, and an analog-to-digital converter for converting to digital signals, Chou in view of Wang, Zand and Borders do not teach:
a multiplexer for outputting a plurality of signals; and a demultiplexer for following up the analog signal; a plurality of signals from the output of said multiplexer
However, Konwar teaches:
a multiplexer for outputting a plurality of signals [read from said probabilistic bit circuits](Konwar, pg., 2, see also figs. 5 and 6, “A multiplexer is a special type of combinational circuit which selects only one of ‘n’ given data inputs and routes it to the output…[t]he block diagram of 8:1 multiplexer is shown in fig. 5.”);7
and a demultiplexer for following up the analog signal [converted by said digital-to-analog converter for probabilistic bit reading and writing operations]( Konwar, pg., 2, see also figs. 5 and 6, “The demultiplexer performs the reverse operation of the multiplexer i.e. it receives one input and distributes it over several outputs… [t]he block diagram of a 1:8 demultiplexer is as given in fig. 6.”).8
[an analog-to-digital converter for converting] a plurality of signals from the output of said multiplexer [to digital signals]( Konwar, pg., 2, see also figs. 5 and 6, “A multiplexer is a special type of combinational circuit which selects only one of ‘n’ given data inputs and routes it to the output…[t]he block diagram of 8:1 multiplexer is shown in fig. 5.”).9
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chou in view of Wang, Zand and Borders with the teachings of Konwar the motivation to do so would be to use logic gates based on the adiabatic approach to save power in digital circuits(Konwar, pg., 1, “Due to the shrinking size of systems in today’s era of technology, researchers in the field of low power microelectronics have become responsible of handling low power concerns along with the diminishing size… [t]he adiabatic logic is the latest approach for power saving in digital circuits. They are different from static CMOS in that they use an oscillating power-supply, the so called
power-clock. Though CMOS technology provides circuits with very low static power dissipation, during the switching operation currents are generated, due to the discharge of load capacitances, that cause a power dissipation increasing with the clock frequency. The
adiabatic technique prevents such losses: the charge does not flow from the supply voltage to the load capacitance and then to ground, but it flows back to a trapezoidal or sinusoidal supply voltage, the power-clock, and the power can be reused….”).
Regarding claim 10, Chou in view of Wang, Zand, Borders and further in view of Konwar teaches the system according to claim 9, wherein said probabilistic bit circuit comprises a plurality of probabilistic bit cells(Borders, pg., 391, see also Fig. 3(a), “Experimentally we connect eight p-bits following a general architecture presented previously…(Fig. 3a)[ a plurality of probabilistic bit cells].”) and a plurality of control lines(Borders, pg., 391, see also Fig. 2, “The output voltage for the ith p-bit,
V
O
U
T
,
i
from this composite unit can be written in terms of the input voltage
V
I
N
,
i
[and a plurality of control lines]….”), and each of said plurality of probabilistic bit cells comprising: a spin-orbit torque magnetic tunnel junction for magnetization flipping(Borders, pg., 391, see also figs. 2a and 3a, “To form the building block for stochastic neural networks, we connect the stochastic MTJs[a spin-orbit torque magnetic tunnel junction for magnetization flipping] with standard n-type metal–oxide–semiconductor (NMOS) transistors to obtain a three-terminal p-bit (Fig. 2a)) when said plurality of control lines are applied with different voltages or currents(Borders, pg., 391, see also Fig. 2, “Figure 2b shows the time-averaged output voltage as the input voltage is swept from 1.5 V to 2.4 V, where each point is averaged over 700 ms with a fixed input voltage. Figure 2c shows the time-varying output voltage for specific input voltages, displaying stochastic behaviour centred at 1.95 V, but becoming deterministic as the input changes by about
±
75 mV, a consequence of spin-transfer torque[when said plurality of control lines are applied with different voltages or currents].”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chou in view of Wang and Zand with the above teachings of Borders for the same rationale stated at claim 9.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Camsari, et al. "From charge to spin and spin to charge: Stochastic magnets for probabilistic switching." Proceedings of the IEEE 108.8. (2020)(details various p-bit architectures for p-computing)
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/Adam C Standke/
Primary Examiner
Art Unit 2129
1 Examiner Remarks: The claim limitations that are not in bold and contained within square brackets (i.e. [ ]) are claim limitations taught by the prior art of Chou.
2 It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chou with the above teachings of Wang for the same rationale stated at Claim 1.
3 As detailed by the prior art of Spiceman. (2020, December 30). Arduino MEGA 2560 R3 specifications/functions/spiceman. (https://web.archive.org/web/20210119142838/https://spiceman.net/arduino-mega-2560/) the Arduino Mega 2560 includes an analog to digital convertor (ADC) that is able to take analog input on pins A0-A15 and convert it into a digital signal representing 10 bits.
4 Examiner Remarks: The claim limitations that are not in bold and contained within square brackets (i.e. [ ]) are claim limitations that are not taught by the prior art of Chou in view of Wang and in view of Borders
5 Examiner Remarks: The claim limitations that are not in bold and contained within square brackets (i.e. [ ]) are claim limitations that are not taught by the prior art of Chou in view of Wang and in view of Borders
6 Examiner Remarks: The claim limitations that are not in bold and contained within square brackets (i.e. [ ]) are claim limitations that are not taught by the prior art of Chou in view of Wang and in view of Borders
7 Examiner Remarks: The claim limitations that are not in bold and contained within square brackets (i.e. [ ]) are claim limitations that are taught by the prior art of Chou in view of Wang and in view of Borders
8 Examiner Remarks: The claim limitations that are not in bold and contained within square brackets (i.e. [ ]) are claim limitations that are taught by the prior art of Chou in view of Wang and in view of Borders
9 Examiner Remarks: The claim limitations that are not in bold and contained within square brackets (i.e. [ ]) are claim limitations that are taught by the prior art of Chou in view of Wang and in view of Borders