DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html).
Status of claim(s) to be treated in this office action:
Independent: 14 and 20.
Pending: 14-21, 24 and 25.
Canceled: 1-13, 22 and 23.
Response to Arguments
Applicant's arguments with respect to claims 14-19 have been considered but are moot in view of the new ground(s) of rejection.
Applicant’s arguments/remarks, see page(s) 4-7 filed 10/24/2025, with respect to claim(s) 20, 21, 24 and 25 have been fully considered and are persuasive. The rejection of claim(s) 20, 21, 24 and 25 has been withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 14-17 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lai et al., US Patent 10,636,812 B1; in view of Lu et al., US Patent 9853043 B2.
Re: Independent Claim 14, Lai discloses a substrate (602, fig. 6);
a memory region (150, fig. 2) over the substrate (602, fig. 6) and comprising a plurality of levels of memory cells (multi-level cell from 121-124, fig. 1A); and
an access region (160, fig. 2) over the substrate (602, fig. 6) and comprising:
a plurality of word lines (WLs, fig. 1A) associated with accessing the plurality of levels of memory cells (multi-level cell from 121-124, fig. 1A);
a conductive pillar (171-174, 121a,b,c-124a,b,c, fig. 1A) for coupling a first word line (121, fig. 1A) at a first level (level at 121, fig. 1A) of memory cells (multi-level cell from 121-124, fig. 1A) with decoder circuitry (262, fig. 2) in association with accessing a set of memory cells (multi-level cell from 121-124, fig. 1A) at the first level (level at 121, fig. 1A), wherein the conductive pillar (171-174, 121a,b,c-124a,b,c, fig. 1A) is located in a channel region (121b-124b in region 160, fig. 1A and 155, fig. 1c) between word lines (WLs, fig. 1A) at levels over the first level (level at 121, fig. 1A) and for providing access to the first word line (121, fig. 1A), and
wherein the conductive pillar (171-174, 121a,b,c-124a,b,c, fig. 1A) extends, in a first direction orthogonal (upward or downward to the substrate 602, fig. 6) to the substrate (602, fig. 6), from the first word line (121, fig. 1A) through a fill material (1120, fig. 11) in the channel region (121b-124b in region 160, fig. 1A and 155, fig. 1c) over the first word line (121, fig. 1A); and an oxide material (see annotated figure 20 below) in contact with the first word line (121, fig. 1A) and a dielectric material (604, fig. 6) located between the first level (level at 121, fig. 1A) and a second level (level of 122, fig. 1A) of memory cells (multi-level cell from 121-124, fig. 1A) over the first level (level at 121, fig. 1A).
Lai is silent regarding: wherein the oxide material is different from the dielectric material.
Lu discloses wherein the oxide material (165, fig. 26B;column 11, lines 15-17) is different from the dielectric material (132, fig. 26B; column 6, lines 28-43).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a different oxide material (common silicon oxide material from the dielectric material for example high-k dielectric material since high-k dielectric material provide improved characteristics with respect to reducing leakage currents even when an equivalent oxide thickness (EOT) is less than a critical thickness of a silicon oxide layer. The EOT of a high-k dielectric layer means the thickness of a silicon oxide layer that would provide the same capacitance. Thus, use of a high-k dielectric can provide a capacitance equivalent to that provided using a physically thinner silicon oxide layer while providing improved leakage current characteristics.
Re: Claim 15, Lai and Lu disclose(s) all the limitations of claim 14 on which this claim depends. Lai further discloses: wherein the access region (160, fig. 2) further comprises:
a metal contact (171, fig. 1A) coupled with the first word line (121, fig. 1A) and the conductive pillar (171-174, 121a,b,c-124a,b,c, fig. 1A), wherein the oxide material (see annotated figure 20 below) is in contact with the metal contact (171, fig. 1A), the conductive pillar (171-174, 121a,b,c-124a,b,c, fig. 1A), or any combination thereof.
Re: Claim 16, Lai and Lu disclose(s) all the limitations of claim 14 on which this claim depends. Lai further discloses: wherein a portion of the fill material (1120, fig. 11) is located between the oxide material (see annotated figure 20 below) and the conductive pillar (171-174, 121a,b,c-124a,b,c, fig. 1A) in a second direction parallel to the substrate (602, fig. 6).
Re: Claim 17, Lai and Lu disclose(s) all the limitations of claim 14 on which this claim depends. Lai further discloses: a second conductive pillar (122a,b,c, fig. 1A) for coupling a second word line (122, fig. 1A) at a third level (level of 112, fig. 1A) of memory cells (multi-level cell from 121-124, fig. 1A) with the decoder circuitry (262, fig. 2), wherein the second conductive pillar (122a,b,c, fig. 1A) is located in the channel region (121b-124b in region 160, fig. 1A and 155, fig. 1c) and extends from the second word line (122, fig. 1A) through the fill material (1120, fig. 11).
Claim(s) 18-19 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lai et al., US Patent 10,636,812 B1 in view of Lu et al., US Patent 9853043 B2; further in view of Lin et al., US patent 11,729,997 B2.
Re: Claim 18, Lai and Lu discloses all the limitations of claim 14 on which this claim depends. Lai is silent regarding: the fill material 1120 including a second oxide material different from the oxide material (see annotated figure 20 below).
Lin discloses in figure 16 oxide material 1601 different (column 25, lines 57-66) than the fill dielectric 803 surrounding a conductive via 807.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a different oxide material to protect the conductive via since this can prevents write disturb issues during write operations to a targeted resistor of the memory cell. For example, during write operations to a targeted resistor of the memory cell, leakage currents are prevented from passing through the bit line of the non-targeted resistor of the memory cell due to the diode that is electrically connected to the non-targeted resistor (column 2, lines 53-59).
Re: Claim 19, Lai and Lu discloses all the limitations of claim 14 on which this claim depends. Lai is silent regarding: the fill material is associated with a first etch rate, a first density, or any combination thereof, and the oxide material (see annotated figure 20 below) is associated with a second etch rate different from the first etch rate, a second density different from the first density, or any combination thereof.
Lin discloses in figure 16 oxide material 1601 different (column 25, lines 57-66) than the fill dielectric 803 surrounding a conductive via 807.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a different oxide material to protect the conductive via and different material would be obvious to have different etch rate and since this can prevents write disturb issues during write operations to a targeted resistor of the memory cell. For example, during write operations to a targeted resistor of the memory cell, leakage currents are prevented from passing through the bit line of the non-targeted resistor of the memory cell due to the diode that is electrically connected to the non-targeted resistor (column 2, lines 53-59). Furthermore, according to the MPEP, Section 2113, "Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process”. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
Below is an annotated of Lai et al., US Patent 10,636,812 B1 figure 20.
PNG
media_image1.png
514
650
media_image1.png
Greyscale
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Knoefler et al., US PG pub. 20090309152 A1”) discloses an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.
* (“Karda US PG pub. 20210384354 A1”) discloses a transistor comprises a lower contact structure, a channel structure, a dielectric fill structure, and an upper contact structure. The lower contact structure comprises a first oxide semiconductive material. The channel structure contacts the lower contact structure and comprises a second oxide semiconductive material having a smaller atomic concentration of one or more metals than the first oxide semiconductive material. The dielectric fill structure contacts an inner side surface of the channel structure and has a recessed upper surface relative to the channel structure. The upper contact structure comprises a third oxide semiconductive material having a greater atomic concentration of the one or more metals than the channel structure. The upper contact structure comprises a first portion contacting the upper surface of the dielectric fill structure and the inner side surface of the channel structure, and a second portion contacting the upper surface of the channel structure.
Allowable Subject Matter
Claim(s) 20, 21, 24 and 25 are allowed.
The following is an examiner’s statement of reasons for allowance:
The closest prior art to the present invention is/are Lai et al., US Patent 10,636,812 B1 in view of Lu et al., US Patent 9853043 B2; further in view of Lin et al., US patent 11,729,997 B2.
Lai discloses a memory device, which can be configured as a 3D NAND flash memory, includes a plurality of stacks of conductive strips. The plurality of stacks of conductive strips includes a plurality of intermediate levels of conductive strips configured as word lines and an upper level of conductive strips configured as string select lines. A plurality of first patterned conductors is disposed above the plurality of stacks of conductive strips. A plurality of linking elements connects conductive strips in respective intermediate levels in the plurality of intermediate levels of conductive strips to first patterned conductors in the plurality of first patterned conductors. The linking elements in the plurality of linking elements include switches responsive to signals in conductive strips in the upper level of conductive strips.
Lu discloses a three-dimensional memory device, includes forming a lower stack structure of insulating and first sacrificial material layers over a substrate, forming first memory openings through the lower stack structure and filling the first memory openings with a sacrificial fill material, replacing the first sacrificial material layers with first electrically conductive layers, forming an upper stack structure of insulating and second sacrificial material layers over the lower stack structure after replacing the first sacrificial material layers, forming second memory openings through the upper stack structure in areas overlying the first memory openings, replacing the second sacrificial material layers with second electrically conductive layers, removing the sacrificial fill material from the first memory openings underneath the second memory openings to form inter-stack memory openings after replacing the second sacrificial material layers, and forming memory stack structures within the inter-stack memory openings.
Lin discloses a memory devices include a resistive memory array including a first resistive memory cell, a staircase contact structure adjacent the resistive memory array, and an inter-metal dielectric layer over the staircase contact structure. The memory devices further include a first diode and a second diode over the inter-metal dielectric layer. The memory devices further include a first conductive via electrically coupling the first diode to a first resistor of the first resistive memory cell and a second conductive via electrically coupling the second diode to a second resistor of the first resistive memory cell.
Re: Independent Claim 20 (and dependent claim(s) 21, 24 and 25), there is no teaching or suggestion in the prior art of record to provide: a plurality of word lines over the substrate and separated from each other by respective dielectric layers; a contact coupled with a first word line of the plurality of word lines; a conductive pillar coupled with the contact and for coupling the first word line with decoder circuitry, the conductive pillar extending through a first oxide material located over the first word line; and a second oxide material over the first word line and adjacent to a first dielectric layer that is over the first word line, wherein the second oxide material is in contact with the first word line and the first dielectric layer.
Missing elements in the closest art gives rise to the innovation in the current invention.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on 9-5PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at https://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached on (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898