DETAILED ACTION
Receipt of Applicant’s amendment filed 02/02/2026.
Claims 1, 4, 7, 9, 10, 13, 15-16, and 18 have been amended.
Claims 3, 5-6, 12 and 14 have been canceled.
Claims 1-2, 4, 7-11, 13 and 15-19 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Notes
Examiner cites particular columns, paragraphs, figures and line numbers in the
references as applied to the claims below for the convenience of the applicant. Although
the specified citations are representative of the teachings in the art and are applied to
the specific limitations within the individual claim, other passages and figures may apply
as well. Examiner may also include cited interpretations encompassed within parenthesis, e.g. (Examiner' s interpretation), for clarity. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. The entire reference is considered to provide disclosure relating to the claimed invention. The claims & only the claims form the metes & bounds of the invention. Office personnel are to give the claims their broadest reasonable interpretation in light of the supporting disclosure. Unclaimed limitations appearing in the specification are not read into the claim. Prior art was referenced using terminology familiar to one of ordinary skill in the art. Such an approach is broad in concept and can be either explicit or implicit in meaning. Examiner's Notes are provided with the cited references to assist the applicant to better understand how the examiner interprets the applied prior art. Such comments are entirely consistent with the intent & spirit of compact prosecution.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Claim Rejections under 35 U.S.C. § 112(d):
Acknowledgement is made of canceled claim 6. Previous rejection to claim 6 is withdrawn.
Claim Rejections under 35 U.S.C. § 101:
Acknowledgement is made of amended independent claim 1 to incorporate previous claims 3 and 5. Acknowledgement is made of amended independent claim 10 to incorporate previous claims 12 and 14. Applicants arguments have been fully considered and are persuasive. Rejections to claims 1, 2, 10, 11 and associated dependent claims are withdrawn.
Claim Rejections under 35 U.S.C. § 103:
Acknowledgement is made of amended independent claims. Applicant' s arguments filed 02/02/2026 have been fully considered but they are not persuasive.
Previous rejections to claims are maintained.
Applicant argues [Pg.2 Ln.19-20] Brozek (secondary reference) doesn’t disclose or suggest “wherein N is greater than or equal to 10 and less than or equal to 20”. The examiner respectfully disagrees. Brozek discloses testing/simulating memory cells using several different array sizes (see Brozek Pg.7 Fig.11), e.g. 5x5, 10x10, 15x15, etc.. However, each array is not tested/simulated all at once, as Applicant argues. Instead, individual cells within the arrays can be tested individually - Brozek discloses “Since the resistance of each cell can be tested independently, the array can provide valid, bit level information about cell functionality” [Pg.4 Col.1 Ln.4-6]. Additionally, specific word lines (WL) or bit lines (BL) within each array can be selected, as Brozek discloses in Fig.5 (see below).
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Fig.5 shows an 8x8 array where WL3 has been selected, thus 8 memory cells (i.e. N) have been selected. However, selecting a WL within a 10x10 array or 15x15 or 20x20, as Brozek discloses, results in N=10 or 15 or 20, respectively. Additionally, Brozek discloses array size “can further be optimized to provide the best trade-off between the statistical sample size of tested bits and the test speed and resistance measurement error.” [Pg.8 Col.1 P.4]. Therefore, Applicant’s argument is not persuasive.
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, Park (primary reference) is analogous to the claimed invention since both patents address memory cell repair verification, involving detection of defective memory cells, use of redundant cells for repair, and verification of repair success. Both involve address manipulation and data writing/reading to confirm repair. Each includes apparatus/system claims (test apparatus or MBIST circuit) and methods for executing the repair and verification process. Both aim to improve memory reliability and yield by automating the detection and repair of faulty memory cells. Brozek (secondary reference) is analogous art as it relates to effective memory cell development and testing, as does the claimed invention (see Spec. Pg.1 Ln.22), with the goal of reducing turn-around-time and development costs. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Brozek’s disclosed memory cell array with Park’s memory cell testing method in order for a “fast and inexpensive approach for process optimization and yield improvement of new emerging memories” Brozek [Pg.8 IV.].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham V. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
Claims 1-2, 4, 7-11, 13, and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. US Pub. No. 20220113889 A1 (hereinafter referred to as “Park”) in view of Brożek, Tomasz, and Dennis Ciplickas. "Design and Measurement Requirements for Short Flow Test Arrays to Characterize Emerging Memories." IEEE Journal of the Electron Devices Society 7 (2019): 1248-1257 (hereinafter referred to as “Brozek”).
Regarding claim 1, Park discloses A method of circuit simulation, wherein a circuit comprises an array region circuit (“The memory core 200 may include first to fourth bank arrays [...] correspond to the memory cell array [...] row decoders [...] column decoders [...] sense amps” Park [P.0072]. These components are interpreted as an “array region circuit” due to Applicant’s disclosure [Spec. Pg.4 Ln.15-17]) and a peripheral region circuit (“The architecture requirements of the memory PHY includes DC parameters including voltage levels and rise times and fall times of input/output signals provided to signal lines connected to the memory PHY and AC parameters including a memory access time, and setup times and hold times for the input/output signals.” Park [P.0022]. This is interpreted as “peripheral region circuit” per Applicant’s disclosure [Spec. Pg.4 Ln.14-15]), and the method comprises: (“there is provided a method of testing a memory device including a plurality of memory banks and a memory built-in self-test (MBIST) circuit, wherein the plurality of memory banks include a plurality of memory cells” Park [P.0008])
initializing a simulation environment, comprising selecting N memory cells from a memory array as to-be-verified cells, (“performing the DDR (double data rate) test on one bank selected from among the plurality of memory banks; based on detecting a defective cell (i.e. selection of N memory cells) as a result of the DDR test or the PBT test, performing a repair operation for repairing the defective cell with a redundancy cell through the MBIST circuit; and performing a re-test for verifying the repair operation through the MBIST circuit, wherein the re-test is performed on one or more memory cells including the defective cell among the plurality of memory cells.” Park [P.0008]. Memory banks are interpreted to include memory cell array because “The MCA 122 may include a plurality of memory banks, and the memory banks may each include a normal cell array and a redundancy cell array.” Park [P.0065])
and performing repair verification on each to-be-verified cell (“based on detecting a defective cell as a result of the DDR test or the PBT test, performing a repair operation for repairing the defective cell with a redundancy cell through the MBIST circuit; and performing a re-test for verifying the repair operation through the MBIST circuit, wherein the re-test is performed on one or more memory cells including the defective cell among the plurality of memory cells” Park [P.0008]), ;
simulating the circuit; (“and performing a re-test for verifying the repair operation through the MBIST circuit, wherein the re-test (i.e. simulate) is performed on one or more memory cells including the defective cell among the plurality of memory cells.” Park [P.0008])
and outputting a circuit simulation result file, the circuit simulation result file comprising a result of repair verification for each to-be-verified cell. (“In operation S640, the MBIST circuit 126 may output DDR test results and/or PBT test results for the memory device 120 to the memory controller 110 and terminate the MBIST. The memory controller 110 may perform a memory allocation operation by referring to test results output from the MBIST circuit 126. Here, the test results may include only information regarding the fail cell address (i.e. to-be-verified cell) F/A.” Park [P.0114]. See S640 in Fig.6 below.)
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wherein the performing repair verification on each to-be-verified cell comprises: performing repair replacement on the to-be-verified cell by using a repair circuit; (“performing a repair operation for repairing the defective cell (i.e. to-be-verified cell) with a redundancy cell through the MBIST circuit (i.e. repair circuit)” Park [P.0008]. The MBIST circuit is interpreted as a repair circuit because “there is provided a memory built-in self-test (MBIST) circuit for testing a memory device including a plurality of memory banks. The MBIST circuit includes: a test pattern generating (TPG) circuit configured to generate a plurality of test patterns, the plurality of test patterns including a double data rate (DDR) test pattern and a parallel bit test (PBT) test pattern; a built-in redundancy analysis (BIRA) circuit configured to perform a repair operation for replacing a defective cell detected in a PBT test or a DDR test on the memory device with a redundancy cell, and store information regarding a fail cell address and a redundancy cell address in an address storage table (AST); and a built-in self-repair (BISR) control circuit configured to output BISR signals to perform the repair operation in response to a fail flag signal indicating that the defective cell has been detected, wherein the TPG circuit is further configured to perform a re-test on one or more memory cells including the defective cell among a plurality of memory cells to verify the repair operation through the BIRA circuit.” Park [P.0023])
writing first data into an address corresponding to the to-be-verified cell after repair replacement; (“In the PBT (parallel bit) test, after writing a PBT pattern (i.e. first data), that is, the same data (e.g., “0” or “1”), to the memory cells MCs of the first to fourth banks BANK1 to BANK4” Park [P.0097])
and reading the address corresponding to the to-be-verified cell after repair replacement, (“The control circuit 124 may output the fail flag signal FS indicating that a defective cell has been detected during the PBT test based on the comparison signal of the logic high level output from the comparator 210 and output the fail cell (i.e. to-be-verified) address F/A of the corresponding defective cell.” Park [P.0098])
and when currently read data is the first data, determining that repair of the to-be-verified cell succeeds. (“In the PBT test, when data read from memory cells MCs of the first to fourth banks BANK1 to BANK4 are read in the same logic state, the comparator 210 may output, for example, a comparison signal of a logic low level (i.e. success). In the PBT test, when a different logic state is detected from even one of data read from memory cells MCs of the first to fourth banks BANK1 to BANK4, the comparator 210 may output, for example, a comparison signal of a logic high level (i.e. failure). The control circuit 124 may output the fail flag signal FS indicating that a defective cell has been detected during the PBT test based on the comparison signal of the logic high level output from the comparator 210 and output the fail cell address F/A of the corresponding defective cell.” Park [P.0098])
wherein before the writing first data into an address corresponding to the to-be-verified cell after repair replacement, the method further comprises: reading the address corresponding to the to-be-verified cell after repair replacement; (“the BIRA (built in redundancy analysis) circuit 220 may provide the information regarding the AST (address storage table) 222 to the TPG (test pattern generation) circuit 127. The TPG circuit 127 may perform a re-test (i.e. after repair replacement) on the first to fourth banks BANK1 to BANK4 to verify a repair operation by the BIRA circuit 220 based on the information regarding the AST 222.” Park [P.0085]. AST is interpreted to include cell addresses because “and store information regarding a fail cell address and a redundancy cell address in an address storage table (AST)” Park [P.0023])
and the writing first data into an address corresponding to the to-be-verified cell after repair replacement comprises: when currently read data is empty (“a built-in redundancy analysis (BIRA) circuit configured to perform a repair operation for replacing a defective cell detected in a PBT test or a DDR test on the memory device with a redundancy cell” Park [P.0023]. The redundancy cell is interpreted to be empty per Applicant’s disclosure [Spec. Pg.12 Ln.9-11] “before a redundant memory cell (i.e. redundant memory address) is used for repairing a regular memory cell, data stored in the redundant memory cell is empty.”), writing the first data into the address corresponding to the to-be-verified cell after repair replacement. (“the TPG circuit is further configured to perform a re-test on one or more memory cells including the defective cell among a plurality of memory cells to verify the repair operation through the BIRA circuit.” Park [P.0023]. The TPG circuit is interpreted to write first data to the to-be-verified cell because “The TPG circuit 127 may provide test patterns for detecting cell failures in the MCA (memory cell array) [...] the test patterns may include random test patterns, pseudo-random test patterns, which are similar to the random test patterns except that test vector sequences thereof are repeated, or parallel bit test (PBT) patterns including the same data (e.g., “0” or “1”)” Park [P.0068])
Park fails to specifically disclose wherein N is greater than or equal to 10 and less than or equal to 20.
However, Brozek discloses wherein N is greater than or equal to 10 and less than or equal to 20 (Given Applicant’s FIG.6 and FIG.7 disclosure, Examiner interprets this limitation to mean a 10x10 cross point array of memory elements. Brozek discloses “For each case, the resistance distributions were randomly generated for high and low resistance state, and Cross Point arrays of 10x10 elements were built.” [Pg.5 Col.2 P.2].
Brozek is analogous art as it relates to memory cell development and testing. Brozek discloses “complete characterization of the memory cells requires full memory array of desired size and logic-based periphery for Row/Column selection, read circuitry, etc. The memory testing involves writing various patterns to understand cell interaction, detect failure modes and possible spatial signals, caused by cell placements, or Row or Column interaction, and possible disturbs during Program, Erase, or Read operation.” [Pg.2 Col.2 B.].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Brozek’s disclosed 10X10 memory cell array with Park’s memory cell testing method in order for a “fast and inexpensive approach for process optimization and yield improvement of new emerging memories” Brozek [Pg.8 IV.].
Regarding claim 2, Park-Brozek disclose the method according to claim 1, Park further discloses wherein the selecting N memory cells as to-be-verified cells comprises: receiving N pieces of address information, (“The performing of the repair operation for repairing the defective cell with the redundancy cell through the MBIST circuit includes: outputting a fail flag signal indicating that the defective cell has been detected; outputting a fail cell address (i.e. N pieces of address information) of the defective cell (i.e. to-be-verified cell)” Park [P.0016])
wherein the address information comprises row address information and column address information of a memory cell, (“repairing each of a fail row address or a fail column address included in the fail cell address” Park [P.0016])
the row address information belongs to a row address information set of the memory array, and the column address information belongs to a column address information set of the memory array; (“the BIRA circuit 220 may store information regarding source addresses S_ADDR indicating the fail row address FRA and/or the fail column address FCA of one or more banks (i.e. memory array) that needed to be repaired and destination addresses D_ADDR indicating the redundancy row address RRA and/or the redundancy column address RCA in the AST 222.” Park [P.0082])
and determining the to-be-verified cells according to the address information. (“The BISR (built in redundancy analysis) control circuit 128 may include a row repairer 1281 that determines the redundancy row address RRA, such that redundancy resources for repairing the fail row address FRA do not overlap with one another.” Park [P.0120])
Regarding claim 4, Park-Brozek disclose the method according to claim 1, Park further discloses wherein the performing repair replacement on the to-be-verified cell by using a repair circuit comprises: randomly selecting a redundant memory cell; (“The TPG (test pattern generation) circuit (included within MBIST circuit, i.e. repair circuit) 127 may provide test patterns for detecting cell failures in the MCA 122 [...] the test patterns may include random test patterns, pseudo-random test patterns, which are similar to the random test patterns except that test vector sequences thereof are repeated, or parallel bit test (PBT) patterns including the same data (e.g., “0” or “1”)” Park [P.0068]. Note: The TPG circuit is included within the MBIST circuit, i.e. repair circuit (see claim 3))
and replacing an address of the to-be-verified cell with an address of the redundant memory cell, to complete repair replacement for the to-be-verified cell. (“The BIRA circuit 220 may perform a repair operation based on the BISR signals BISRS and replace the fail row address FRA and/or the fail column address FCA stored in the AST 222 with a redundancy row address RRA and/or a redundancy column address RCA, respectively” Park [P.0082])
Regarding claim 7, Park-Brozek disclose the method according to claim 1, Park further discloses wherein after the selecting N memory cells from a memory array as to-be-verified cells and before the performing repair verification on each to-be-verified cell, the method further comprises: writing second data into the to-be-verified cell, wherein the second data is different from the first data; (“Similarly, a PBT (parallel bit test) test for each of the first to fourth banks BANK1 to BANK4 may be performed or not performed according to the state of each of second to n-1-th (n is a natural number) test patterns.” Park [P.0104]. The second test pattern data is interpreted as different from initial test pattern data and the PBT test is understood to be performed before repair verification (reference Fig.10). Also, Park discloses two separate memory cell tests, PBT and DDR, both utilizing different test patterns (reference P.0014-15), which can be interpreted as writing different data into the to-be-verified cell.)
and the performing repair verification on each to-be-verified cell comprises: reading the to-be-verified cell; and when currently read data is the second data, performing repair verification on the to-be-verified cell. (“In operation S1040, the MBIST circuit 126 may perform an all cell check (i.e. repair verification) for testing all of the memory cells of the first to fourth banks BANK1 to BANK4. The MBIST circuit 126 may perform the all cell check of operation S1040 in the PBT test mode (i.e. second data).” Park [P.0128]. The cell check (i.e. repair verification) is interpreted as reading the to-be-verified cell.)
Regarding claim 8, Park-Brozek disclose the method according to claim 7, Park further discloses wherein after the reading the to-be-verified cell, the method further comprises: when the currently read data is not the second data, skipping repair verification for the to-be-verified cell. (“Similarly, a PBT test for each of the first to fourth banks BANK1 to BANK4 may be performed or not performed according to the state of each of second to n-1-th (n is a natural number) test patterns (i.e. second data) [...] When the operation state of the n-th test pattern TPn is disabled, no test is performed (i.e. skipping repair verification).” Park [P.0104-105])
Regarding claim 9, Park-Brozek disclose the method according to claim 1, Park further discloses wherein after the reading the address corresponding to the to-be-verified cell after repair replacement, the method further comprises: when the currently read data is not the first data, determining that repair of the to-be-verified cell fails. (“In the PBT test, when data read from memory cells MCs of the first to fourth banks BANK1 to BANK4 are read in the same logic state, the comparator 210 may output, for example, a comparison signal of a logic low level (i.e. success). In the PBT test, when a different logic state is detected from even one of data read from memory cells MCs of the first to fourth banks BANK1 to BANK4, the comparator 210 may output, for example, a comparison signal of a logic high level (i.e. failure). The control circuit 124 may output the fail flag signal FS indicating that a defective cell has been detected during the PBT test based on the comparison signal of the logic high level output from the comparator 210 and output the fail cell address F/A of the corresponding defective cell.” Park [P.0098])
Regarding Claim 10, Park discloses one or more processors; and a storage apparatus, configured to store one or more programs, wherein the one or more programs, when executed by the one or more processors, cause the one or more processors to execute operations (“The term “unit” or “module” may be implemented by a program that is stored in an addressable storage medium and executable by a processor.” Park [P.0063]).
The remaining limitations recite substantially the same subject matter as claim 1 and are rejected under similar rationale.
Claims 11, 13, 15-18 recite substantially the same subject matter as claims 2, 4, 6-9 and are rejected under similar rationale.
Regarding claim 19, Park discloses A computer readable storage medium, wherein the computer readable storage medium stores computer executable instructions, and the computer executable instructions are executed by a processor to implement the method according to claim 1. (“The term “unit” or “module” may be implemented by a program that is stored in an addressable storage medium and executable by a processor.” Park [P.0063]).
Conclusion
The prior art made of record, listed on form PTO-892, and not relied upon is
considered pertinent to applicant's disclosure:
COWLES et al. (Circuit And Method For Time-efficient Memory Repair – US Patent No 6918072 B2). This invention provides methods and circuitry for efficient testing and repair of semiconductor memory chips. It introduces on-chip address registers that store only the column address of defective memory cells, enabling rapid identification and repair of defective columns by replacing them with redundant memory columns.
Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
/ANTHONY CHAVEZ/ Examiner, Art Unit 2186
/RENEE D CHAVEZ/Supervisory Patent Examiner, Art Unit 2186
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