Prosecution Insights
Last updated: April 19, 2026
Application No. 17/813,954

MICROFLUIDIC CHIPS WITH ONE OR MORE VIAS

Final Rejection §103§112
Filed
Jul 21, 2022
Examiner
HYUN, PAUL SANG HWA
Art Unit
1796
Tech Center
1700 — Chemical & Materials Engineering
Assignee
International Business Machines Corporation
OA Round
4 (Final)
70%
Grant Probability
Favorable
5-6
OA Rounds
3y 5m
To Grant
99%
With Interview

Examiner Intelligence

Grants 70% — above average
70%
Career Allow Rate
582 granted / 834 resolved
+4.8% vs TC avg
Strong +36% interview lift
Without
With
+36.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
38 currently pending
Career history
872
Total Applications
across all art units

Statute-Specific Performance

§101
1.0%
-39.0% vs TC avg
§103
38.5%
-1.5% vs TC avg
§102
23.0%
-17.0% vs TC avg
§112
31.0%
-9.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 834 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment The amendment filed on January 9, 2026 is acknowledged. Claims 1-4, 6-14 and 16 remain pending. Applicant amended claims 1 and 11. Response to Arguments Regarding claims 1-4 and 6-10, the amendment necessitated the new ground of rejection set forth below. Consequently, Applicant’s argument directed to the patentability of the claims is moot. Regarding claims 11-14 and 16, despite the amendment, the claims remain rejected based on the disclosure of Foster et al. (“Foster”). That said, Applicant’s argument directed to the patentability of the claims has been fully considered but it is not persuasive. Applicant argues that claim 11 is patentable over the disclosure of Foster because Foster does not disclose the subject matter encompassed by the amended language, i.e. vias that “extend entirely through the silicon device layer from a second surface of the silicon device layer through to a first surface of the silicon device layer, wherein the second surface is located on a side of the silicon device layer opposite the first surface”. Remarks 6. The argument is not persuasive. Contrary to Applicant’s argument, silicon device layer 10 taught by Foster comprises vias 60 (not identified in Figure 10 but identified in Figure 8) that extend entirely through the thickness of the silicon device layer 10 from a second surface (bottom surface) to an opposing first surface (top surface). While the vias illustrated in Figure 10 appear to be used for the purpose of providing electrical connection (see bumps 94 and runners 32 associated with each via 60), meaning the vias are sealed and thus not in “fluid communication with a microfluidic device” as required by claim 11, Foster discloses that the vias may also be used for the purpose of establishing fluidic connections (see abstract and [0050]). Based on the disclosure, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have to formed the via 60 as a conduit for transporting fluid to the microfluidic element 36 for detection/processing. For the foregoing reason, the rejection of claims 11-14 and 16 is maintained, albeit it has been updated to address the amended claim language. Claim Interpretation The claims are interpreted in light of the specification. That said, the specification uses the terminology “microfluidic chip” to refer to the entire invention. In other words, according to the specification, the silicon device layer is a part of a “microfluidic chip”. Consequently, the recitation “the silicon device layer comprises a layer of a microfluidic chip” in claim 1 is being interpreted as conveying that “the silicon device layer constitutes a layer of a microfluidic chip” as opposed to conveying that “the silicon device layer includes a separate layer of a microfluidic chip”. Based on this interpretation, the recitation is taught by Foster, as Foster discloses that its invention is directed to a microfluidic device (see [0003]), meaning the components of the invention, including the silicon device layer 10, constitutes a layer of a microfluidic chip. As for claims 11 and 16, the claim only requires one via. Consequently, limitations directed to a plurality of vias is being interpreted as limiting the lone via required by the claim. Claim Rejections - 35 USC § 112 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claims 11-14 and 16 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Claim 11 recites a microfluidic element and subsequently a microfluidic device. The distinction between the two elements is unclear. The limitations “element” and “device” do not convey sufficient structure/function so as to distinguish the limitations in terms of scope (i.e. a microfluidic element can be a microfluidic device and vice versa). This is further supported by the specification, which uses the terms interchangeably. That said, it is unclear whether the claim intends to recite two different elements/devices, or whether the limitations refer to a common element/device. Based on prosecution history (the claim previously recited “the microfluidic device”, suggesting that the limitation intended to refer to the “microfluidic element” but was misspelled), it will be presumed that the latter limitation is referring to the former limitation. Claim Rejections - 35 USC § 103 Claims 11-14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Foster (US 2009/0212407 A1). With respect to claim 11, Foster discloses an apparatus comprising (see Fig. 10): a silicon device layer 10 comprising: a via 60 (see Figure 8 for identification of via using reference numeral 60) extending through the silicon device layer 10; and a microfluidic element 36 (see Fig. 4 for identification) embedded within and protruding from a first (top) surface of the silicon device layer 10, wherein the silicon device layer 10 has a thickness greater than or equal to about 7 micrometers and less than or equal to about 500 micrometers (see [0084]); and a sealing layer 20 bonded to the silicon device layer 10, wherein the sealing layer, due to having greater thickness (see Fig. 10), has greater rigidity than the silicon device layer 10, and wherein the via 60 extends entirely through the silicon device layer from a second surface (bottom surface) of layer 10 through to an opposing first surface (top surface) of layer 10. While Figure 10 of Foster does not explicitly illustrate a via 60 in fluid communication with the microfluidic element 36 (the via 60 appears to be used as an electrical connection, and hence it is sealed by bump 94 and runner 32), Foster discloses that vias of the apparatus may also be used for the purpose of establishing fluidic connections (see abstract and [0050]). Based on the disclosure, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have to formed the via 60 as a conduit for transporting fluid to the microfluidic element 36 for detection/processing. If the modification is made, then the via 60 would be in fluidic communication with the microfluidic element 36 as recited in claim 11. With respect to claim 12, Foster discloses that the layers of the apparatus can have a thickness up to 100 microns (see [0084] and claim 9). Based on the disclosure, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have provided the sealing layer 10 with a thickness of about 100 microns. With respect to claim 13, the sealing layer is silicon, as discussed above (see rejection of claim 2). With respect to claim 14, as discussed above, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have provided the apparatus with vias having a diameter that falls within the claimed range (see rejection of claim 4). With respect to claim 16, the vias are situated in a surface of the silicon device layer 10 that is opposite the sealing layer 20 (i.e. the vias are situated at the top surface of layer 10) (see Fig. 10). Moreover, as discussed above (see claim interpretation), the claim only requires a single via. Consequently, the spatial density of a plurality of vias does not further limit the claimed invention. Claims 1-4 and 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over Foster in view of Toner et al. (“Toner”) (US 2009/0014360 A1). With respect to claim 1, Foster discloses an apparatus comprising (see Fig. 10): a silicon (see [0084]) device layer 10 (see Fig. 9 for identification) comprising a plurality of vias 60 (see Fig. 8 for identification of vias), the plurality of vias spaced apart from one another by 25 microns or less (see [0085]), and the plurality of vias 60 extending through the silicon device layer (in Fig. 10, the device layer 10 is thinned such that the via extends through the device layer); a sealing layer 20 bonded to the silicon device layer, wherein the sealing layer, due to having greater thickness (see Fig. 10), has greater rigidity than the silicon device layer 10; and a microfluidic element 36 embedded within and protruding from a first (top) surface of the silicon device layer 10 (see Fig. 4), wherein the silicon device layer 10 constitutes a layer of a microfluidic chip (see [0003]). The apparatus taught by Foster differs from the claimed invention in that Foster does not explicitly disclose a device comprising vias arranged in a spatial density that falls within the claimed range. In addition, Foster does not disclose the recitation, “wherein the sealing layer is directly connected to and adjacent a first surface of the microfluidic element, wherein the silicon device layer is directly connected to and adjacent a second surface of the microfluidic element, wherein the second surface is opposite the first surface”. Regarding the spatial density of the vias, given that the spatial density of the vias taught by Foster (25 microns or less) overlaps the claimed range, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have provided the silicon device layer 10 with inter-via spacing that falls within the claimed range. Regarding the quoted recitation above not taught by Foster, given that the apparatus is intended to be used as a biological or a chemical sensor (see [0003]), it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have implemented the microfluidic element 36 as a conventional sensor, for example a sensor that utilizes a deterministic displacement array (DDA) (i.e. array of obstacles in a channel), as taught by Toner (see [0004], [0195] and [0223] of Toner disclosing that DDA has utility in microfluidic environmental sensing). If the modification is made, then the sealing layer 20 would be directly connected to and adjacent a first surface of the microfluidic element (i.e. top surface of the array of obstacles) and the silicon device layer 10 would be directly connected to and adjacent an opposing second surface of the microfluidic element (i.e. bottom surface of the array of obstacles). With respect to claim 2, the sealing layer 20, which is compositionally identical to the device layer, is made from silicon (see [0109]). With respect to claim 3, the silicon device layer 10 has a thickness greater than or equal to about 7 micrometers and less than or equal to about 500 micrometers (see [0084]). With respect to claim 4, Foster discloses that vias having a spatial density that falls within the claimed range can have diameters that fall within the claimed range (see [0085]). Based on the disclosure, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have provided the apparatus with vias having a diameter that falls within the claimed range. With respect to claim 6, as discussed above (see rejection of claim 11), it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have to formed the via 60 as a conduit for transporting fluid to the microfluidic element 36 for detection/processing. With respect to claim 7, the microfluidic element 36 is encapsulated by a combination of the silicon device layer 10 and the sealing layer 20 (see Fig. 10). With respect to claim 8, as discussed above (see rejection of claim 1), the microfluidic element 36 would be adapted to utilize a DDA. With respect to claim 9, the apparatus further comprises a fluidic bus 35 in fluid communication with the microfluidic element 36 (see Fig. 4). With respect to claim 10, as discussed above (see rejection of claim 1), the sealing layer 20 is thicker than the silicon device layer 10 (see Fig. 10). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL S HYUN whose telephone number is (571)272-8559. The examiner can normally be reached M-F 8:30-5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Luan Van can be reached at 571-272-8521. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PAUL S HYUN/ Primary Examiner, Art Unit 1796
Read full office action

Prosecution Timeline

Jul 21, 2022
Application Filed
May 30, 2025
Non-Final Rejection — §103, §112
Jul 04, 2025
Response Filed
Jul 30, 2025
Final Rejection — §103, §112
Aug 06, 2025
Applicant Interview (Telephonic)
Aug 06, 2025
Examiner Interview Summary
Aug 26, 2025
Response after Non-Final Action
Sep 30, 2025
Request for Continued Examination
Oct 02, 2025
Response after Non-Final Action
Oct 14, 2025
Non-Final Rejection — §103, §112
Jan 09, 2026
Response Filed
Mar 05, 2026
Final Rejection — §103, §112
Mar 16, 2026
Applicant Interview (Telephonic)
Mar 16, 2026
Examiner Interview Summary

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12599127
VITRIFICATION DEVICE AND METHOD FOR PREPARING SAMPLE
2y 5m to grant Granted Apr 14, 2026
Patent 12599906
CONTAINER FOR SMALL LIQUID VOLUMES
2y 5m to grant Granted Apr 14, 2026
Patent 12590508
MANIPULATION OF FLUIDS, FLUID COMPONENTS AND REACTIONS IN MICROFLUIDIC SYSTEMS
2y 5m to grant Granted Mar 31, 2026
Patent 12558684
ELECTRONIC DEVICE
2y 5m to grant Granted Feb 24, 2026
Patent 12551888
DEVICES AND METHODS FOR EXTRACTION, SEPARATION AND THERMOCYCLING
2y 5m to grant Granted Feb 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

5-6
Expected OA Rounds
70%
Grant Probability
99%
With Interview (+36.0%)
3y 5m
Median Time to Grant
High
PTA Risk
Based on 834 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month