Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 2, 4-8, 10-22 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-20 of U.S. Patent No. 11977508, in view of obviousness. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant application and the patent are both directed to:
Data Frames and Channels: Both applicants describe methods of receiving, processing, and transmitting data frames via data channels.
Header and Payload Data: Both focus on operations involving header and payload data, including read and write operations based on this data.
Checksum Validation: Both include steps for validating checksums to ensure data integrity before proceeding with operations.
Synchronous Operations: Both highlight the importance of synchronously receiving and transmitting frames, often in the same time interval or synchronously with a clock signal
Bus Node Configuration: Both describe a bus node comprising transmitting and receiving devices, control logic, and frame encoders/decoders configured to handle data frames and operations.
The differences between 11977508 are rendered obvious in view of new grounds of rejection in the 103 rejection below.
Instant Application
17/814370
Patent
11977508
Claim 1
A method comprising:
receiving a first frame via a first data channel,
wherein the first frame comprises at least a first header field having first header data and a first payload field having first payload data;
implementing a read operation at a read address determined by the first header data;
generating a second frame containing at least a second payload field having second payload data based on the data read when implementing the read operation;
transmitting the second frame via a second data channel with a temporal overlap with receiving the first frame via the first data channel;
and implementing a write operation on the basis of the first payload data.
claims 1, 2, 4, 5, 6 and 7
Receiving the first frame (claim 1)
Claim 1 describes receiving a first frame (including first header data and first payload data, plus a first checksum) via a first data channel using a serial data interface
[ie. “An electronic communication method comprising: receiving, via a serial data interface at a first bus node comprising a first interface controller, a first frame via a first data channel using clocked data transfer”, claim 1]
wherein the first frame comprises first header data, first payload data and a first checksum”, claim 1]
Read operation determined by header data (claims 4 and 5) Claim 4 specifies that a portion of the first header data comprises a memory address and that the method accesses this memory address
[ie.” The method of claim 1, wherein the portion of the first header data comprises a memory address of a memory included with the first bus node, and wherein the function accesses the memory address”, claim 4]
Claim 5 details that the function includes reading first data from that memory address, where the data read (the “first data”) determine the content used for the second payload.
[ie. “The method of claim 4, wherein the function accessing the memory address further comprises reading first data from the memory address, and wherein the second payload data are dependent on the first data”, claim 5]
Generating the Second Frame Based on the Read Data (claims 1 and 5)
In claim 1, after receiving a portion of the first frame,
[ie.” a function is executed to generate second header data and second payload data” claim 1].
Claim 5 further clarifies that the second payload data are dependent on the data read from the memory (i.e., the “first data”)
[ie. “The method of claim 4, wherein the function accessing the memory address further comprises reading first data from the memory address, and wherein the second payload data are dependent on the first data”, claim 5]
Transmitting the second frame with temporal overlap (claims 1 and 2)
Claim 1 explicitly requires that the second frame be transmitted via a second data channel (different from the first) simultaneously while receiving the first frame.
[ie.” a second frame comprising the second header data, the second payload data, and a second checksum calculated using the second payload data and the first header data simultaneously while the first frame is received; and transmitting, from the first bus node to the second bus node using the clocked data transfer from the first interface controller to the second interface controller via a second data channel different from the first data channel, the second frame simultaneously while receiving the first frame via the first data channel”, claim 1]
Claim 2 reinforces this by stating that the transmission of the second frame occurs while the first frame is being received
[ie. “The method of claim 1, wherein the second frame is transmitted while the first frame is being received”, claim 2]
Write Operation Based on the First Payload Data (claims 6 and 7)
The “write operation” is reflected in claims 6 and 7
Claim 6 adds that the function accessing the memory address (discussed in Claims 4 and 5) further comprises writing second data to that same memory address, where the second data are associated with the first payload data.
[ie. “The method of claim 5, wherein the function accessing the memory address further comprises writing second data to the memory address, and wherein the second data are associated with the first payload data”, claim 6]
Claim 7 clarifies the order (read before write) and the association between the data read and the second payload data.
[ie. “The method of claim 6, wherein the first data are read before the second data are written, and wherein the first data are associated with the second payload data”, claim 7]
Claim 2
The method as claimed in claim 1, wherein the first frame additionally contains a checksum
and the write operation is implemented only after successful checking of the checksum.
claims 1, 6, 7 and 9
Checksum inclusion (claim 1)
Claim 1 already recites that the first frame comprises first header data, first payload data, and a first checksum.
[ie. “wherein the first frame comprises first header data, first payload data and a first checksum; and responsive to receiving a portion of the first frame, executing, at the first bus node, a function to generate second header data and second payload data based at least on a portion of the first header data; generating, at the first bus node, a second frame comprising the second header data, the second payload data, and a second checksum calculated using the second payload data and the first header data simultaneously while the first frame is received”, claim 1]
Checksum validation (claim 9)
[ie. “The method of claim 1, further comprising: validating, at the first bus node, the first checksum based on the first header data and the first payload data”, claim 9]
The new limitation requires that the write operation be performed only after the first checksum has been successfully checked. Although none of the claims explicitly state that the write step is gated by checksum validation, Claim 9 adds the step of validation.
[ie. “The method of claim 1, further comprising: validating, at the first bus node, the first checksum based on the first header data and the first payload data”, Claim 9]
Write operation features (claims 6 and 7)
The write operation itself is described in Claims 6 and 7 (where second data are written to the memory address only after reading data from that address).
[ie. “The method of claim 5, wherein the function accessing the memory address further comprises writing second data to the memory address, and wherein the second data are associated with the first payload data”, claim 6]
[ie. “The method of claim 6, wherein the first data are read before the second data are written, and wherein the first data are associated with the second payload data”, claim 7]
Combining these elements, the amendment effectively introduces the requirement that the write operation (as per Claims 6 and 7) is executed only after the successful checksum validation (as per Claim 9).
Claim 3 (now part of claim 1):
The method as claimed in claim 1,
wherein the first payload data contain information regarding a write address and a data word,
and wherein implementing the write operation comprises writing data based on the data word to the write address.
claims 1, 4, 6 and 7:
Claim 1 discloses the overall method
[ie. “wherein the first frame comprises first header data, first payload data and a first checksum…”, claim 1]
and write operation is performed as a part of the method.
Structure of the first payload data
The limitation directs that the first payload is structured to include both a write address and a data word. However, per claim 4, the write address is obtained from the header [ie. “The method of claim 1, wherein the portion of the first header data comprises a memory address of a memory included with the first bus node, and wherein the function accesses the memory address”, claim 4]
Implementation of the write operation
Claim 6 (with claim 7) discloses the write operation. The specific write operation--writing data (the data word) to the write address—is functionally equivalent to the write step disclosed in Claim 6 (and sequenced in Claim 7),
[ie. “The method of claim 5, wherein the function accessing the memory address further comprises writing second data to the memory address, and wherein the second data are associated with the first payload data”, claim 6]
[ie. “The method of claim 6, wherein the first data are read before the second data are written, and wherein the first data are associated with the second payload data”, claim 7]
Claim 4:
The method as claimed in claim 1, wherein the second frame is transmitted in the same time interval in which the first frame is received.
Claims 1 and 2
Underlying Framework from Claim 1:
Claim 1 provides the basic method framework including receiving the first frame and transmitting the second frame.
[ie. “a second frame comprising the second header data, the second payload data, and a second checksum calculated using the second payload data and the first header data simultaneously while the first frame is received; and transmitting, from the first bus node to the second bus node using the clocked data transfer from the first interface controller to the second interface controller via a second data channel different from the first data channel, the second frame simultaneously while receiving the first frame via the first data channel”, claim 1]
Concurrent Transmission and Reception:
Claim 2 specifies that the second frame is transmitted concurrently (i.e., during the same time interval) with the reception of the first frame.
[ie.” The method of claim 1, wherein the second frame is transmitted while the first frame is being received”, claim 2]
Claim 5
The method of claim 1, wherein the second frame is transmitted while the first frame is being received.
claims 1 and 3
Base Framework from Claim 1
The method of Claim 1 already involves receiving a first frame and transmitting a second frame via clocked data transfer.
[ie. “a first frame via a first data channel using clocked data transfer via the serial data interface from a second bus node to the first bus node, wherein the second bus node comprises a second interface controller using the clocked data transfer… from the first bus node to the second bus node using the clocked data transfer”, claim 1]
Synchronous Operation with a Clock Signal:
The requirement for synchronous transmission and reception—i.e. the use of a clock signal to control the data transfer—is mapped to Claim 3
[ie. “The method of claim 1, wherein the clocked data transfer is a synchronous clocked data transfer using a clock signal generated by the second interface controller at the second bus node.”, claim 3]
Claim 6
The method as claimed in claim 1, wherein implementing the read operation takes place directly after receiving the first header data and even before the first frame has been completely received.
claim 1
In Claim 1 the first frame is received and, responsive to receiving a portion of it, a function is executed that includes generating the second frame. This “responsive” language implies that certain operations (like the read) may begin before the entire first frame is received.
[ie. “wherein the first frame comprises first header data, first payload data and a first checksum; and responsive to receiving a portion of the first frame”, claim 1] which implies that the read operation (a component of the function that generates the second frame) is initiated without waiting for the complete first frame
Claim 7
A bus node comprising: a transmitting and receiving device configured to receive a first frame via a first data channel,
wherein the first frame comprises at least a first header field having first header data and a first payload field having first payload data;
a control logic configured to implement a read operation at a read address determined by the first header data, and further configured to implement a write operation on the basis of the first payload data;
and a frame encoder configured to generate a second frame containing at least a second payload field having second payload data based on the data read when implementing the read operation;
wherein the transmitting and receiving device is further configured to transmit the second frame via a second data channel with a temporal overlap with receiving the first frame via the first data channel.
Claims 4-7 and 10
Transmitting/Receiving Device (claim 10)
[ie.” A first bus node for electronic communication, the first bus node comprising: a first interface controller configured to receive a first frame via a first data channel”, claim 10]
[ie. “wherein the first frame comprises first header data, first payload data and a first checksum”, claim 10]
Control Logic for Read and Write Operations (claims 4-7 and 10]
[ie. “a control logic configured to execute a function associated with the first header data, wherein the function is executed simultaneously while the first frame is received”, claim 10].
In the method claims (particularly Claims 4–7), that function includes both reading from a memory address (derived from the header) and performing a write operation (with the write operation associated with the payload data.
[ie. “The method of claim 1, wherein the portion of the first header data comprises a memory address of a memory included with the first bus node, and wherein the function accesses the memory address”, claim 4]
[ie. “The method of claim 4, wherein the function accessing the memory address further comprises reading first data from the memory address, and wherein the second payload data are dependent on the first data”, claim 5]
[ie. “The method of claim 5, wherein the function accessing the memory address further comprises writing second data to the memory address, and wherein the second data are associated with the first payload data”, claim 6]
[ie. “The method of claim 6, wherein the first data are read before the second data are written, and wherein the first data are associated with the second payload data”, claim 7]
Frame Encoder (claim 10)
[ie. “and a frame encoder configured to generate a second frame further comprising second header data, second payload data, and a second checksum, and further configured to calculate the second checksum based on the second payload data and the first header data”, claim 10]
Temporal Overlap (claim 10)
This “simultaneous” or “temporal overlap” operation is the same.
[ie. “wherein the first interface controller is further configured to transmit the second frame to the second interface controller via a second data channel different from the first data channel simultaneously while receiving the first frame via the first data channel”, claim 10]
Claim 8
The bus node as claimed in claim 7, wherein the first frame additionally contains a checksum
and the control logic is configured to implement the write operation only after successful checking of the checksum.
claims 1, 6, 7 and 9
Checksum Inclusion (claim 1)
Claim 1, which discloses that the first frame comprises a checksum
[ie. “wherein the first frame comprises first header data, first payload data and a first checksum; and responsive to receiving a portion of the first frame, executing, at the first bus node, a function to generate second header data and second payload data based at least on a portion of the first header data; generating, at the first bus node, a second frame comprising the second header data, the second payload data, and a second checksum calculated using the second payload data and the first header data simultaneously’, claim 1]
Conditional Write Operation (claims 6, 7 and 9)
Claim 9, specifies that the first bus node validates the first checksum (based on the first header and payload data) before proceeding with further operations. In the method, the write operation (described in Claims 6 and 7) is performed only after this validation is successful.
[ie. “The method of claim 1, further comprising: validating, at the first bus node, the first checksum based on the first header data and the first payload data”, claim 9]
[ie. “The method of claim 5, wherein the function accessing the memory address further comprises writing second data to the memory address, and wherein the second data are associated with the first payload data”, claim 6]
[ie. “The method of claim 6, wherein the first data are read before the second data are written, and wherein the first data are associated with the second payload data, claim 7]
Claim 9 (now part of claim 7)
The bus node as claimed in claim 7, wherein the first payload data contain information regarding a write address and a data word,
and wherein implementing the write operation comprises writing data based on the data word to the write address.
claims 1, 4, 6 and 7
Modification of the First Payload Data: •The claim requires that “the first payload data contain information regarding a write address and a data word.” • In the original disclosure (Claim 1), the first frame is defined to include first header data and first payload data [ie. “wherein the first frame comprises first header data, first payload data and a first checksum”, claim 1].
However, Claim 4 teaches that a portion of the first header data comprises a memory address used in the read operation. In contrast, this limitation shifts the location of the write address from the header to the payload, thereby modifying the structure of the first payload [ie. “The method of claim 1, wherein the portion of the first header data comprises a memory address of a memory included with the first bus node, and wherein the function accesses the memory address”, claim 4]
Implementation of the Write Operation: • The claim further recites that “implementing the write operation comprises writing data based on the data word to the write address.” • In the patent’s disclosure, Claim 6 specifies that the function accessing the memory address further comprises writing second data to that memory address [ie. “The method of claim 5, wherein the function accessing the memory address further comprises writing second data to the memory address, and wherein the second data are associated with the first payload data”, claim 6], with Claim 7 clarifying the sequence (i.e. that the read occurs before the write) [ie. “The method of claim 6, wherein the first data are read before the second data are written, and wherein the first data are associated with the second payload data”, claim 7] • Thus, while the original claims associate the write operation with a memory address extracted from the header (per Claim 4), this limitation maps to the same functional write operation disclosed in Claims 6 and 7 but with the address and data now derived from the payload.
Claim 10
The bus node as claimed in claim 7, wherein the control logic is configured to implement the read operation directly after receiving the first header data
even before the first frame has been completely received
claims 1 and 7
This emphasizes that the read operation is initiated immediately upon receipt of the header rather than waiting for the entire fame. Although none of the dependent claims spell out this exact timing, the inherent processing in claim 1 support this approach.
The overall method in claim 1 teaches that operations (such as generating the second frame) occur concurrently with the reception of the first frame. The new limitation specially narrows this by requiring that the read operation starts as soon as the header is available, without waiting for the remainder of the frame. This is consistent with the “responsive to receiving a portion” language in claim 1 [ie. “wherein the first frame comprises first header data, first payload data and a first checksum; and responsive to receiving a portion of the first frame, executing, at the first bus node”, claim 1],
and the ordered sequencing of operations (read-before write) clarified in claim 7 [ie. “The method of claim 6, wherein the first data are read before the second data are written, and wherein the first data are associated with the second payload data”, claim 7]
Claims 11-22 are rejected for similar reasons as stated above.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4-7, 10-12, 14, 16-17, 19-21 is/are rejected under 35 U.S.C. 102 as being anticipated by Matlock (20140136738).
As per claim 1, Matlock shows the use of a method comprising: receiving a first frame via a first data channel, wherein the first frame comprises at least a first header field having first header data and a first payload field having first payload data (e.g., figure 1, element 133 and figure 4); implementing a read operation at a read address determined by the first header data (e.g., figure 4 received MOSI); generating a second frame containing at least a second payload field having second payload data based on data read when implementing the read operation (e.g., figure 4, transmitting MISO); transmitting the second frame back to a source of the first frame via a second data channel with a temporal overlap with receiving the first frame via the first data channel (e.g., figure 4); and implementing a write operation on the basis of information regarding a write address contained in the first payload data and a data word contained in the first payload data, wherein implementing the write operation comprises writing data based on the data word to the write address (e.g., figure 3 and paragraphs 48-53).
As per claim 4, Matlock shows wherein the second frame is transmitted in a same time interval in which the first frame is received (e.g., figures 3 and 4).
As per claim 5, Matlock shows wherein the first frame and the second frame are received and respectively transmitted synchronously with a clock signal (e.g., figure 3, SCLK).
As pare claim 6, Matlock shows the use of wherein implementing the read operation takes place directly after receiving the first header data and even before the first frame has been completely received (e.g., figure 4, “READY”).
As per claim 7 it is rejected for similar reasons as claim 1. In addition, Matlock shows the use of frame encoder configured to generate a second frame containing at least a second payload field having second payload data based on the data read when implementing the read operation (e.g., figure 4 and paragraph 66).
As per claims 10-12, they are rejected for similar reasons as claims 4-6.
As per claim 14, Matlock shows wherein the control logic is further configured to generate a second header field, and the second frame further comprises the second header field (e.g., figure 10, elements 420 and 422).
As per claim 16, it is rejected for similar reasons as claim 14.
As per claim 17, it is rejected for similar reasons as claim 1. In addition, Matlock shows the use of a processor and memory (e.g. figure 1 and paragraphs 95-97).
As per claim 19-21, they are rejected for similar reasons as claims 4-6.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 8, 13, 15, 18 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matlock (20140136738) in view of Hoermaier (20200136754).
As per claim 2, Matlock does not show, however Hoermaier does show wherein the first frame additionally contains a checksum and the write operation is implemented only after successful checking of the checksum (e.g., paragraph 80). It would have been obvious to one of ordinary skill in the art prior to the effective filing date to modify the method of Matlock with Hoermaier because it would provide for end to end protection of the data.
As per claim 8, it is rejected for similar reasons as claim 2.
As per claim 13, Matlock does not show, however Hoermaier wherein the control logic is further configured to determine a checksum for the second frame based on at least the second payload data and on the first header data of the first frame (e.g., paragraph 9). It would have been obvious to one of ordinary skill in the art prior to the effective filing date to modify the method of Matlock with Hoermaier because it would provide for end to end protection of the data.
As per claim 15, it is rejected for similar reasons as claim 13.
As per claim 18, it is rejected for similar reasons as claim 2.
As per claim 22, it is rejected for similar reasons as claim 13.
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection necessitated by Applicant’s amendment.
Applicant's arguments filed 7/20/26, with respect to the double patenting rejection have been fully considered but they are not persuasive. Applicants argued that the claimed “write operation” is “functionally equivalent” without addressing providing any obviousness analysis. In response to Applicant’s remarks, obviousness is not needed when using functionally equivalent. It’s a one to one mapping.
Applicants also argued that the office action did not address the how or why one of ordinary skill in the art would modify the ‘508 Patent to meet the limitation of “a write address contained in the first payload data.”. In response to Applicant’s remarks, the examiner had stated in the double patenting rejection above that the differences between 11977508 are rendered obvious in view of new grounds of rejection in the 103 rejection below. Furthermore, the claim language is “implementing a write operation on the basis of information regarding a write address contained in the first payload data”. The claim is interpreted as information contained in the first payload data.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nakajima (20170276509) shows the use of MISO and MOSI using SPI protocol (e.g., figure 9).
Kazuno (20140115212) shows the use of MISO and MOSI using SPI protocol (e.g, figures 5A-10).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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