Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Arguments
Applicant’s arguments filed 03/10/2026 have been fully considered but they are not persuasive.
The applicant argues that Kobayashi et al. does not disclose the limitation as presented in claim 1. The examiner respectfully disagrees. Kobayashi et al. (figures 1-8) discloses an electronic device as claimed including a plurality of gate lines (G; figure 3) disposed on the substrate and extending along a second direction, wherein the first direction is different from the second direction; a plurality of data lines (S; the lines can be extended in three different directions, xyz) disposed on the substrate and extending along the first direction, wherein the data lines are electrically insulated from the signal lines, and the gate lines and the data lines intersect to define a plurality of sub-pixel units, the plurality of sub-pixel units comprises a first sub-pixel unit and a second sub-pixel unit adjacent to the first sub-pixel unit (each sub-pixel unit can comprise a plurality of sub-pixels); and a gate driving unit (SW of the current sub-pixel unit and the neighboring sub-pixel unit) disposed in the active area and including a receiving switch element, a first buffer switch element and a second buffer switch element, wherein the receiving switch element is disposed corresponding to the first spacer, the receiving switch element is electrically connected to the first signal line and receives an input signal through the first signal line, the first buffer switch element is disposed corresponding to the second spacer and is electrically connected to the receiving switch element, and the second buffer switch element is electrically connected to the receiving switch element, wherein one of the gate lines is electrically connected to a first node which is between the first buffer switch element and the second buffer switch element, wherein the plurality of data lines comprises a first data line and a second data line, the first data line is electrically connected to the first sub-pixel unit, and the second data line is electrically connected to the second sub-pixel, wherein the first signal line and the second data line are disposed between the first sub- pixel unit and the second sub-pixel unit (the spacers are disposed between the pixels; see annotated drawing 1). The claim language therefore does not patentably distinguish over the applied reference[s], and the previous rejections are maintained.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-5, 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kobayashi et al. (US 2012/0327338).
Regarding claim 1, Kobayashi et al. (figures 1-8) discloses an electronic device, comprising:
a substrate including an active area and a peripheral area adjacent to the active area (figure 1);
a plurality of spacers (SP) disposed in the active area and including a first spacer and a second spacer (SP of the current pixel and the neighboring pixel);
a plurality of signal lines (S; figure 3) arranged on the substrate and extending along a first direction, wherein the plurality of signal lines comprises a first signal line;
a plurality of gate lines (G; figure 3) disposed on the substrate and extending along a second direction, wherein the first direction is different from the second direction; a plurality of data lines (S; the lines can be extended in three different directions, xyz) disposed on the substrate and extending along the first direction, wherein the data lines are electrically insulated from the signal lines, and the gate lines and the data lines intersect to define a plurality of sub-pixel units, the plurality of sub-pixel units comprises a first sub-pixel unit and a second sub-pixel unit adjacent to the first sub-pixel unit (each sub-pixel unit can comprise a plurality of sub-pixels); and
a gate driving unit (SW of the current sub-pixel unit and the neighboring sub-pixel unit) disposed in the active area and including a receiving switch element, a first buffer switch element and a second buffer switch element,
wherein the receiving switch element is disposed corresponding to the first spacer, the receiving switch element is electrically connected to the first signal line and receives an input signal through the first signal line, the first buffer switch element is disposed corresponding to the second spacer and is electrically connected to the receiving switch element, and the second buffer switch element is electrically connected to the receiving switch element, wherein one of the gate lines is electrically connected to a first node which is between the first buffer switch element and the second buffer switch element, wherein the plurality of data lines comprises a first data line and a second data line, the first data line is electrically connected to the first sub-pixel unit, and the second data line is electrically connected to the second sub-pixel, wherein the first signal line and the second data line are disposed between the first sub- pixel unit and the second sub-pixel unit (the spacers are disposed between the pixels; see annotated drawing 1).
The limitation, “wherein the receiving switch element is disposed corresponding to the first spacer and receives an input signal through one of the signal lines, and the buffer switch element is disposed corresponding to the second spacer and is electrically connected to the receiving switch element, wherein the buffer switch element outputs a scan signal to one of the gate lines” is functional in nature. Such a functional limitation is only given patentable weight insofar as it imparts a structural limitation. Here, Kobayashi et al. discloses the structural limitations required to perform the function as claimed. It is further noted that apparatus claims must be structurally distinguishable from the prior art and that the manner of operating the device does not differentiate the apparatus claim from the prior art (see e.g. MPEP 2114). In other words, the prior art need not perform the function, but must merely be capable of doing so.
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Regarding claim 2, Kobayashi et al. (figures 1-8) discloses wherein the sub-pixel units include a green sub-pixel unit and a blue sub-pixel unit, wherein an aperture ratio of the blue sub-pixel unit is different from that of the green sub-pixel unit (figure 8).
Regarding claim 4, Kobayashi et al. (figures 1-8) discloses wherein at least one of the receiving switch element and the buffer switch element is disposed adjacent to the blue sub-pixel unit.
Regarding claim 5, Kobayashi et al. (figures 1-8) discloses wherein the gate driving unit further includes a switch element, and the switch element is electrically connected to at least one of the receiving switch element and the buffer switch element (SW of another pixel).
Regarding claim 22, Kobayashi et al. (figures 1-8) discloses wherein a gate of the first buffer switch element and a gate of the second buffer switch element are electrically connected to a second node (see annotated drawing 1), and an input terminal of the first buffer switch element and an input terminal of the second buffer switch element are configured to receive different signals respectively (the TFT is connected to different signal / data lines).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi et al. (US 2012/0327338).
Regarding claim 3, Kobayashi et al. discloses the limitations as shown in the rejection of claim 2 above. However, Kobayashi et al. is silent regarding wherein a ratio of the aperture ratio of the blue sub-pixel unit to the aperture ratio of the green sub-pixel unit is between 70% and 99%. Kobayashi et al. (figures 1-8) discloses wherein a ratio of the aperture ratio of the blue sub-pixel unit to the aperture ratio of the green sub-pixel unit is between 70% and 99% (figure 8). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify aperture ratio of the sub-pixel in order to improve the occurrence of display non-uniformity due to the spacer.
One of ordinary skill in the art before the effective filing date of the claimed invention would recognize utilizing a value close to applicant's claimed range, since it has been held that where the general condition of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. Further, it has been held that a prima facie case of obviousness exists where the claimed ranges and prior art ranges do not overlap by are close enough that one skilled in the art would have expected them to have the same properties. Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985).
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990) (The prior art taught carbon monoxide concentrations of “about 1-5%” while the claim was limited to “more than 5%.” The court held that “about 1-5%” allowed for concentrations slightly above 5% thus the ranges overlapped.). Similarly, a prima facie case of obviousness exists where the claimed ranges and prior art ranges do not overlap but are close enough that one skilled in the art would have expected them to have the same properties. Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985) (Court held as proper a rejection of a claim directed to an alloy of “having 0.8% nickel, 0.3% molybdenum, up to 0.1% iron, balance titanium” as obvious over a reference disclosing alloys of 0.75% nickel, 0.25% molybdenum, balance titanium and 0.94% nickel, 0.31% molybdenum, balance titanium.). See MPEP § 2144.05.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi et al. (US 2012/0327338) in view of Tian (KR 2017-0126183).
Regarding claim 21, Kobayashi et al. discloses the limitations as shown in the rejection of claim 1 above. However, Kobayashi et al. is silent regarding wherein the first buffer switch element is an N-type switch element and the second buffer switch element is a P-type switch element. Tian (figures 1-5) discloses wherein the first buffer switch element is an N-type switch element and the second buffer switch element is a P-type switch element (360 and 362 of the neighboring pixels). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the transistors as taught by Tian in order to improve the display quality of the image of the display device.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAUREN NGUYEN whose telephone number is (571)270-1428. The examiner can normally be reached on Monday - Thursday, 8:00 AM -6:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jennifer Carruth, can be reached at 571-272-9791. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAUREN NGUYEN/Primary Examiner, Art Unit 2871