Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 14 and 15 objected to because of the following informalities: “Tide data” appears to be a misspelling of “time data”. Appropriate correction is required.
Applicant is advised that should claim 7 be found allowable, claim 8 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 7-14, and 16-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Moore (US 20190230304 A1).
Claim 1: Moore teaches a method to determine time of flight for light detection and ranging, the method comprising:
enabling a time to digital converter ([0092] - activation and [0035] - TDC);
emitting a light pulse after enabling the time to digital converter ([0092] - portion of SPAD array enabled before emission);
initiating a sampling window at a time of emission of the light pulse (Fig. 2K, [0087]);
using the time to digital converter to determine times of flight for photons detected during the sampling window (Fig. 2K, showing sampling windows and [0029] - distance);
initiating a blanking period in response to concluding the sampling window; and disabling the time to digital converter in response to initiation of the blanking period ([0091] - disabling SPAD after pulse).
Claim 2: Moore teaches the method of claim 1, further comprising emitting a subsequent light pulse after an end of the blanking period ([0091]).
Claim 3: Moore teaches the method of claim 2, further comprising re-enabling operation of the time to digital converter before emission of the subsequent light pulse, initiating a subsequent sampling window at a time of emission of the subsequent light pulse, using the time to digital converter to determine times of flight for photons detected during the subsequent sampling window; initiating a subsequent blanking period after an end of the subsequent sampling window; and disabling the time to digital converter after initiating the subsequent blanking period ([0092] - repetition).
Claim 4: Moore teaches the method of claim 1, further comprising incrementing bins of a histogram depending on times of flight of photons detected during the sampling window ([0030]).
Claim 5: Moore teaches the method of claim 1, wherein using the time to digital converter to determine times of flight for photons detected during the sampling window comprises detecting a photon, opening a clock gate gating a clock input for the time to digital converter in response to detecting the photon, and sampling a time of flight of the photon after opening the clock gate ([0029], [0041]).
Claim 7: Moore teaches the method of claim 1, wherein enabling the time to digital converter comprises enabling a synchronous time to digital converter ([0039]- TDC input synchronized with reference clock).
Claim 8: Moore teaches the method of claim 1, wherein enabling a time to digital converter comprises enabling a synchronous time to digital converter ([0039]- TDC input synchronized with reference clock).
Claim 9: Moore teaches the method to determine time of flight for light detection and ranging, the method comprising:
detecting a photon; opening a clock gate in response to detecting the photon; and sampling data using a time to digital converter on a next edge of a clock signal passed by the clock gate after opening the clock gate (Fig. 2H, step 259, [0063])).
Claim 10: Moore teaches the method of claim 9, wherein the next edge of the clock signal comprises a next falling edge of the clock signal ([0064]).
Claim 11: Moore teaches the method of claim 9, further comprising initiating a count beginning with a time of emission of a light pulse and wherein sampling time data using the time to digital converter comprises sampling the count ([0003]).
Claim 12: Moore teaches the method of claim 9, further comprising incrementing a bin of a histogram depending on the data sampled ([0030]).
Claim 13: Moore teaches the method of claim 9, further comprising
the time to digital converter ([0092] - activation and [0035] - TDC);
emitting a light pulse after enabling the time to digital converter ([0092] - portion of SPAD array enabled before emission);
initiating a sampling window at a time of emission of the light pulse; the photon being detected during the sampling window (Fig. 2K, [0087]);
initiating a blanking period in response to concluding the sampling window; and disabling operation of the time to digital converter in response to initiation of the blanking period ([0091] - disabling SPAD after pulse).
Claim 14: Moore teaches the method of claim 9, sampling time data using a time to digital converter comprises using a synchronous time to digital converter to sample tide data ([0039]- TDC input synchronized with reference clock).
Claim 16: Moore teaches the method of claim 9, wherein sampling time data using a time to digital converter comprises sampling a timestamp indicating a time elapsed between emission of a light pulse and detecting the photon ([0026]).
Claim 17: Moore teaches a power-saving time to digital converter system comprising:
a time to digital converter comprising an input to receive data and a clock input ([0076]),
the time to digital converter being configured to sample data received at the input in response to assertion of a signal received at the clock input (Fig. 2H, step 257 and [0076]);
and a gating circuit comprising an event-detection input configured to receive an event-detection signal and a gating input ([0046]),
wherein the gating circuit is configured to open and close an output of the gating circuit depending on a gating signal received at the gating input ([0046]),
the gating signal being synchronized with a time period of interest for operating the time to digital converter,
and wherein the output is coupled with the time to digital converter ([0049]).
Claim 18: Moore teaches the system of claim 17, further comprising an event-driven gating logic circuit comprising an event-detection input configured to receive an event detection signal, a data input configured to receive a data signal, and an output coupled with time to digital converter, and wherein the event-driven gating logic circuit is configured to open its output in response to asserting the event-detection signal ([0057]).
Claim 19: Moore teaches the system of claim 18,
wherein the time to digital converter comprises a synchronous time to digital converter ([0039]- TDC input synchronized with reference clock),
the output of the gating circuit is coupled with the data input of the time to digital converter ([0057]),
the output of the event-driven gating logic circuit is coupled with the clock input of the time to digital converter ([0057]),
and wherein the data signal received by the event-driven gating logic circuit comprises a clock signal ([0057]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Moore (US 20190230304 A1) in view of Kumar (US 20140232827 A1).
Claim 6: Moore teaches the method of Claim 5. Moore does not teach, but Kumar does teach, wherein sampling the time of flight of the photon comprises sampling on a negative clock edge after opening the clock gate ([0056]).
It would have been obvious before the effective filing date to use the negative clock edge, as taught by Kumar, with the method as taught by Moore because, as Kumar teaches, this can avoid random triggering ([0012]).
Claims 15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Moore (US 20190230304 A1) in view of Vaananen (US 20080317186 A1).
Claim 15: Moore teaches the method of Claim 9. Moore does not teach, but Vaananen does teach, sampling time data using a time to digital converter comprises using an asynchronous time to digital converter to sample tide data ([0039]).
It would have been obvious before the effective filing date to use the asynchronous TDC, as taught by Vaananen, in the method as taught by Moore, because, as Vaananen teaches, this improves accuracy ([0041]).
Claim 20: Moore teaches the system of claim 18,
[…]
the output of the gating circuit is coupled with the clock input of the time to digital converter ([0057]),
the output of the event-driven gating logic circuit is coupled with the data input of the time to digital converter ([0057]),
and wherein the data signal received by the event-driven gating logic circuit comprises a timestamp ([0026]).
Moore does not teach, but Vaananen does teach, wherein the time to digital converter comprises an asynchronous time to digital converter ([0039]).
It would have been obvious before the effective filing date to use the asynchronous TDC, as taught by Vaananen, in the method as taught by Moore, because, as Vaananen teaches, this improves accuracy ([0041]).
Conclusion
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/CLARA G CHILTON/Examiner, Art Unit 3645
/ROBERT W HODGE/Supervisory Patent Examiner, Art Unit 3645