DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 15 – 19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention (Invention II), there being no allowable generic or linking claim. Election of Invention I was made without traverse in the reply filed on 22 July 2025.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference characters not mentioned in the description: 201, 301, and 401 labeled in FIGS. 8, 9, and 10, respectively.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the subject matter of claim 11, that “the trap layer completely covers an upper surface of the PMD layer in the second region”, must be shown or the feature canceled from the claim. No new matter should be entered.
The drawings are objected to because of the following additional informalities:
In FIGS. 4, 5, and 6, there appears to be a thin layer above the substrate that is not labeled in any manner, and thus its presence is unclear (note at page 14, lines 5 – 9 of the specification, it is stated that the oxide film must generally be removed from the second region A2);
In FIGS. 3 and 20, the sidewall spacer mentioned at page 10, lines 2 – 6 should be identified with a reference character (cf. specification, page 10, line 2); and
In FIGS. 11 – 12, the meaning of “S/W” in the label “S/W Stack” is unclear from the specification.
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several view of the drawings for consistency. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The abstract of the disclosure is objected to because the abstract should be in narrative form and should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details. The language should be clear and concise and should not repeat information given in the title. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The disclosure is objected to because of the following informalities:
At page 2, lines 12 – 13 as well as at page 10, lines 22 – 23, comparison is made to a “conventional SOI substrate 9”, with the implication that is does not include a trap layer, whereas in FIG. 1, substrate 9 does include a trap layer 970;
At page 2, lines 15 – 16 as well as at page 10, lines 25 – 26, “ohm•com” should be “ohm•cm”;
At page 5, line 14, an extra comma appears after “device”;
At page 11, line 18, an extra “is” appears after “trap layer 150”;
At page 11, line 22, some extra spacing appears before “(see FIG. 6)”; and
At page 13, line 3, an extra “between” appears after “reduce”.
Appropriate correction is required.
Claim Objections
Claim 5 objected to because of the following informality: It would appear to be necessary to change the dependence of claim 5 to claim 4, instead of claim 3, due to the recitation of “the at least one metal wire in the second region”, for antecedent basis purposes. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 6 – 11 and 14 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
The term “substantially” in claims 6, 10, and 14 is a relative term which renders the claims indefinite. The term “substantially” is not defined by the claims, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Claims 7 – 9 and 11 are rejected on the same basis as dependent from claim 6.
Furthermore, in claim 7, the recitation of “wherein a plurality of the metal wires are in the second region” is unclear because claim 6, from which claim 7 depends, “a plurality of metal wires spaced apart from each other”. Does claim 7 refer to some of the plurality of metal recited in claim 6, or a different plurality of metal wires? There is insufficient antecedent basis for this limitation in the claim.
Still further, in claims 8 – 10, the recitation of “wherein the trap layer between adjacent ones of the metal wires in the second region” is unclear because the only positional relationships previously recited in claims 6 and 7, from which claims 8 – 10 depend, are that a plurality of metal wires are in the second region and the trap layer vertically overlaps one of the metal wires in the second region. As such, there is insufficient antecedent basis for “the trap layer between adjacent one of the metal wires in the second region.
Still further, in claim 11, the recitation “wherein the trap layer completely covers an upper surface of the PMD layer in the second region” is unclear because the specification and the drawings show that a pre-metal dielectric (PMD) layer 160 is on the substrate 101 and on the trap layer 150 (see FIG. 4 and page 11, lines 11 – 12; see also the recitation in claim 6). It is thus unclear how the trap layer could completely cover an upper surface of the PMD layer.
Claim Rejections - 35 USC § 103
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 – 14 are rejected under 35 U.S.C. 103 as being unpatentable over Seefeldt, James D., US. 6,355,537 B1 (hereinafter “Seefeldt”) in view of Kumauchi, Takahiro, et al., US 5,773,340 A (hereinafter “Kumauchi”). FIG. 2 of Seefeldt is reproduced herein for reference.
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Regarding claim 1, Seefeldt discloses an RF switch device (see FIGS. 1 – 3 and col. 1, ll. 17 – 21, device 20), comprising:
a high resistivity substrate (see FIG. 2 and col. 4, ll. 26 – 54, substrate 22, particularly including layers 40, 42, 44, and 46 as further described at col. 6, ll. 8 – 37); see also FIG. 6);
a plurality of gates on the substrate in a first region (see FIGS. 2 and 9 – 10, and col. 7, l. 5 – col. 8, l. 16, wherein the first region is the first device mesa 28 in FIG. 2, with greater detail regarding the preferred BiCMOS process technology being shown in FIGS. 9 – 10, particular step 414 of FIG. 10);
a source and a drain in the first region (see id., particularly step 416 of FIG. 10);
a well in the substrate (see id., particularly steps 410 and 412 of FIG. 10);
a device isolation layer in the substrate at a boundary between the first region and a second region (see FIGS. 1 – 3 and col. 4, l. 8 – col. 5, l. 34, isolation trench 26 forming a boundary between the first region (28) and a second (guard ring) region 36); and
a trap layer on the substrate in the second region (see FIGS. 2 – 3 and 8, col. 4, ll. 26 – 54, and col. 6, ll. 55 – 65, collector layer 48 which is disposed on layer 46 of substrate 22).
While FIG. 2 of Seefeldt does not explicitly disclose details of the claimed gate, S/D regions, and well in the context of the inventive embodiment, it is shown in FIGS. 9 – 10 and described at col. 7, ll. 5 – 30 that it is desirable to use a BiCMOS process such as illustrated in FIGS. 9 – 10 or in various prior art patents such as Kumauchi at FIGS. 1 – 4 (col. 5, l. 66 – col. 8, l. 25) in order to manufacture the inventive embodiment.
Obviousness can be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so. (See In re Kahn, 441 F.3d 977, 986 (Fed. Cir. 2006); MPEP 2143.01.) Seefeldt itself, as noted above, provides a clear teaching and suggestion to use the process described in, e.g., Kumauchi, to fabricate the inventive embodiment. Accordingly, it would have been prima facie obvious to a person having ordinary skill in the art before the effective filing date of the present application to have used the BiCMOS process taught in Kumauchi or FIGS. 9 – 10 of Seefeldt to fabricate the inventive embodiment of Seefeldt.
Regarding claim 2, Seefeldt in view of Kumauchi is relied on for the RF switch device of claim 1 as above, and Seefeldt further discloses wherein the trap layer comprises poly-silicon or amorphous silicon (see Seefeldt, FIGS. 9 – 10, and col. 7, l. 37 – col. 8, l. 13, describing poly-silicon deposition / doping in the second region, which would form part of the trap layer when the process of FIGS. 9 – 10 are used to fabricate the inventive device).
Regarding claim 3, Seefeldt in view of Kumauchi is relied on for the RF switch device of claim 2 as above, and both Seefeldt and Kumauchi further disclose a pre-metal dielectric (PMD) layer on the trap layer and the substrate (see Seefeldt, FIGS. 9 – 10, col. 8, ll. 13 – 16, step 426; Kumauchi, FIGS. 11 and 16, and col. 10, ll. 22 – 51, insulating film 25, and col. 12, ll. 30 – 32) and Seefeldt further discloses a plurality of metal wires spaced apart from each other on the PMD layer (see Seefeldt, FIGS. 2 and 9 – 10, col. 8, ll. 13 – 16, and col. 4, ll. 26 – 54, conductors 52 and step 426).
Regarding claim 4, Seefeldt in view of Kumauchi is relied on for the RF switch device of claim 3 as above, and Seefeldt further discloses wherein at least one of the metal wires is in the second region, and the trap layer at least partially overlaps the at least one metal wire in the second region vertically (see Seefeldt, FIGS. 2 and 9, illustrating the relative positioning of the conductors 52 (i.e., metallization in the context of the suggested BiCMOS process of FIG. 9)).
Regarding claim 5, Seefeldt in view of Kumauchi is relied on for the RF switch device of claim 3 as above, and Seefeldt, FIG. 9, illustrates the relative proportions of the metallization outside of the first (CMOS) region as would be applied to the inventive device of FIG. 2, such that the trap layer is below the at least one metal wire in the second region and has a width greater than that of the at least one metal wire in the second region.
Regarding claim 6, Seefeldt discloses an RF switch device (see FIGS. 1 – 3 and col. 1, ll. 17 – 21, device 20), comprising:
a high resistivity substrate (see FIG. 2 and col. 4, ll. 26 – 54, substrate 22, particularly including layers 40, 42, 44, and 46 as further described at col. 6, ll. 8 – 37); see also FIG. 6);
a gate on the substrate in a first region (see FIGS. 2 and 9 – 10, and col. 7, l. 5 – col. 8, l. 16, wherein the first region is the first device mesa 28 in FIG. 2, with greater detail regarding the preferred BiCMOS process technology being shown in FIGS. 9 – 10, particular step 414 of FIG. 10);
a source and a drain in a well in the first region (see id., particularly step 416 of FIG. 10 regarding the S/D, and steps 410 and 412 of FIG. 10 regarding the well);
a device isolation layer in the substrate at a boundary between the first region and a second region (see FIGS. 1 – 3 and col. 4, l. 8 – col. 5, l. 34, isolation trench 26 forming a boundary between the first region (28) and a second (guard ring) region 36);
a trap layer comprising poly-silicon or amorphous silicon on the substrate in the second region (see FIGS. 2 – 3 and 8, col. 4, ll. 26 – 54, and col. 6, ll. 55 – 65, collector layer 48 which is disposed on layer 46 of substrate 22 as the trap layer; see also FIGS. 9 – 10, and col. 7, l. 37 – col. 8, l. 13, describing poly-silicon deposition / doping in the second region, which would form part of the trap layer when the process of FIGS. 9 – 10 are used to fabricate the inventive device);
a pre-metal dielectric (PMD) layer on the trap layer and the substrate (see FIGS. 9 – 10, col. 8, ll. 13 – 16, step 426); and
a plurality of metal wires spaced apart from each other on the PMD layer (see FIGS. 2 and 9 – 10, col. 8, ll. 13 – 16, and col. 4, ll. 26 – 54, conductors 52 and step 426),
wherein the trap layer vertically overlaps one of the metal wires in the second region (see FIGS. 2 and 9, illustrating the relative positioning of the conductors 52 (i.e., metallization in the context of the suggested BiCMOS process of FIG. 9)).
While FIG. 2 of Seefeldt does not explicitly disclose details of the claimed gate, S/D regions, and well in the context of the inventive embodiment, it is shown in FIGS. 9 – 10 and described at col. 7, ll. 5 – 30 that it is desirable to use a BiCMOS process such as illustrated in FIGS. 9 – 10 or in various prior art patents such as Kumauchi at FIGS. 1 – 4 (col. 5, l. 66 – col. 8, l. 25) in order to manufacture the inventive embodiment. Moreover, while Seefeldt does not explicitly disclose a resistivity of substantially greater than 1,000 ohm•cm, it does disclose “[t]he support substrate 40 is preferably formed of a high resistivity (or high Z) substrate having a high ohm per centimeter rating, such as for example, a 1 KΩ per centimeter substrate” at col. 4, ll. 33 – 36.
As noted above, obviousness can be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so. (See In re Kahn, supra; MPEP 2143.01.) Seefeldt itself, as noted above, provides a clear teaching and suggestion to use the process described in, e.g., Kumauchi, to fabricate the inventive embodiment. Moreover, given the uncertainly of “substantially greater” as set forth above, with respect to the resistivity of the substrate, it is noted that a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. (See Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 783 (Fed. Cir. 1985); MPEP 2144.05(I).) Accordingly, it would have been prima facie obvious to a person having ordinary skill in the art before the effective filing date of the present application to have used the BiCMOS process taught in Kumauchi or FIGS. 9 – 10 of Seefeldt to fabricate the inventive embodiment of Seefeldt.
Regarding claim 7, Seefeldt in view of Kumauchi is relied on for the RF switch device of claim 6 as above, and Seefeldt further discloses wherein a plurality of the metal wires are in the second region (see Seefeldt, FIG. 2, wherein two wires 52 are illustrated in the second region).
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Regarding claims 8 – 10, Seefeldt in view of Kumauchi is relied on for the RF switch of claim 7 as above, however, given the uncertainty of “the trap layer between adjacent ones of the metal wires in the second region” as noted above, as best can be understood from Seefeldt, FIG. 1 (reproduced below for reference), the trap layer (36, 38) between adjacent ones of the metal wires in the second region may be fairly said to have either a grid shape or a plurality of regularly-spaced openings (claim 8), a stripe shape or a line shape (claim 9, referring to any of the four sides of 36, 38), or a substantially square or island shape (claim 10).
Regarding claim 12, Seefeldt discloses an RF switch device (see FIGS. 1 – 3 and col. 1, ll. 17 – 21, device 20), comprising:
a high resistivity substrate (see FIG. 2 and col. 4, ll. 26 – 54, substrate 22, particularly including layers 40, 42, 44, and 46 as further described at col. 6, ll. 8 – 37); see also FIG. 6);
a plurality of stacks, wherein each of the plurality of stacks has a gate on the substrate and a source and a drain in a well in a first region of the substrate (see FIGS. 2 and 9 – 10, and col. 7, l. 5 – col. 8, l. 16, wherein the first region is the first device mesa 28 in FIG. 2, with greater detail regarding the preferred BiCMOS process technology being shown in FIGS. 9 – 10, particular step 414 of FIG. 10; see also id., particularly step 416 of FIG. 10 regarding the S/D, and steps 410 and 412 of FIG. 10 regarding the well) (herein it is noted that the term “a plurality of stacks” is interpreted herein as a plurality of gate stacks, i.e., including at least gate oxide and a conductive gate, as there is no limitation in the claim as to the orientation or positioning of the “stacks” with respect to one another);
a device isolation layer in the substrate at a boundary between the first region and a second region (see FIGS. 1 – 3 and col. 4, l. 8 – col. 5, l. 34, isolation trench 26 forming a boundary between the first region (28) and a second (guard ring) region 36);
a trap layer comprising poly-silicon or amorphous silicon on the substrate in the second region (see FIGS. 2 – 3 and 8, col. 4, ll. 26 – 54, and col. 6, ll. 55 – 65, collector layer 48 which is disposed on layer 46 of substrate 22 as the trap layer; see also FIGS. 9 – 10, and col. 7, l. 37 – col. 8, l. 13, describing poly-silicon deposition / doping in the second region, which would form part of the trap layer when the process of FIGS. 9 – 10 are used to fabricate the inventive device);
a pre-metal dielectric (PMD) layer on the trap layer and the substrate (see FIGS. 9 – 10, col. 8, ll. 13 – 16, step 426); and
a plurality of metal wires spaced apart from each other on the PMD layer (see FIGS. 2 and 9 – 10, col. 8, ll. 13 – 16, and col. 4, ll. 26 – 54, conductors 52 and step 426),
wherein the trap layer vertically overlaps one of the metal wires in the second region (see FIGS. 2 and 9, illustrating the relative positioning of the conductors 52 (i.e., metallization in the context of the suggested BiCMOS process of FIG. 9)).
While FIG. 2 of Seefeldt does not explicitly disclose details of the claimed gate, S/D regions, and well in the context of the inventive embodiment, it is shown in FIGS. 9 – 10 and described at col. 7, ll. 5 – 30 that it is desirable to use a BiCMOS process such as illustrated in FIGS. 9 – 10 or in various prior art patents such as Kumauchi at FIGS. 1 – 4 (col. 5, l. 66 – col. 8, l. 25) in order to manufacture the inventive embodiment.
As noted above, obviousness can be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so. (See In re Kahn, supra; MPEP 2143.01.) Seefeldt itself, as noted above, provides a clear teaching and suggestion to use the process described in, e.g., Kumauchi or FIGS. 9 – 10 of Seefeldt, to fabricate the inventive embodiment. Accordingly, it would have been prima facie obvious to a person having ordinary skill in the art before the effective filing date of the present application to have used the BiCMOS process taught in Kumauchi to fabricate the inventive embodiment of Seefeldt.
Regarding claim 13, Seefeldt in view of Kumauchi is relied on for the RF switch device of claim 12 as above, and Seefeldt further discloses wherein the trap layer is in a space between two of the stacks (see Seefeldt, FIG. 1, relative positioning of features 24, 26, 28, and 36; and 30, 32, 34, and 38).
Regarding claim 14, Seefeldt in view of Kumauchi is relied on for the RF switch device of claim 12 as above, and Seefeldt, FIG. 9, illustrates the relative proportions of the metallization outside of the first (CMOS) region as would be applied to the inventive device of FIG. 2, such that the trap layer has a width greater than that of the one metal wire in the second region.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure:
Kjar, Raymond A., US 2008/0217727 A1, disclosing an electrically charged field control ring situated over a buried oxide layer and surrounding an SOI transistor. The electrically charged field control ring reduces a conductivity of a surface portion of the bulk substrate underlying the field control ring, thereby minimizing RF coupling of the at least one SOI transistor through the bulk substrate.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Ryan Fortin whose telephone number is 703-756-5649. The examiner can normally be reached on Monday – Friday from 8:30 AM to 12:30 PM and from 2:30 PM to 6:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo, can be reached at telephone number 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/R.T.F./
Examiner, Art Unit 2897
/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897