DETAILED ACTION
The response filed on January 12, 2026 is being acknowledged.
Submitted claims on 01/12/2026 are directed to an invention that is independent or distinct from the invention originally claimed for the following reasons:
the original claims represent subject matter of circuit board while submitted claims represent claims directed to cable with a circuit board and furthermore, it appears to have limitation “an isolation loop forming an arc in the conducting layer extending between two connector contacts and surrounding the end of the first signal line proximate to the contact” is not solely part of the circuit board. For example, an adhesive tape which also can be used anywhere other than wire, while a wire harness having a wire with an adhesive tape around the wire are two different products. See further MPEP.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 1-4, 7-8, 12-14, 29-31, 33, and 39-40 (all claims) are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03. Therefore, there are no claims for prosecution, as well as considering appeal, and arguments.
The rejection under USC 112 and/or USC 103 below is given based on original claim representation with modified language are given to advance prosecution; however, proper clarification and amendment is required based on original claim representation in order to consider the rejections below.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-4, 7-8, 12-14, 29-31, 33, and 39-40 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Rejection of claims 1 and 29, the limitation “a contact positioned at an end of the first signal line, and an isolation loop forming an arc in the conducting layer extending between two connector contacts and surrounding the end of the first signal line proximate to the contact” contains subject matter which was not described in the specification.
Specification only mentions that “the cable 50 may include ground plane
loops (e.g., loop 506 as shown in Fig. 6) to further isolate the signal lines (e.g., signal line 504) by surrounding the respective signal lines in a semi-circle or arc and thereby provide intra-contact cross talk shielding”; however, specification do not clearly mention that “arc or loop” is part of the circuit board.
Therefore, the limitation contains new matter which was not described in the specification.
Rejection of claims 2-4, 7-8, 12-14, 30-31, 33, and 39-40, claims 2-4, 7-8, 12-14, 30-31, 33, and 39-40 are rejected by the same reason applied to the rejection of claims 1 or 29.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7-8, are rejected under 35 U.S.C. 103 as being unpatentable over CN207802499 (hereinafter referred to as CN20) or Kobayashi et al. (US6040524, hereinafter referred to as Kobayashi) in view of Nakamura et al. (US2005230813, hereinafter referred to as Nakamura) or Jain et al. (US6133805, hereinafter referred to as Jain).
Referring to claim 1, CN20 or Kobayashi discloses a flexible printed (see figures 7,9, 11-13 and figures 3a-3d of CN 20, or See figure 10 and specification of Kobayashi), comprising:
a conducting layer including a first signal line (S1, see figures 7,9, 11-13 and figures 3a-3d of CN 20, note that similar explanation apply to Kobayashi), a first ground plane (one of 130a or 130b in part 100a) and a second ground plane (another of 130a or 130b , note that other figure all reads on the claim as based on interpreted differently );
a first ground plane layer (one of 150 or 140) including a third ground plane (a part 150a or 140a of one of 150 or 140 defined by 100a provided at above S1 );
a second ground plane layer (another of 150 or 140) including a fourth ground plane (a respective part 150a or 140a of another of 150 or 140 defined by 100a provided below S1 ); ; and
a first shielding via (a VH at the one of 130a or 130b based on corresponding figures, for example in figure ) extending from the third ground plane to the fourth ground plane and extending through the first ground plane to electrically connect the first ground plane, the third ground plane and the fourth ground plane (140a, and 150a); and
a second shielding via (a VH at the another of 130a or 130b based on corresponding figures, for example figure 7, where first and second Via passing from 130a and 130b in both side of S1 in part 100a, while in figure 9, first and second Via passing from 130a and 130a in both side of S1 in part 100a, similar explanation apply to other figures and components or parts ) extending from the third ground plane to the fourth ground plane and extending through the second ground plane to electrically connect the second ground plane, the third ground plane) and the fourth ground plane (140a and 150a),
the first ground plane, the second ground plane, the third ground plane, the fourth ground plane , the first shielding via and the second shielding via, together, circumferentially surrounding the first signal line to minimize electromagnetic interference with the first signal line (see part of 100a in the figures);
a fifth ground plane (one of 130b or 130c in part 100c ) and a sixth ground plane (another of 130b or 130c in part 100c), a second signal line (S3) at the conducting layer, the second signal line being separate and distinct from the first signal line (S1 and S3 are separated) ;
a seventh ground plane (one of 150c or 140c of one of 150 or 140 defined by 100c provided above S3 ) at the first ground plane layer (the one of 150 or 140);
an eighth ground plane (another 150c or 140c of the another of 150 or 140 defined by 100c provided below S3 ) at the second ground plane layer (the another of 150 or 140);
a third shielding via (a VH at the one of 130b or 130c based on corresponding figures)extending from the seventh ground plane to the eighth ground plane and extending the fifth ground plane to electrically connect the fifth ground plane, the seventh ground plane and the eighth ground plane (140c and 150c); and
a fourth shielding via extending from the seventh ground plane to the eighth ground plane and extending the sixth ground plane to electrically connect the sixth ground plane, the seventh ground plane and the eighth ground plane (a VH at the another of 130b or 130c based on corresponding figures, for example figure 7, where third and fourth Via passing from 130b and 130c in both side of S3 in part 100c, while in figure 9, first and second Via passing from 130c and 130c in both side of S3 in part 100c, similar explanation apply to other figures and components or parts ),
the fifth ground plane, the sixth ground plane, the seventh ground plane, the eighth ground plane, the second shielding via and the third shielding via, together, circumferentially surrounding the second signal line to minimize electromagnetic interference with the second signal line (see part 11c in the figures of CN20) ( similar explanation of CN20 apply to for signal line 146’a and 146’c with ground planes in figure 10 of Kobayashi).
CN20 or Kobayashi fails to disclose a contact positioned at an end of the first signal line, and an isolation loop forming an arc in the conducting layer extending between two connector contacts and surrounding the end of the first signal line proximate to the contact.
Nakamura or Jain discloses a contact positioned at an end of the first signal line, and an isolation loop forming an arc in the conducting layer and surrounding the end of the first signal line proximate to the contact (see the ground guard pattern 17 includes a pair of straight pattern 17 a extending in parallel with the signal line pattern 16 located in a space interposed between the straight patterns 17 a, 17 a, and a circular pattern 17 b extending along an imaginary circle 18 concentric with the via 15 so as to connect the tip ends of the straight patterns 17a, 17a to each other in figure 2 of Nakamura; or see isolation loops of 906 and 907 the figure 9 of Jain forming an arc in the conducting layer including 905 and 910 and surrounding the end of the first signal line 905 proximate to the contact 910 )
It would have been obvious to ordinary skill in the art before the effective filing date of claimed invention to modify the circuit board of CN20 or Kobayashi to have arrangement as taught by Nakamura or Jain by doing so it will increase area of shielding around signal line or at the end signal line to further improve shielding of the signal line or maintain signal interiority or reliability at that area, and/or the characteristic impedance can thus be controlled in a more efficient manner, a noise can sufficiently be suppressed in electric signals of the board.
Referring to claim 2, CN20 or Kobayashi in view of Nakamura or Jain disclose the flexible printed circuit board of claim 1, wherein the first signal line is positioned between the first ground plane (13) and the second ground plane (see explanation in rejection of claim 1, and see part 100a in the figures of CN20, or see figure 10 of Kobayashi).
Referring to claim 3, CN20 or Kobayashi in view of Nakamura or Jain disclose the flexible printed circuit board of claim 1, wherein the first signal line is positioned between the third ground plane and the fourth ground plane (see explanation in rejection of claim 1, and see part 100a in the figures, or see figure 10 and specification of Kobayashi).
Referring to claim 4, CN20 or Kobayashi in view of Nakamura or Jain disclose the flexible printed circuit board of claim 1, wherein the first signal line is positioned between the first shielding via and the second shielding via (see explanation in rejection of claim 1, and see part 100a in the figures, or see figure 10 and specification of Kobayashi).
Referring to claim 7, CN20 or Kobayashi in view of Nakamura or Jain disclose the flexible printed circuit board of claim 1, further comprising: a first dielectric plane positioned between the first signal line and the third ground plane (an insulating layer between S1 and the part 150a or 140a of the one of 150 or 140 defined by 100a provided at above S1, see the figures).
Referring to claim 8, CN20 or Kobayashi in view of Nakamura or Jain disclose the flexible printed circuit board of claim 1, further comprising: a second dielectric plane positioned between the first signal line and the fourth ground plane (an insulating layer between S1 and the another part 150a or 140a of the another of 150 or 140 defined by 100a provided at above S1, see the figures).
Referring to claims 2-4 and 7-8, examiner makes also office notice that dielectrics as mentioned in claims 2-8 around signal lines and between signal line and ground plane are common in circuit board with transmission lines in order to distance and shield from each other, as well as prevent short circuit between them.
Referring to claim 39, CN20 or Kobayashi in view of Nakamura or Jain disclose a ground plane loop that couples the first ground plane and the second ground plane and surrounds the first signal line in a semi-circle or arc (see curve portion connecting ground pair of 17a the figure 2 of Nakamura; or see curve portion connecting 906 and 907 the figure 9 of Jain as mention in the independent claim above).
Claims 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over (CN20 or Kobayashi) and (Jain or Nakamura) and further in view of Schreiber et al. (US4845311, herein referred to as Schreiber) or Chung et al. (US20160007445, herein referred to as Chung).
Referring to claims 12 and 14, CN20 or Kobayashi in view of Nakamura or Jain disclose the flexible printed circuit board of claim 1, but fails to disclose a dielectric plane positioned between the third ground plane and the seventh ground plane at the first ground plane layer to electromagnetically isolate the third ground plane and the seventh ground plane; and a dielectric plane positioned between the fourth ground plane and the eighth ground plane at the second ground plane layer to electromagnetically isolate the fourth ground plane and the eighth ground plane.
Schreiber or Chung discloses a dielectric plane positioned between the third ground plane and the seventh ground plane at the first ground plane layer to electromagnetically isolate the third ground plane and the seventh ground plane (a dielectric plane between top spitted ground conductor 76 of return line 74 in figure 18-19 in view of figures 11-12 in Schreiber; or a top 31a between two group planes in figures 9-10 of Chung); and a dielectric plane positioned between the fourth ground plane and the eighth ground plane at the second ground plane layer to electromagnetically isolate the fourth ground plane and the eighth ground plane (a dielectric plane between bottom spitted conductor 75 of return line 74 in figure 18-19 in view of figures 11-12 in Schreiber; or a bottom 31a between two group planes in figures 9-10 of Chung).
It would have been obvious to ordinary skill in the art before the effective filing date of claimed invention to modify the circuit board of CN20 or Kobayashi in view of Nakamura or Jain to have arrangement of dielectric plane as taught by Schreiber or Chung by doing so the present invention is capable of suppressing interference such as the Electromagnetic Interference (EMI) or the Radio Frequency Interference (RFI) of the each signal efficiently and more economical way by reducing amount of metal used to make ground plane and/or capable of transmitting signals in the high frequency range without appreciable signal loss and providing high density packaging.
Claims 29-31, 33, and 40 are rejected under 35 U.S.C. 103 as being unpatentable over Kuzmina et al. (US7186922, hereinafter referred to as Kuzmina) and CN20 or Kobayashi (as mentioned above in rejection of claim 1).
Referring to claim 29, Kuzmina discloses a printed circuit board including: a conducting layer including a first signal line and a second signal, the first signal line having a first physical length and a first electrical length and the second signal line having a second physical length and a second electrical length, the physical length of the first signal line being different from the physical length of the second signal line such that a difference between the first electrical length and the second electrical length is less than one electrical degree (see claim 20 and also specification mentions that the signals arrive at the pins exactly at the same time, specification do mention that how to adjust electrical length to be same even if different physical length, traces will have the same electrical length, even if geometrical length is different. Also, specification mentions that delay in each bit line between the controller and the DIMM must be the same ).
Kuzmina fails to disclose the flexible printed circuit board, wherein the conducting layer includes: a first ground plane, a second ground plane, a third ground plane and a fourth ground plane, wherein the first signal line is positioned between the first ground plane and the second ground plane and wherein the second signal line is positioned between the third ground plane and the fourth ground plane;
a contact positioned at an end of the first signal line, and an isolation loop forming an arc in the conducting layer and surrounding the end of the first signal line proximate to the contact.
CN20 or Kobayashi disclose the flexible printed circuit board, wherein the conducting layer includes: a first ground plane, a second ground plane, a third ground plane and a fourth ground plane, wherein the first signal line is positioned between the first ground plane and the second ground plane and wherein the second signal line is positioned between the third ground plane and the fourth ground plane (see rejection of claim 1 for explanation).
It would have been obvious to ordinary skill in the art before the effective filing date of claimed invention to modify the circuit board of Kuzmina and to have structural arrangement as taught by (CN20 or Kobayashi) in order to reduce noise, disturbance, or electromagnetic interferences which maintains or improves signal lines signal integrity or reliability as well as provide common grounding.
Nakamura or Jain discloses a contact positioned at an end of the first signal line, and an isolation loop forming an arc in the conducting layer and surrounding the end of the first signal line proximate to the contact (see the ground guard pattern 17 includes a pair of straight pattern 17 a extending in parallel with the signal line pattern 16 located in a space interposed between the straight patterns 17 a, 17 a, and a circular pattern 17 b extending along an imaginary circle 18 concentric with the via 15 so as to connect the tip ends of the straight patterns 17a, 17a to each other in figure 2 of Nakamura; or see isolation loops of 906 and 907 the figure 9 of Jain forming an arc in the conducting layer including 905 and 910 and surrounding the end of the first signal line 905 proximate to the contact 910 )
It would have been obvious to ordinary skill in the art before the effective filing date of claimed invention to modify the circuit board of Kuzmina in view of (CN20 or Kobayashi) to have arrangement as taught by Nakamura or Jain by doing so it will increase area of shielding around signal line or at the end signal line to further improve shielding of the signal line or maintain signal interiority or reliability at that area, and/or the characteristic impedance can thus be controlled in a more efficient manner, a noise can sufficiently be suppressed in electric signals of the board.
Referring to claim 30, Kuzmina in view of (CN20 or Kobayashi) and (Nakamura or Jain) disclose the flexible printed circuit board of claim 29, wherein the physical length of the first signal line being different from the physical length of the second signal line such that a difference between the first electrical length and the second electrical length is less than one- half of an electrical degree (see rejection of claim 29 above).
Referring to claim 31, Kuzmina in view of (CN20 or Kobayashi) and (Nakamura or Jain) disclose the flexible printed circuit board of claim 29, wherein the physical length of the first signal line being different from the physical length of the second signal line such that a difference between the first electrical length and the second electrical length is less than one- quarter of an electrical degree (see rejection of claim 29 above).
Referring to claim 33, Kuzmina in view of (CN20 or Kobayashi) and (Nakamura or Jain) disclose the flexible printed circuit board of claim 29, but fail to disclose further comprising: a first dielectric layer and a second dielectric layer, the first signal line and the second signal line being positioned between the first dielectric layer and the second dielectric layer.
CN20 or Kobayashi disclose a first dielectric layer and a second dielectric layer, the first signal line and the second signal line being positioned between the first dielectric layer and the second dielectric layer (see the figures of CN20 or Kobayashi).
It would have been obvious to ordinary skill in the art before the effective filing date of claimed invention to modify the circuit board of Kuzmina in view of (CN20 or Kobayashi) and (Nakamura or Jain) to have structural arrangement as taught by CN20 or Kobayashi because each of these coaxial structures is surrounded by additional isolating dielectric materials and a 360-degree layer of conductive material for shielding each of the coaxial structures and having structure without appreciable signal loss and providing high density packaging.
Referring to claim 33, examiner makes also office notice that dielectrics as mentioned in claim 33 around signal lines and between signal lines and ground plane are common in circuit board with transmission lines in order to distance and shield from each other, as well as prevent short circuit between them.
Referring to claim 40, Kuzmina in view of (CN20 or Kobayashi) and (Nakamura or Jain) disclose the flexible printed circuit board of claim 29, a ground plane loop that couples the first ground plane and the second ground plane and surrounds the first signal line in a semi-circle or arc (see curve portion connecting ground pair of 17a the figure 2 of Nakamura; or see curve portion connecting 906 and 907 the figure 9 of Jain as mention in the independent claim above).
Pertinent Prior Arts
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Please refer to enclosed PTO-892 from for the citation of the pertinent art in the present case.
Response to Arguments
Applicant’s arguments with respect to claim(s) are not considered because applicants argument based on the non-elected subject matter which is withdrawn. Currently, no claim for prosecution based on by the original presentation as well as arguments.
Communication
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PARESH PAGHADAL whose telephone number is (571)272-5251. The examiner can normally be reached on 7:00AM-4:00PM, Monday - Thursday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached on (571)272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PARESH PAGHADAL/Primary Examiner, Art Unit 2847