DETAILED ACTION
The response filed on August 03, 2026 is being acknowledged.
Specification
The disclosure is objected to because of the following informalities:
See paragraphs below:
[0058] FIG. 5 is a conceptual top cross-section of a flexible printed circuit board, according to an exemplary embodiment of the invention; and
[0059] FIG. 6 is a magnified view 6-6 of a portion of FIG. 5.
[0061]A flexible printed circuit board (FPCB) may be preferred over coaxial cable because the FPCB is more compact.
[0063] Referring to the drawings in detail, wherein like reference numerals indicate like elements throughout, there is shown in FIGS. 1-6, respectively, a flexible printed circuit board (FPCB) 10, and FPCB 20, a method 30 for manufacturing a FPCB, a FPCB 40 and a cable 50,
[00156] Referring now to FIG. 5, there is shown a top cross-section of a cable 50 along A to A′ of FIG. 4, according to an exemplary embodiment of the invention. While the cable 50 is illustrating the FPCB 40 of FIG. 4, the cable 50 may include other FPCBs, including FPCB 10 and FPCB 20. The cable 50 may include a first connector 502 and/or a second connector 504. The cable 50 may include one or more signals lines (e.g., signal line 404) and/or guard traces (e.g., ground traces 403 a-b) that extend from the first connector 502 to the second connector 504. The first connector 502 and/or the second connector 504 may be a rigid printed circuit board. The first connector 502 and/or the second connector 504 may include one or more connector elements (e.g., pins, wires, contacts, zero insertion force connectors, etc.) that electrically couple the cable 50 to an external electrical device, such that when the first connector 502 and the second connector 504 is connected to first and second external devices.
[0157] Each of the signal lines, and/or guard traces may be centered on, and perpendicular to, a connector pitch. As used herein, connector pitch may refer to the center line extending between at least two connector contacts (e.g., contacts 505 a-b as shown in FIG. 6) of the connector (e.g., second connector 504).
[0158] the cable 50 may include ground plane loops (e.g., loop 506 as shown in FIG. 6) to further isolate the signal lines (e.g., signal line 504) by surrounding the respective signal lines in a semi-circle or arc and thereby provide intra-contact cross talk shielding. In some embodiments, connector 502 and/or connector 504 may be coupled to one or more ground planes to shield the connector from electromagnetic interference.
The specification (from above paragraphs) states that the cable 50 illustrates the FPCB 40, but the relationship between the two is not clear – is the cable the same as FPCB 40? Or is FPCB part of cable 50?; no clear boundary between cable and FPCB is disclosed in the specification to identify the cable and the FPCB.
Appropriate action is required (no new matter should be added)
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show Fig. 5. “Para [0057] states that it is a cross section of a FPCB, and para [0156] states that “the cable 50 is illustrating the FPCB 40 of Fig. 4.” Wherein FPCB 40 should be labeled in Fig. 5 to illustrate which parts illustrated form the FPCB vs. the cable as described in the specification or claim. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-4, 7-8, 12-14, 29-31, 33, and 39-42 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Rejection of claims 1 and 29, the limitation “a flexible printed circuit board, comprising: …. an isolation loop forming an arc in the conducting layer extending between two connector contacts and surrounding the end of the first signal line proximate to the contact” is failing to contain subject matter which was not described in the specification.
From paragraphs above, cable includes connection contacts 505a-505b, and loop 506; now where in specification supports this structure is part of any FCPB.
But if see figures 5-6 which is just cable 50, also there no boundary or numerical defined between FCPB 40 and Cable 50 , or even do not mentions that FCPB inserted hole or cavity of cable; furthermore, It is not clear how FCPB placed in the cable or is it even placed within the cable or it may be placed on the cable; also, from figure 5, one of the ordinary skill can not decide what is part of cable and FCPB without proper boundary because specification states that cable 50 includes one or more signals lines (e.g., signal line 404) and/or ground traces (e.g., ground traces 403 a-b) as well as additional structure not common to both cable 50 and FPCB 40.
furthermore, paragraph 0156-158 discloses cable 50 includes The first connector 502 and/or the second connector 504 may include one or more connector elements; the cable 50 may include ground plane loops (e.g., loop 506 as shown in FIG. 6) to further isolate the signal lines (e.g., signal line 504) by surrounding the respective signal lines in a semi-circle or arc and thereby provide intra-contact cross talk shielding. In some embodiments, connector 502 and/or connector 504 may be coupled to one or more ground planes to shield the connector from electromagnetic interference.
And connector pitch may refer to the center line extending between at least two connector contacts (e.g., contacts 505 a-b as shown in FIG. 6) of the connector (e.g., second connector 504). (This description is also under cable in paragraphs 0156-0158). Therefore, FCPC has no clear support for having two connector contacts contacts 505 a-b and loop 506.
The spec does not make clear that the isolation loop is part of the FPCB as opposed to the cable.
Therefore, the claims contain new matter.
Rejection of claims 2-4, 7-8, 12-14, 30-31, 33, and 39-42, these claims are rejected by same reason applied to rejection of claim 1 or 29 above.
Rejection of claims 39-40, the limitation “a ground plane loop that couples the first ground plane and the second ground plane and surrounds the first signal line in a semi-circle or arc” is failing to contain subject matter which was not described in the specification.
Claim 1 or 29 already discloses an isolation loop, it appears to be second loop as a ground plane loop couples the first ground plane and the second ground plane. Specification do not disclose an isolation loop and a ground plane loop.
Therefore, the claims contain new matter.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4, 7-8, 12-14, 29-31, 33, and 39-42 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Rejection of claims 1 and 29, the limitation “a flexible printed circuit board, comprising: …. an isolation loop forming an arc in the conducting layer extending between two connector contacts and surrounding the end of the first signal line proximate to the contact” is indefinite for failing to particularly point out and distinctly claim the subject matter.
The claims are indefinite because the claims do not specify that the FPCB includes the isolation loop, but the spec describes the isolation loop as being a part of the cable, not the FPCB (see further explanation in objection of specification as well as rejection under USC 112 new matter above).
Additionally, claim lacks essential structural relation between the isolation loop and the first and the second ground planes via by the two connector contacts. Specification is limited to the isolation loop and the first and the second ground planes connected to each other by the two connector contacts but the claim is open ended and which currently readd on the two connector contacts connected not connected anything other than isolation loop (note that it is considered as a new matter ), therefore, it is required claim to have essential structure mentioned in the claim.
Therefore, the claims are indefinite.
Rejection of claims 2-4, 7-8, 12-14, 30-31, 33, and 39-42, these claims are rejected by same reason applied to rejection of claim 1 or 29 above.
Rejection of claims 39-40, the limitation “a ground plane loop that couples the first ground plane and the second ground plane and surrounds the first signal line in a semi-circle or arc” is indefinite for failing to particularly point out and distinctly claim the subject matter.
Claim 1 or 29 already discloses an isolation loop, Specification does not disclose two loops: an isolation loop and a ground plane loop, and do not mention how it is connected to the first ground plane and the second ground plane at same end of the first ground plane and the second ground plane, or one of the isolation loop and the ground plane loop connect to one ends of the first ground plane and the second ground plane and another of the isolation loop and the ground plane loop connect to another ends of the first ground plane and the second ground plane.
Therefore, the claims are indefinite.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7-8, are rejected under 35 U.S.C. 103 as being unpatentable over CN207802499 (hereinafter referred to as CN20) or Kobayashi et al. (US6040524, hereinafter referred to as Kobayashi) in view of Wei et al. (US20120247825, hereinafter referred to as Nakamura) or Jow et al. (US8058956, hereinafter referred to as Jow).
Referring to claim 1, CN20 or Kobayashi discloses a flexible printed (see figures 7,9, 11-13 and figures 3a-3d of CN 20, or See figure 10 and specification of Kobayashi), comprising:
a conducting layer including a first signal line (S1, see figures 7,9, 11-13 and figures 3a-3d of CN 20, note that similar explanation apply to Kobayashi), a first ground plane (one of 130a or 130b in part 100a) and a second ground plane (another of 130a or 130b , note that other figure all reads on the claim as based on interpreted differently );
a first ground plane layer (one of 150 or 140) including a third ground plane (a part 150a or 140a of one of 150 or 140 defined by 100a provided at above S1);
a second ground plane layer (another of 150 or 140) including a fourth ground plane (a respective part 150a or 140a of another of 150 or 140 defined by 100a provided below S1 ); ; and
a first shielding via (a VH at the one of 130a or 130b based on corresponding figures, for example in figure ) extending from the third ground plane to the fourth ground plane and extending through the first ground plane to electrically connect the first ground plane, the third ground plane and the fourth ground plane (140a, and 150a); and
a second shielding via (a VH at the another of 130a or 130b based on corresponding figures, for example figure 7, where first and second Via passing from 130a and 130b in both side of S1 in part 100a, while in figure 9, first and second Via passing from 130a and 130a in both side of S1 in part 100a, similar explanation apply to other figures and components or parts ) extending from the third ground plane to the fourth ground plane and extending through the second ground plane to electrically connect the second ground plane, the third ground plane) and the fourth ground plane (140a and 150a),
the first ground plane, the second ground plane, the third ground plane, the fourth ground plane , the first shielding via and the second shielding via, together, circumferentially surrounding the first signal line to minimize electromagnetic interference with the first signal line (see part of 100a in the figures);
a fifth ground plane (one of 130b or 130c in part 100c ) and a sixth ground plane (another of 130b or 130c in part 100c), a second signal line (S3) at the conducting layer, the second signal line being separate and distinct from the first signal line (S1 and S3 are separated);
a seventh ground plane (one of 150c or 140c of one of 150 or 140 defined by 100c provided above S3 ) at the first ground plane layer (the one of 150 or 140);
an eighth ground plane (another 150c or 140c of the another of 150 or 140 defined by 100c provided below S3 ) at the second ground plane layer (the another of 150 or 140);
a third shielding via (a VH at the one of 130b or 130c based on corresponding figures)extending from the seventh ground plane to the eighth ground plane and extending the fifth ground plane to electrically connect the fifth ground plane, the seventh ground plane and the eighth ground plane (140c and 150c); and
a fourth shielding via extending from the seventh ground plane to the eighth ground plane and extending the sixth ground plane to electrically connect the sixth ground plane, the seventh ground plane and the eighth ground plane (a VH at the another of 130b or 130c based on corresponding figures, for example figure 7, where third and fourth Via passing from 130b and 130c in both side of S3 in part 100c, while in figure 9, first and second Via passing from 130c and 130c in both side of S3 in part 100c, similar explanation apply to other figures and components or parts ),
the fifth ground plane, the sixth ground plane, the seventh ground plane, the eighth ground plane, the second shielding via and the third shielding via, together, circumferentially surrounding the second signal line to minimize electromagnetic interference with the second signal line (see part 11c in the figures of CN20) ( similar explanation of CN20 apply to for signal line 146’a and 146’c with ground planes in figure 10 of Kobayashi).
CN20 or Kobayashi fails to disclose a contact positioned at an end of the first signal line, and an isolation loop forming an arc in the conducting layer extending between two connector contacts and surrounding the end of the first signal line proximate to the contact.
Wei or Jow discloses a contact positioned at an end of the first signal line, and an isolation loop forming an arc (84 in figure 2 of Wei; or see 319 in figure 3D of Jow) in the conducting layer extending between two connector contacts (82 on both ends in Wei; see ends of 319 in Jow ) and surrounding the end of the first signal line proximate to the contact (see the figure of Wei; or the figure of Jow).
It would have been obvious to ordinary skill in the art before the effective filing date of claimed invention to modify the circuit board of CN20 or Kobayashi to have arrangement as taught by Wei or Jow by doing so it will increase area of shielding around signal line or at the end signal line to further improve shielding of the signal line or maintain signal interiority or reliability at that area, and/or the characteristic impedance can thus be controlled in a more efficient manner, a noise can sufficiently be suppressed in electric signals of the board.
Referring to claim 2, CN20 or Kobayashi in view of Wei or Jow disclose the flexible printed circuit board of claim 1, wherein the first signal line is positioned between the first ground plane (13) and the second ground plane (see explanation in rejection of claim 1, and see part 100a in the figures of CN20, or see figure 10 of Kobayashi).
Referring to claim 3, CN20 or Kobayashi in view of Wei or Jow disclose the flexible printed circuit board of claim 1, wherein the first signal line is positioned between the third ground plane and the fourth ground plane (see explanation in rejection of claim 1, and see part 100a in the figures, or see figure 10 and specification of Kobayashi).
Referring to claim 4, CN20 or Kobayashi in view of Wei or Jow disclose the flexible printed circuit board of claim 1, wherein the first signal line is positioned between the first shielding via and the second shielding via (see explanation in rejection of claim 1, and see part 100a in the figures, or see figure 10 and specification of Kobayashi).
Referring to claim 7, CN20 or Kobayashi in view of Wei or Jow disclose the flexible printed circuit board of claim 1, further comprising: a first dielectric plane positioned between the first signal line and the third ground plane (an insulating layer between S1 and the part 150a or 140a of the one of 150 or 140 defined by 100a provided at above S1, see the figures).
Referring to claim 8, CN20 or Kobayashi in view of Wei or Jow disclose the flexible printed circuit board of claim 1, further comprising: a second dielectric plane positioned between the first signal line and the fourth ground plane (an insulating layer between S1 and the another part 150a or 140a of the another of 150 or 140 defined by 100a provided at above S1, see the figures).
Referring to claims 2-4 and 7-8, examiner makes also office notice that dielectrics as mentioned in claims 2-8 around signal lines and between signal line and ground plane are common in circuit board with transmission lines in order to distance and shield from each other, as well as prevent short circuit between them.
Claims 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over (CN20 or Kobayashi) and (Wei or Jow) and further in view of Schreiber et al. (US4845311, herein referred to as Schreiber) or Chung et al. (US20160007445, herein referred to as Chung).
Referring to claims 12 and 14, CN20 or Kobayashi in view of Nakamura or Jain disclose the flexible printed circuit board of claim 1, but fails to disclose a dielectric plane positioned between the third ground plane and the seventh ground plane at the first ground plane layer to electromagnetically isolate the third ground plane and the seventh ground plane; and a dielectric plane positioned between the fourth ground plane and the eighth ground plane at the second ground plane layer to electromagnetically isolate the fourth ground plane and the eighth ground plane.
Schreiber or Chung discloses a dielectric plane positioned between the third ground plane and the seventh ground plane at the first ground plane layer to electromagnetically isolate the third ground plane and the seventh ground plane (a dielectric plane between top spitted ground conductor 76 of return line 74 in figure 18-19 in view of figures 11-12 in Schreiber; or a top 31a between two group planes in figures 9-10 of Chung); and a dielectric plane positioned between the fourth ground plane and the eighth ground plane at the second ground plane layer to electromagnetically isolate the fourth ground plane and the eighth ground plane (a dielectric plane between bottom spitted conductor 75 of return line 74 in figure 18-19 in view of figures 11-12 in Schreiber; or a bottom 31a between two group planes in figures 9-10 of Chung).
It would have been obvious to ordinary skill in the art before the effective filing date of claimed invention to modify the circuit board of CN20 or Kobayashi in view of Nakamura or Jain to have arrangement of dielectric plane as taught by Schreiber or Chung by doing so the present invention is capable of suppressing interference such as the Electromagnetic Interference (EMI) or the Radio Frequency Interference (RFI) of the each signal efficiently and more economical way by reducing amount of metal used to make ground plane and/or capable of transmitting signals in the high frequency range without appreciable signal loss and providing high density packaging.
Claims 29-31, 33, and 40 are rejected under 35 U.S.C. 103 as being unpatentable over Kuzmina et al. (US7186922, hereinafter referred to as Kuzmina), and CN20 or Kobayashi (as mentioned above in rejection of claim 1 above), and in view of Wei or Jow (as mentioned above in rejection of claim 1 above).
Referring to claim 29, Kuzmina discloses a printed circuit board including: a conducting layer including a first signal line and a second signal, the first signal line having a first physical length and a first electrical length and the second signal line having a second physical length and a second electrical length, the physical length of the first signal line being different from the physical length of the second signal line such that a difference between the first electrical length and the second electrical length is less than one electrical degree (see claim 20 and also specification mentions that the signals arrive at the pins exactly at the same time, specification do mention that how to adjust electrical length to be same even if different physical length, traces will have the same electrical length, even if geometrical length is different. Also, specification mentions that delay in each bit line between the controller and the DIMM must be the same ).
Kuzmina fails to disclose the flexible printed circuit board, wherein the conducting layer includes: a first ground plane, a second ground plane, a third ground plane and a fourth ground plane, wherein the first signal line is positioned between the first ground plane and the second ground plane and wherein the second signal line is positioned between the third ground plane and the fourth ground plane;
a contact positioned at an end of the first signal line, and an isolation loop forming an arc in the conducting layer and surrounding the end of the first signal line proximate to the contact.
CN20 or Kobayashi disclose the flexible printed circuit board, wherein the conducting layer includes: a first ground plane, a second ground plane, a third ground plane and a fourth ground plane, wherein the first signal line is positioned between the first ground plane and the second ground plane and wherein the second signal line is positioned between the third ground plane and the fourth ground plane (see rejection of claim 1 for explanation).
It would have been obvious to ordinary skill in the art before the effective filing date of claimed invention to modify the circuit board of Kuzmina and to have structural arrangement as taught by (CN20 or Kobayashi) in order to reduce noise, disturbance, or electromagnetic interferences which maintains or improves signal lines signal integrity or reliability as well as provide common grounding.
Wei or Jow discloses a contact positioned at an end of the first signal line, and an isolation loop forming an arc (84 in figure 2 of Wei; or see 319 in figure 3D of Jow) in the conducting layer extending between two connector contacts (82 on both ends in Wei; see ends of 319 in Jow ) and surrounding the end of the first signal line proximate to the contact (see the figure of Wei; or the figure of Jow).
It would have been obvious to ordinary skill in the art before the effective filing date of claimed invention to modify the circuit board of CN20 or Kobayashi to have arrangement as taught by Wei or Jow by doing so it will increase area of shielding around signal line or at the end signal line to further improve shielding of the signal line or maintain signal interiority or reliability at that area, and/or the characteristic impedance can thus be controlled in a more efficient manner, a noise can sufficiently be suppressed in electric signals of the board.
Referring to claim 30, Kuzmina in view of (CN20 or Kobayashi) and (Wei or Jow) disclose the flexible printed circuit board of claim 29, wherein the physical length of the first signal line being different from the physical length of the second signal line such that a difference between the first electrical length and the second electrical length is less than one- half of an electrical degree (see rejection of claim 29 above).
Referring to claim 31, Kuzmina in view of (CN20 or Kobayashi) and (Wei or Jow) disclose the flexible printed circuit board of claim 29, wherein the physical length of the first signal line being different from the physical length of the second signal line such that a difference between the first electrical length and the second electrical length is less than one- quarter of an electrical degree (see rejection of claim 29 above).
Referring to claim 33, Kuzmina in view of (CN20 or Kobayashi) and (Wei or Jow) disclose the flexible printed circuit board of claim 29, but fail to disclose further comprising: a first dielectric layer and a second dielectric layer, the first signal line and the second signal line being positioned between the first dielectric layer and the second dielectric layer.
CN20 or Kobayashi disclose a first dielectric layer and a second dielectric layer, the first signal line and the second signal line being positioned between the first dielectric layer and the second dielectric layer (see the figures of CN20 or Kobayashi).
It would have been obvious to ordinary skill in the art before the effective filing date of claimed invention to modify the circuit board of Kuzmina in view of (CN20 or Kobayashi) and (Wei or Jow) to have structural arrangement as taught by CN20 or Kobayashi because each of these coaxial structures is surrounded by additional isolating dielectric materials and a 360-degree layer of conductive material for shielding each of the coaxial structures and having structure without appreciable signal loss and providing high density packaging.
Referring to claim 33, examiner makes also office notice that dielectrics as mentioned in claim 33 around signal lines and between signal lines and ground plane are common in circuit board with transmission lines in order to distance and shield from each other, as well as prevent short circuit between them.
It would have been obvious to ordinary skill in the art before the effective filing date of claimed invention to modify the circuit board of Kuzmina in view of (CN20 or Kobayashi) and (Wei or Jow) to have dielectric and by doing so it will increase area of shielding or protection around signal line or at the end signal line to further improve shielding or protection of the signal line or maintain signal interiority or reliability at that area, and/or the characteristic impedance can thus be controlled in a more efficient manner, a noise can sufficiently be suppressed in electric signals of the board.
Claim 39 is rejected under 35 U.S.C. 103 as being unpatentable over CN20 or Kobayashi (as mentioned above in rejection of claim 1), in view of (Wei or Jow) and further in view of Nakamura et al. (US20050247482, herein referred to as Nakamura).
Referring to claim 39, CN20 or Kobayashi in view of Wei or Jow discloses the flexible printed circuit board of claim 1, but fail to disclose further comprising; a ground plane loop that couples the first ground plane and the second ground plane and surrounds the first signal line in a semi-circle or arc.
Nakamura discloses a ground plane loop that couples the first ground plane and the second ground plane and surrounds the first signal line in a semi-circle or arc (loops at both ends in figure 20 of Nakamura where one of the loops as a ground plane loop coupled to 126 and 128).
It would have been obvious to ordinary skill in the art before the effective filing date of claimed invention to modify the circuit board to have conductor structure as taught by Nakamura and by doing so it will increase area of shielding to cover entire signal line with further improve shielding to have signal interiority or reliability and further reduces electromagnetic interference or noise.
Claim 40 is rejected under 35 U.S.C. 103 as being unpatentable over Kuzmina et al. (US7186922, hereinafter referred to as Kuzmina), and (CN20 or Kobayashi) (as mentioned above in rejection of claim 29), (Wei or Jow) and in view of Nakamura et al. (US20050247482, herein referred to as Nakamura).
Referring to claim 40, Kuzmina in view of (CN20 or Kobayashi) and (Wei or Jow) disclose the flexible printed circuit board of claim 29, but fail to disclose further comprising; a ground plane loop that couples the first ground plane and the second ground plane and surrounds the first signal line in a semi-circle or arc.
Nakamura discloses a ground plane loop that couples the first ground plane and the second ground plane and surrounds the first signal line in a semi-circle or arc (loops at both ends in figure 20 of Nakamura where one of the loops as a ground plane loop coupled to 126 and 128).
It would have been obvious to ordinary skill in the art before the effective filing date of claimed invention to modify the circuit board to have conductor structure as taught by Nakamura and by doing so it will increase area of shielding to cover entire signal line with further improve shielding to have signal interiority or reliability and further reduce electromagnetic interference or noise.
Claims 41-42 are rejected under 35 U.S.C. 103 as being unpatentable over CN20 or Kobayashi (as mentioned above in rejection of claim 1), in view of (Wei or Jow) and further in view of Chen et al. (US9847307, herein referred to as Chen).
Referring to claim 41, CN20 or Kobayashi in view of Wei or Jow disclose the flexible printed circuit board of claim 1, but fail to disclose wherein the isolation loop is electrically connected to the first ground plane and the second ground plane by the two connector contacts.
Chen discloses a ground plane loop that couples the first ground plane and the second ground plane and surrounds the first signal line in a semi-circle or arc (loop 214 in figures 1-2 in Chen connected to two conductors 34 by intermediate connection means 341).
It would have been obvious to ordinary skill in the art before the effective filing date of claimed invention to modify the circuit board to have conductor structure as taught by Chen and by doing so it will increase area of shielding to cover area long signal line with further improve shielding to have signal interiority or reliability and further reduces electromagnetic interference or noise as well as it will provide common shielding and grounding between conductors.
Referring to claim 42, (CN20 or Kobayashi) and (Wei or Jow), and further in view of Chen discloses the flexible printed circuit board of claim 1, wherein the first signal line is positioned between the two connector contacts such that the isolation loop forms an arc surrounding the contact of the first signal line to shield the first signal line from intra-contact crosstalk (see end loop structure of Wei, Jow, or Chen).
Response to Arguments
Applicant’s arguments with respect to the claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Pertinent Prior Arts
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Please see enclosed PTO-892 form for the citation of the pertinent art in the present case.
Response to Arguments
Applicant’s arguments with respect to claim(s) are not considered because applicants argument based on the non-elected subject matter which is withdrawn. Currently, no claim for prosecution based on by the original presentation as well as arguments.
Furthermore, in response to applicant argument about support to the subject matter of isolation loop and contacts in claim 1 and claim 29, see paragraphs and explanation mentioned above under objection of drawings and specification and see rejection under USC 112 above and they only discuss the isolation loop and contacts as a part of the cable 50, and no clear support for FPCB 40.
Therefore, applicant arguments are not persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for replying to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Communication
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PARESH PAGHADAL whose telephone number is (571)272-5251. The examiner can normally be reached on 7:00AM-4:00PM, Monday - Thursday.
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/PARESH PAGHADAL/Primary Examiner, Art Unit 2847
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