DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to the reply filed 24 November 2025.
Claims 1, 4-6, 9-11, 14-16 and 19-28 are pending and have been presented for examination.
Claims 2, 3, 7, 8, 12, 13, 17 and 18 have been cancelled.
Response to Arguments
Applicant's arguments filed 24 November 2025 have been fully considered but they are not persuasive.
Applicant argues (see page 6):
McGlaughlin discloses a system in which a write disturb refresh rate is based on a count incremented in proportion to various groups of write-to-write times. McGlaughlin fails to disclose or suggest incrementing the write counter by a second value much greater than the first value, where the write counter is used to control the write disturb refresh rate. Therefore, the cited reference fails to disclose the identical invention recited in Applicant's independent claims to the same level of detail of the claimed invention, as required to support a prima facie case of anticipation. The dependent claims necessarily include all features of the invention as recited in the independent claims. Therefore, claims are not rendered unpatentable by the cited references, and Applicant respectfully requests that the rejection be withdrawn.
The Examiner respectfully disagrees. MCGLAUGHLIN uses an exponential function to determine the amount to increment a write counter. The function is divided into bins corresponding to a write interval. The counter is incremented by an amount corresponding to the bin that covers the write interval (see [0042] and figure 5). The counter increment values are based on an exponential function, therefore the values in one bin can be considered much larger than values in another bin. Applicant has not provided any guidance or criteria that can be used to objectively quantify the term “much larger”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 4-6, 9-11, 14-16 and 19-28 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 4 and 5 recites the limitation "the logic" in lines 1 and 2, respectively. There is insufficient antecedent basis for this limitation in the claim. It appears that amended claim 1 is missing a few limitations that were present in the prior claim listing. These missing limitations are “one or more substrates” and “logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware”. The markup to the claims do not show these limitations being removed. If these limitations were present, that would resolve the antecedent basis issue.
The term “much greater than” in claims 1, 6, 11 and 16 is a relative term which renders the claim indefinite. The term “much greater than” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Since the term “much greater than” is not defined, it is not clear how much the second value would need to be incremented by.
Claims 4-5 and 21-22 are also rejected based on their dependency to claim 1.
Claims 9-10 and 23-24 are also rejected based on their dependency to claim 6.
Claims 14-15 and 25-26 are also rejected based on their dependency to claim 11.
Claims 19-20 and 27-28 are also rejected based on their dependency to claim 16.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4-6, 9-11, 14-16, 19, 20, 22, 26 and 28 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by MCGLAUGHLIN (U.S. Patent Application Publication #2020/0066341).
1. MCGLAUGHLIN discloses A memory controller (see [0022]: controller coupled to memory components) comprising: one or more substrates (see [0023]: one or more integrated circuits); and logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware (see [0023]: software/firmware; [0029]: ASIC), the logic to: determine a write-to-write delay with respect to a memory cell (see [0048]: time between writes to a memory cell is determined) that indicates a delay between subsequent writes to the memory cell is a relatively long delay or a relatively short delay (see [0041]-[0042], figure 5: different bins based on the time interval between writes), wherein one or more neighboring cells are adjacent to the memory cell (see [0045]-[0046]: adjacent neighboring memory cells); increment a write counter corresponding to the memory cell by a first value if the delay is the relatively long delay, or by a second value that is much greater than the first value if the delay is the relatively short delay (see figure 5: shorter time intervals increase the count by a greater amount than longer time intervals); and control a write disturb refresh rate of the one or more neighboring cells based on the write counter (see [0050]: disturb count is incremented based on the time between writes, when the counter reaches a threshold a refresh operation is performed).
4. The memory controller of claim 1, wherein the logic is further to reset the write counter in response to a refresh operation in the one or more neighboring cells (see [0055]: disturb count is reset in response to a refresh operation).
5. The memory controller of claim 1, wherein to determine the write-to-write delay, the logic is to determine a demarcation voltage associated with the memory cell (see [0049]: entry in drift table can be used to determine the interval since a last write; [0033]-[0034]: drift table tracks a voltage drift until a steady state is reached, this would be the demarcation voltage).
6. MCGLAUGHLIN discloses At least one computer readable storage medium comprising a set of instructions (see [0062]: computer program stored in a computer readable medium), which when executed by a memory controller (see [0022]: controller coupled to memory components), cause the memory controller to: determine a write-to-write delay with respect to a memory cell (see [0048]: time between writes to a memory cell is determined) that indicates a delay between subsequent writes to the memory cell is a relatively long delay or a relatively short delay (see [0041]-[0042], figure 5: different bins based on the time interval between writes), wherein one or more neighboring cells are adjacent to the memory cell (see [0045]-[0046]: adjacent neighboring memory cells); increment a write counter corresponding to the memory cell by a first value if the delay is the relatively long delay, or by a second value that is much greater than the first value if the delay is the relatively short delay (see figure 5: shorter time intervals increase the count by a greater amount than longer time intervals); and control a write disturb refresh rate of the one or more neighboring cells based on the write counter (see [0050]: disturb count is incremented based on the time between writes, when the counter reaches a threshold a refresh operation is performed).
9. The at least one computer readable storage medium of claim 6, wherein the instructions, when executed, further cause the memory controller to reset the write counter in response to a refresh operation in the one or more neighboring cells (see [0055]: disturb count is reset in response to a refresh operation).
10. The at least one computer readable storage medium of claim 6, wherein to determine the write-to-write delay, the instructions, when executed, further cause the memory controller to determine a demarcation voltage associated with the memory cell (see [0049]: entry in drift table can be used to determine the interval since a last write; [0033]-[0034]: drift table tracks a voltage drift until a steady state is reached, this would be the demarcation voltage).
11. MCGLAUGHLIN discloses A computing system comprising: a non-volatile memory including a memory cell (see [0020]: SSD, flash storage) and one or more neighboring cells adjacent to the memory cell (see [0045]-[0046]: neighbor cells that are adjacent); and a memory controller (see [0022]: controller coupled to memory components) including logic (see [0023]: software/firmware; [0029]: ASIC) coupled to one or more substrates (see [0023]: one or more integrated circuits), the logic to: determine a write-to-write delay with respect to a memory cell (see [0048]: time between writes to a memory cell is determined) that indicates a delay between subsequent writes to the memory cell is a relatively long delay or a relatively short delay (see [0041]-[0042], figure 5: different bins based on the time interval between writes), wherein one or more neighboring cells are adjacent to the memory cell (see [0045]-[0046]: adjacent neighboring memory cells); increment a write counter corresponding to the memory cell by a first value if the delay is the relatively long delay, or by a second value that is much greater than the first value if the delay is the relatively short delay (see figure 5: shorter time intervals increase the count by a greater amount than longer time intervals); and control a write disturb refresh rate of the one or more neighboring cells based on the write counter (see [0050]: disturb count is incremented based on the time between writes, when the counter reaches a threshold a refresh operation is performed).
14. The computing system of claim 11, wherein the logic is further to reset the write counter in response to a refresh operation in the one or more neighboring cells (see [0055]: disturb count is reset in response to a refresh operation).
15. The computing system of claim 11, wherein to determine the write-to- write delay, the logic is to determine a demarcation voltage associated with the memory cell (see [0049]: entry in drift table can be used to determine the interval since a last write; [0033]-[0034]: drift table tracks a voltage drift until a steady state is reached, this would be the demarcation voltage).
16. MCGLAUGHLIN discloses A method comprising: determining a write-to-write delay with respect to a memory cell (see [0048]: time between writes to a memory cell is determined) that indicates a delay between subsequent writes to the memory cell is a relatively long delay or a relatively short delay (see [0041]-[0042], figure 5: different bins based on the time interval between writes), wherein one or more neighboring cells are adjacent to the memory cell (see [0045]-[0046]: adjacent neighboring memory cells); incrementing a write counter corresponding to the memory cell by a first value if the delay is the relatively long delay, or by a second value that is much greater than the first value if the delay is the relatively short delay (see figure 5: shorter time intervals increase the count by a greater amount than longer time intervals); and controlling a write disturb refresh rate of the one or more neighboring cells based on the write counter (see [0050]: disturb count is incremented based on the time between writes, when the counter reaches a threshold a refresh operation is performed).
19. The method of claim 16, further including resetting the write counter in response to a refresh operation in the one or more neighboring cells (see [0055]: disturb count is reset in response to a refresh operation).
20. The method of claim 16, wherein determining the write-to-write delay includes determining a demarcation voltage associated with the memory cell (see [0049]: entry in drift table can be used to determine the interval since a last write; [0033]-[0034]: drift table tracks a voltage drift until a steady state is reached, this would be the demarcation voltage).
22. The memory controller of claim 1, wherein the logic is further to: set a write disturb threshold to a base rate multiplied by the second value (see [0050]: the refresh operation is performed when a count meets the threshold, if the base rate were one, then the value of the counter would be the threshold).
24. The at least one computer readable storage medium of claim 6, wherein the instructions, when executed, further cause the memory controller to: set a write disturb threshold to a base rate multiplied by the second value (see [0050]: the refresh operation is performed when a count meets the threshold, if the base rate were one, then the value of the counter would be the threshold).
26. The computing system of claim 11, wherein the logic is further to: set a write disturb threshold to a base rate multiplied by the second value (see [0050]: the refresh operation is performed when a count meets the threshold, if the base rate were one, then the value of the counter would be the threshold).
28. The method of claim 16, wherein the logic is further to: set a write disturb threshold to a base rate multiplied by the second value (see [0050]: the refresh operation is performed when a count meets the threshold, if the base rate were one, then the value of the counter would be the threshold).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 21, 23, 25 and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over MCGLAUGHLIN (U.S. Patent Application Publication #2020/0066341).
21. The memory controller of claim 1, wherein the first value is one and the second value is eight.
MCGLAUGHLIN fails to disclose explicit count values. Rather, the reference discloses a relationship between write frequency and count increments. The reference does not exclude any ranges, therefore, one and eight are numbers that would be possible inn the system disclosed by MCGLAUGHLIN. The relationship between the values is based on the properties of the particular memory cells (see [0040]). MCGLAUGHLIN discloses an exponential decay function to define the relationship. If a memory cell were to meet certain properties, a potential exponential decay function could include the values of one and eight for the count increment. One such function that would include one and eight as data points would be y = 12.1257*.6598^x. At time point 1, the count would increment by 8 and at time point 6, the count would increment by 1. “When there is a design need for market pressure to solve a problem and there are a finite number if identified, predictable solutions, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp." KSR, 82 USPQ2d at 1397.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify MCGLAUGHLIN to implement an exponential function with data points of one and eight, since those values would be covered by the graph of MCGLAUGHLIN. One of ordinary skill in the art would have been motivated to make such a modification as this would be obvious to try based on the properties of the memory cells.
23. The at least one computer readable storage medium of claim 6, wherein the first value is one and the second value is eight.
MCGLAUGHLIN fails to disclose explicit count values. Rather, the reference discloses a relationship between write frequency and count increments. The reference does not exclude any ranges, therefore, one and eight are numbers that would be possible inn the system disclosed by MCGLAUGHLIN. The relationship between the values is based on the properties of the particular memory cells (see [0040]). MCGLAUGHLIN discloses an exponential decay function to define the relationship. If a memory cell were to meet certain properties, a potential exponential decay function could include the values of one and eight for the count increment. One such function that would include one and eight as data points would be y = 12.1257*.6598^x. At time point 1, the count would increment by 8 and at time point 6, the count would increment by 1. “When there is a design need for market pressure to solve a problem and there are a finite number if identified, predictable solutions, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp." KSR, 82 USPQ2d at 1397.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify MCGLAUGHLIN to implement an exponential function with data points of one and eight, since those values would be covered by the graph of MCGLAUGHLIN. One of ordinary skill in the art would have been motivated to make such a modification as this would be obvious to try based on the properties of the memory cells.
25. The computing system of claim 11, wherein the first value is one and the second value is eight.
MCGLAUGHLIN fails to disclose explicit count values. Rather, the reference discloses a relationship between write frequency and count increments. The reference does not exclude any ranges, therefore, one and eight are numbers that would be possible inn the system disclosed by MCGLAUGHLIN. The relationship between the values is based on the properties of the particular memory cells (see [0040]). MCGLAUGHLIN discloses an exponential decay function to define the relationship. If a memory cell were to meet certain properties, a potential exponential decay function could include the values of one and eight for the count increment. One such function that would include one and eight as data points would be y = 12.1257*.6598^x. At time point 1, the count would increment by 8 and at time point 6, the count would increment by 1. “When there is a design need for market pressure to solve a problem and there are a finite number if identified, predictable solutions, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp." KSR, 82 USPQ2d at 1397.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify MCGLAUGHLIN to implement an exponential function with data points of one and eight, since those values would be covered by the graph of MCGLAUGHLIN. One of ordinary skill in the art would have been motivated to make such a modification as this would be obvious to try based on the properties of the memory cells.
27. The method of claim 16, wherein the first value is one and the second value is eight.
MCGLAUGHLIN fails to disclose explicit count values. Rather, the reference discloses a relationship between write frequency and count increments. The reference does not exclude any ranges, therefore, one and eight are numbers that would be possible inn the system disclosed by MCGLAUGHLIN. The relationship between the values is based on the properties of the particular memory cells (see [0040]). MCGLAUGHLIN discloses an exponential decay function to define the relationship. If a memory cell were to meet certain properties, a potential exponential decay function could include the values of one and eight for the count increment. One such function that would include one and eight as data points would be y = 12.1257*.6598^x. At time point 1, the count would increment by 8 and at time point 6, the count would increment by 1. “When there is a design need for market pressure to solve a problem and there are a finite number if identified, predictable solutions, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp." KSR, 82 USPQ2d at 1397.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify MCGLAUGHLIN to implement an exponential function with data points of one and eight, since those values would be covered by the graph of MCGLAUGHLIN. One of ordinary skill in the art would have been motivated to make such a modification as this would be obvious to try based on the properties of the memory cells.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD J DUDEK JR whose telephone number is (571)270-1030. The examiner can normally be reached Monday - Friday, 8:00A-4:00P.
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/EDWARD J DUDEK JR/Primary Examiner, Art Unit 2132