DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/11/2026 has been entered.
Response to Amendment
Examiner acknowledges the amendments made to claim 1. Claims 6-10 and 17 stand as withdrawn. Claims 11,12,13 and 18 stand as cancelled.
Response to Arguments
Applicant’s arguments with respect to claims 1-5,12,15-16 and 19-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The previous rejection of claims 1-5,12,15-16 and 19-20 under 35 U.S.C. § 112(a) have been withdrawn in light of the amendments made to claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3,15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Bae et al. (hereinafter Bae) (US 20110272730 A1) in view of Lim et al. (hereinafter Lim) (US 20110210345 A1) and Liang et al. (hereinafter Liang) (CN 104538530 A)
Examiner notes an attached machine translation will be used for the claim mapping of Liang for the remainder of the instant action. See PTO-892 form.
Regarding claim 1, Bae discloses in Figs. 3 and 4,
A light-emitting diode (LED), comprising:
a substrate [100 Fig. 3] (Para. [030]) which has a surface [top plane of substrate 100 Fig. 3] with an upper edge [right edge Fig. 4], a lower edge [left edge Fig. 4], and two opposing side edges [top and bottom edges Fig. 4] that extend between said upper and lower edges;
an epitaxial structure [142 Fig. 3] (Para. [0030]) which is disposed on said surface of said substrate [100 Fig. 3] (Para. [0030]) and which includes a first semiconductor layer [120 Fig. 3] (Para. [0030]), a second semiconductor layer [140 Fig. 3] (Para. [0030]) and an active layer [130 Fig. 3] (Para. [0030]) interposed between said first [120 Fig. 3] and second semiconductor layers [140 Fig. 3];
a first electrode [170 Fig. 4] (Para. [0036]) which is disposed on said first semiconductor layer [120 Fig. 3]; and
a second electrode [160,191,192,193 Fig. 4] (Para. [0036]) which is disposed on said second semiconductor layer [140 Fig. 3], and which includes a main portion [160,191 Fig. 4] and two extension portions [192,193 Fig. 4] (Para. [0039]) that extend away from said main portion [160,191 Fig. 4] (Para. [0036]), wherein a projection of said main portion [160,191 Fig. 4] on said surface is more proximal to said lower edge [left edge Fig. 4] than to said upper edge [right edge Fig. 4], and wherein a projection of each of said extension portions [192, 193 Fig. 4] on said surface extends in an extension direction away from said lower edge [left edge Fig. 4] toward a corresponding one of said side edges [top and bottom edges Fig. 4] (Para. [0036]) in such a manner that an included angle between a central axis (See Examiners markup) perpendicular to said bottom edge [left edge Fig. 4] and a tangent line of any point on said projection of each of said extension portions on said surface is not greater than 90˚ and increases along the extension direction (Para. [0036,0045]).
wherein each of said extension portions [192,193] independently extends from said main portion [160,191] (Para. [0045]).
and said extension portions [192,193] are spaced apart from each other (Para. [0039])
wherein said first electrode [170 Fig. 4] and said second electrode [160,191,192,193 Fig. 4] are spaced apart from each other by a distance H3 [distance between 192,193 and 170 Fig. 4] in a direction perpendicular to said lower edge [left edge Fig. 4],
and said upper edge [right edge Fig. 4] and a bottom end of said first electrode [left edge of 170 Fig. 4] that is away from said upper edge [right edge Fig. 4] are away from each other by a distance H2 in the direction perpendicular to said lower edge [distance between left and right edges of 170 Fig. 4],
Examiner notes the interpretation of “on” used in the instant application is understood to be “above” allowing layers to interpose between the element being described as “on” another element as shown in Fig. 2 of the claimed application with the second electrode [31] “on” the second semiconductor layer [22].
Bae fails to disclose,
an insulating layer which is disposed over said epitaxial structure, and which is formed with a first through hole partially exposing said first electrode and a second through hole partially exposing said second electrode;
a first pad electrode which is disposed on said insulating layer and which fills said first through hole to be electrically connected to said first electrode;
and a second pad electrode which is disposed on said insulating layer and which fills said second through hole to be electrically connected to said second electrode.
wherein said second pad electrode covers said main portion and a portion of each of said two extension portions, and exposed portions of said two extension portions that are exposed from said second pad electrode are spaced apart from each other.
Lim discloses,
an insulating layer [830 Fig. 27] which is disposed over a structure (Para. [0200]), and which is formed with a first through hole [B13 Fig. 27] (Para. [0200]) partially exposing a first electrode [820 Fig. 26] (Para. [0197]) and a second through hole [B11 Fig. 27] (Para. [0200]) partially exposing a second electrode [850 Fig. 26] (Para. [0198]);
a first pad electrode [821 Fig. 28] (Para. [0202]) which is disposed on said insulating layer [830 Fig. 28] (Para. [0202]) and which fills said first through hole [B13 Fig. 27] to be electrically connected to said first electrode [810 Fig. 26] (Para. [0202]);
and a second pad electrode [851 Fig. 28] (Para. [202]) which is disposed on said insulating layer [830 Fig. 28] and which fills said second through hole [B11 Fig. 27] to be electrically connected to said second electrode [850 Fig. 26] (Para. [0202]).
wherein said second pad electrode [851 Fig. 28] covers a main portion [850 Fig. 26] of a second electrode and extension portions [852,853 Fig. 26] that are exposed from the second pad electrode [851 Fig. 28] are spaced apart from each other (Paras. [0198,0199])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the insulating layer and electrode pad structure over the electrode structure of Bae in view of Jung for the purpose of preventing contact of the electrode form other semiconductor layers the device of Bae. (Lim Para. [0070])
Bae in view of Lim fails to disclose,
wherein said second pad electrode covers a portion of each of said two extension portions
Liang discloses in Fig. 4,
a pad electrode [40] (Paras. [35,49]) covering a main electrode [21] (Paras. [35,49]) and a portion of an extension portion [22] (Paras. [35,49])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the increased pad electrode size as shown in Liang in the modified device of Bae for the purpose of increasing the effective area of the pad and improved bonding. (Liang Paras. [35,49])
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Regarding claim 2, Bae in view of Lim and Liang as applied to claim 1 above further discloses in Fig. 4 of Bae,
wherein said projection of each of said extension portions [192,193] on said surface has two opposite sides, one of said sides [left side of extension portions] concavely facing said lower edge [left edge], and the other one of said sides [right side of extension portions] convexly facing said upper edge [right edge].
Regarding claim 3, Bae in view of Lim and Liang as applied to claim 1 above further discloses in Fig. 4 of Bae,
wherein each of said extension portions [192,193] is formed as an arc structure (Para. [0045]).
Regarding claim 15, Bae in view of Lim and Liang as applied to claim 1 above further discloses in Bae,
wherein the central axis passes through a centroid of said surface, and a projection of said main portion [160,191 Fig. 4] on said substrate [100 Fig. 3] lies on the central axis (See Examiners Markup).
Regarding claim 16, Bae in view of Lim and Liang as applied to claim 1 above further discloses in Bae,
wherein the central axis passes through a centroid of said surface, and a projection of said first electrode [170 Fig. 4] on said substrate [100 Fig. 3] lies on the central axis (See Examiners Markup).
Claims 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Bae in view of Lim and Liang as applied to claim 1 above, and further in view of Weng et al (hereinafter Weng) (US 20120098023 A1)
Regarding claim 12, Bae in view of Lim and Liang discloses the device outlined in the rejection of claim 1 above but fails to disclose,
wherein a cross section of each of said extension portions perpendicular to the extension direction has a bottom width proximal to said epitaxial structure which ranges from 2 µm to 10 µm.
Weng discloses in Fig. 1,
extension portions [3,4] (Para. [0053]) with a width value between the range of 2 µm to 10 µm (Para. [0053])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the width value of the extension portions of Weng into the extension portions of the modified device of Bae for the purpose of controlling the light absorption due to the electrodes. (Weng Para. [0053])
Regarding claim 19, Bae in view of Lim and Liang discloses the device outlined in the rejection of claim 1 above but fails to disclose,
wherein a length of each of the side edges may be not greater than twice of a length of each of the upper and lower edges
Weng discloses
a length [X] of each of the side edges [top and bottom edges Fig. 1] that is not greater than twice of a length [Y] of each of the upper and lower edges [left and right edges Fig. 1] (Para. [0055])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the length values of the upper, lower and side edges of Weng into the upper, lower and side edges of the modified device of Bae for the purpose of obtaining a rectangle shape for the semiconductor device. (Para. [0055])
Claims 4 and 5 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Bae in view of Lim and Liang as applied to claims 1 and 2 above in view of Chou et al. (hereinafter Chou) (US 20170179343 A1)
Regarding claim 4, Bae in view of Lim and Liang discloses the device outlined in the rejections of claims 1 and 2 above but fails to disclose,
wherein each of said extension portions has a radius of curvature that is not greater than 100 µm.
Chou discloses in Fig. 4,
an extension portion [1621] with a radius of curvature that is not greater than 100 µm. (Para. [0053])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the radius of curvature of Chou into the extension portions of the modified device of Bae for the purpose of controllably selecting a curvature to connect the endpoints of the extension portions to the main body.
Regarding claim 5, Bae in view of Lim and Liang as applied to claim 4 above further discloses,
wherein each of said extension portions [Bae 192,193 Fig. 4] has a radius of curvature that is constant along the extension direction.
Examiner notes that when the radius of curvature of Chou is applied to the entire extension portion of Bae, the radius of curvature throughout the extension portion must be constant as the whole extension portion shares the same radius of curvature value.
Regarding claim 20, Bae in view of Lim and Liang discloses the device outlined in the rejection of claim 1 above but fails to disclose,
A light-emitting device, comprising at least one LED of claim 1.
Choue discloses in Fig. 6,
A light emitting device [600], comprising at least one LED [608] (Para. [0058])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the LED of the modified device of Bae into the light emitting device of Chou for the purpose of obtaining a device to further emit the light produced by the LED of the modified device of Bae.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Examiner notes (US 20200006612 A1) which discloses a second pad covering a main portion and a portion of two extending regions of an electrode. See PTO-892 form.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNTER J NELSON whose telephone number is (571)270-5318. The examiner can normally be reached Mon-Fri. 8:30am-5:00 ET.
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/H.J.N./Examiner, Art Unit 2828 /TOD T VAN ROY/Primary Examiner, Art Unit 2828
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