Prosecution Insights
Last updated: April 19, 2026
Application No. 17/819,117

ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF

Non-Final OA §102§103
Filed
Aug 11, 2022
Examiner
HELBERG, DAVID MICHAEL
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Innolux Corporation
OA Round
3 (Non-Final)
50%
Grant Probability
Moderate
3-4
OA Rounds
3y 5m
To Grant
99%
With Interview

Examiner Intelligence

Grants 50% of resolved cases
50%
Career Allow Rate
4 granted / 8 resolved
-18.0% vs TC avg
Strong +67% interview lift
Without
With
+66.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
59 currently pending
Career history
67
Total Applications
across all art units

Statute-Specific Performance

§103
65.6%
+25.6% vs TC avg
§102
27.8%
-12.2% vs TC avg
§112
6.6%
-33.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 8 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. CN 2022106677091, filed on June 14, 2022. Specification The disclosure is objected to because of the following informalities: Numerical designation “108p” appears in Fig. 10, but is not talked on further in the Specification. The assumption will be made that 108p correlates to an opening of 108. Paragraph [0030] of the specification cites “the openings 106p” and “the openings 106”. The assumption will be made that “106p” is the correct numerical designation for the openings in 106. Appropriate correction is required. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 2, 4, 10-11, and 18-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lin et al. (US 9607958 B2). Regarding claim 1, Lin et al. teaches: An electronic device [50, Col. 6, Lines 13-15, Fig. 1], comprising: an electronic unit [124, Col. 8, Line 15, Fig. 3b] comprising: a chip unit [122 “base substrate”, Col. 8, Lines 12-15, Fig. 3b]; a first insulating layer [134, Col. 8, Lines 48-49, Fig. 3b] disposed on the chip unit [122, Fig. 3b]; and a second insulating layer [180, Col. 11, Lines 18-20, Fig. 7a] disposed on the first insulating layer [134], wherein the second insulating layer [180] has a first side that overlaps the chip unit [122] along a normal direction of the electronic unit [124] [See Fig. 7a below]; a protective layer [148, Col. 9, Lines 14-23, Fig. 4c] surrounding the electronic unit [124]; and a circuit layer [See Fig. 7j below] electrically connected to the electronic unit [124]. PNG media_image1.png 308 474 media_image1.png Greyscale PNG media_image2.png 238 725 media_image2.png Greyscale PNG media_image3.png 274 820 media_image3.png Greyscale Drawings and pictures can anticipate claims if they clearly show the structure which is claimed. In re Mraz, 455 F.2d 1069, 173 USPQ 25 (CCPA 1972). However, the picture must show all the claimed structural features and how they are put together. Jockmus v. Leviton, 28F.2d 812 (2d Cir. 1928). The origin of the drawing is immaterial. For instance, drawings in a design patent can anticipate or make obvious the claimed invention as can drawings in utility patents. When the reference is a utility patent, it does not matter that the feature shown is unintended or unexplained in the specification. The drawings must be evaluated for what they reasonably disclose and suggest to one of ordinary skill in the art. In re Aslanian, 590 F.2d 911, 200 USPQ 500 (CCPA 1979). (MPEP 2125) Regarding claim 2, Lin et al. teaches: The electronic device [50] of claim 1, wherein the first insulating layer [134] has a second side, and the chip unit [122] has a third side aligned with the second side. PNG media_image4.png 230 729 media_image4.png Greyscale Regarding claim 4, Lin et al. teaches: The electronic device [50] of claim 1, wherein the second insulating layer [152] exposes a portion of an upper surface of the first insulating layer [134]. PNG media_image5.png 256 706 media_image5.png Greyscale Regarding claim 10, Lin et al. teaches: A method for manufacturing an electronic device [50], comprising: providing a chip unit [122]; forming a first insulating layer [134, Fig. 3b] on the chip unit [122]; forming a second insulating layer [180, Fig. 7a] on the first insulating layer [134]; and performing a dicing process [136 “saw blade or laser cutting tool”, Col. 8, Lines 62-65, Fig. 3c] to form an electronic unit [124], wherein the second insulating layer [180, Fig. 7a] has a first side that overlaps the electronic unit [124] along a normal direction of the electronic unit [124] after the dicing process [136, Fig. 3c]. Regarding claim 11, Lin et al. teaches: PNG media_image4.png 230 729 media_image4.png Greyscale The method of claim 10, wherein the first insulating layer [134] has a second side, and the chip unit [122] has a third side aligned with the second side after the dicing process. Regarding claim 18, Lin et al. teaches: The method of claim 10, further comprising transferring the electronic unit [124] to a carrier substrate [52, Col. 6, Lines 13-15, Fig. 1] and forming a protective layer [148] surrounding the electronic unit [124]. Regarding claim 19, Lin et al. teaches: The method of claim 18, further comprising forming a circuit layer on the electronic unit [124], wherein the circuit layer is electrically connected to the electronic unit [124]. PNG media_image6.png 274 820 media_image6.png Greyscale Regarding claim 20, Lin et al. teaches: The method of claim 19, wherein the circuit layer extends horizontally from an upper surface of the electronic unit [124] to an upper surface of the protective layer [148]. PNG media_image6.png 274 820 media_image6.png Greyscale Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 3, 7-9, 12, 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 9607958 B2), in view of Yueh et al. (US 10692799 B2). Regarding claim 3, Lin et al. teaches: The electronic device [50] of claim 2, wherein the second side of the first insulating layer [134] has a first roughness, and the third side of the chip unit [122] has a second roughness, Lin et al. does not teach: wherein the first roughness is greater than the second roughness. Yueh et al. teaches: wherein the first roughness is greater than the second roughness [Col. 4, Lines 50-60]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Yueh et al. into the teachings of Lim et al. to include wherein the first roughness is greater than the second roughness. The ordinary artisan would have been motivated to modify Lim et al. in the above manner for the purpose of enhancing adhesion between features. Given the finite number of roughness possibilities; and the predictable result that increasing roughness increases adhesion; it would have been obvious to one skilled in the art to try a first roughness for the second side of the first insulating layer [134] that is greater than the second roughness of the third side of the chip unit [122], for the purpose of increasing adhesion. [MPEP 2143(I)(E) “Obvious to try”]. Regarding claim 7, Lin et al. teaches: The electronic device [50] of claim 1, wherein: the first insulating layer [134] has first openings [See Fig. 4d below] and the second insulating layer [180] has second openings [See Fig. 7a below]; one of the first openings has a first sidewall with a third roughness; and one of the second openings has a second sidewall with a fourth roughness. PNG media_image7.png 278 662 media_image7.png Greyscale PNG media_image8.png 332 731 media_image8.png Greyscale Lin et al. does not teach: A fourth roughness that is less than the third roughness. Yueh et al. teaches: A fourth roughness that is less than the third roughness [Col. 4, Lines 50-60]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Yueh et al. into the teachings of Lim et al. to include a fourth roughness that is less than the third roughness. The ordinary artisan would have been motivated to modify Lim et al. in the above manner for the purpose of enhancing adhesion between features. Given the finite number of roughness possibilities; and the predictable result that increasing roughness increases adhesion; it would have been obvious to one skilled in the art to try a fourth roughness that is less than the third roughness, for the purpose of increasing adhesion. [MPEP 2143(I)(E) “Obvious to try”]. Regarding claim 8, Lin et al. and Yueh et al. teach the electronic device [50] of claim 7. Lin et al. further teaches: Wherein the first sidewall has a concave shape. PNG media_image9.png 278 662 media_image9.png Greyscale Regarding claim 9, Lin et al. and Yueh et al. teach the electronic device [50] of claim 7. Lin et al. further teaches: wherein the electronic unit [124] further comprises conductive pads [132], and wherein the circuit layer is electrically connected to the conductive pads [132] of the electronic unit [124] through the first openings and the second openings. PNG media_image3.png 274 820 media_image3.png Greyscale Regarding claim 12, Lin et al. teaches: The method of claim 11, wherein the second side of the first insulating layer [134] has a first roughness, and the third side of the chip unit [122] has a second roughness. Lin et al. does not teach: wherein the first roughness is greater than the second roughness. Yueh et al. teaches: wherein the first roughness is greater than the second roughness [Col. 4, Lines 50-60]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Yueh et al. into the teachings of Lim et al. to include wherein the first roughness is greater than the second roughness. The ordinary artisan would have been motivated to modify Lim et al. in the above manner for the purpose of enhancing adhesion between features. Given the finite number of roughness possibilities; and the predictable result that increasing roughness increases adhesion; it would have been obvious to one skilled in the art to try a first roughness for the second side of the first insulating layer [134] that is greater than the second roughness of the third side of the chip unit [122], for the purpose of increasing adhesion. [MPEP 2143(I)(E) “Obvious to try”]. Regarding claim 14, Lin et al. teaches: The method of claim 10, further comprising forming first openings in the first insulating layer [134] and forming second openings in the second insulating layer [180], wherein one of the first openings has a first sidewall with a third roughness, and one of the second openings has a second sidewall with a fourth roughness. Lin et al. does not teach: A fourth roughness that is less than the third roughness. Yueh et al. teaches: A fourth roughness that is less than the third roughness [Col. 4, Lines 50-60]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Yueh et al. into the teachings of Lim et al. to include a fourth roughness that is less than the third roughness. The ordinary artisan would have been motivated to modify Lim et al. in the above manner for the purpose of enhancing adhesion between features. Given the finite number of roughness possibilities; and the predictable result that increasing roughness increases adhesion; it would have been obvious to one skilled in the art to try a fourth roughness that is less than the third roughness, for the purpose of increasing adhesion. [MPEP 2143(I)(E) “Obvious to try”]. Regarding claim 15, Lin et al. and Yueh et al. teach the method of claim 14. Lin et al. further teaches: wherein the step of forming the first opening comprises using a laser drilling process [135, Col. 8, Lines 59-61, Fig. 3b] to form the first openings, and wherein the step of forming the second openings comprises using a photolithography process [182, Col. 2, Lines 38-40, Fig. 7a] to form the second openings. Regarding claim 16, Lin et al. and Yueh et al. teach the method of claim 15. Lin et al. further teaches: wherein the second insulating layer [180] exposes a portion of an upper surface of the first insulating layer [134] after the photolithography process. PNG media_image5.png 256 706 media_image5.png Greyscale Regarding claim 17, Lin et al. and Yueh et al. teach the method of claim 14. Lin et al. further teaches: wherein the first sidewall has a concave shape. PNG media_image9.png 278 662 media_image9.png Greyscale Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 9607958 B2), in view of Kwon et al. (US 9496488 B2). Regarding claim 5, Lin et al. teaches: PNG media_image10.png 256 705 media_image10.png Greyscale The electronic device [50] of claim 1, wherein an angle between the first side and a lower surface of the second insulating layer [180] Lim et al. does not teach: The angle greater than or equal to 45° and less than 90°. Kwon et al. teaches: The angle greater than or equal to 45° and less than 90°. [Col. 6, Lines 65-67 to Col. 7, Lines 1-7]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Kwon et al. into the teachings of Lim et al. to include the angle greater than or equal to 45° and less than 90°. The ordinary artisan would have been motivated to modify Lim et al. in the above manner for the purpose of enhancing adhesion between the two features. Claim 6 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 9607958 B2), in view of Tong et al. (US 12198633 B2). Regarding claim 6, Lin et al. teaches: The electronic device [50] of claim 1, wherein the first insulating layer [134] has a first thickness, and the second insulating layer [180] has a second thickness. Lin et al. does not teach: Wherein the first thickness is greater than the second thickness. Tong et al. teaches: Wherein the first thickness is greater than the second thickness [Col. 2, Lines 61-63]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Tong et al. into the teachings of Lin et al. to include wherein the first thickness is greater than the second thickness. The ordinary artisan would have been motivated to modify Lim et al. in the above manner for the purpose of protecting the chip unit, thereby avoiding impaired performance of the chip unit and increasing reliability of the electronic device. Also, a lesser thickness for the second thickness may increase layout area of the circuit, thereby enhancing overall electrical properties of the electronic device. In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.). In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. [MPEP 2144.04(IV)(A) Changes in Size/Proportion] Regarding claim 13, Lin et al. teaches: The method of claim 10, wherein the first insulating layer [134] has a first thickness, and the second insulating layer [180] has a second thickness. Lin et al. does not teach: Wherein the first thickness is greater than the second thickness. Tong et al. teaches: Wherein the first thickness is greater than the second thickness [Col. 2, Lines 61-63]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Tong et al. into the teachings of Lin et al. to include wherein the first thickness is greater than the second thickness. The ordinary artisan would have been motivated to modify Lim et al. in the above manner for the purpose of protecting the chip unit, thereby avoiding impaired performance of the chip unit and increasing reliability of the electronic device. Also, a lesser thickness for the second thickness may increase layout area of the circuit, thereby enhancing overall electrical properties of the electronic device. In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.). In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. [MPEP 2144.04(IV)(A) Changes in Size/Proportion] Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID MICHAEL HELBERG whose telephone number is (571)270-1422. The examiner can normally be reached Mon.-Fri. 8am-5pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached on (571)270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /D.M.H./Examiner, Art Unit 2815 /MONICA D HARRISON/Primary Examiner, Art Unit 2815
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Prosecution Timeline

Aug 11, 2022
Application Filed
Mar 07, 2025
Non-Final Rejection — §102, §103
Jun 01, 2025
Response Filed
Aug 26, 2025
Final Rejection — §102, §103
Nov 10, 2025
Interview Requested
Nov 20, 2025
Examiner Interview Summary
Nov 20, 2025
Applicant Interview (Telephonic)
Dec 04, 2025
Request for Continued Examination
Dec 16, 2025
Response after Non-Final Action
Dec 17, 2025
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
50%
Grant Probability
99%
With Interview (+66.7%)
3y 5m
Median Time to Grant
High
PTA Risk
Based on 8 resolved cases by this examiner. Grant probability derived from career allow rate.

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