DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s arguments and amendments filed December 4, 2025 have been entered and considered.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 4, 2025 has been entered.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 10-11, and 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 9607958 B2), in view of Lin et al. (US 9847324 B2), hereby referred to as Lin ‘324.
Regarding claim 1, Lin et al. teaches:
An electronic device [50, Col. 6, Lines 13-15, Fig. 1], comprising:
an electronic unit [124, Col. 8, Line 15, Fig. 3b] comprising:
a chip unit [122 "base substrate", Col. 8, Lines 12-15, Fig. 3b];
a first insulating layer [134, Col. 8, Lines 48-49, Fig. 3b] disposed on the chip unit [122, Fig. 3b]; and
a second insulating layer [180, Col. 11, Lines 18-20, Fig. 7a] disposed on the first insulating layer [134, Fig. 3b], wherein the second insulating layer [180, Fig. 7a] has a first side that overlaps the chip unit [122, Fig. 7a] along a normal direction of the electronic unit [124, Fig. 7a]; [See Fig. 7a below]
a protective layer [148, Col. 9, Lines 14-23, Fig. 4c] surrounding the electronic unit [124, Fig. 4c],
a circuit layer [See Fig. 7j below] electrically connected to the electronic unit [124, Fig. 7j].
a width of the second insulating layer [180, Col. 11, Lines 15-31, Fig. 7a] is less than a width of the chip unit [124, Col. 8, Lines 12-19, Fig. 7a].
Although not specifically mentioned, it can be seen in Fig. 7a that the width of insulating layer [180] in the horizontal or vertical direction is less than the width of the chip unit [124] in the horizontal or vertical direction. See also, MPEP 2144.04(IV)(A) Changes in Size/Proportion.
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Drawings and pictures can anticipate claims if they clearly show the structure which is claimed. In re Mraz, 455 F.2d 1069, 173 USPQ 25 (CCРА 1972). However, the picture must show all the claimed structural features and how they are put together. Jockmus v. Leviton, 28F.2d 812 (2d Cir. 1928). The origin of the drawing is immaterial. For instance, drawings in a design patent can anticipate or make obvious the claimed invention as can drawings in utility patents. When the reference is a utility patent, it does not matter that the feature shown is unintended or unexplained in the specification. The drawings must be evaluated for what they reasonably disclose and suggest to one of ordinary skill in the art. In re Aslanian, 590 F.2d 911, 200 USPQ 500 (CCPA 1979). (MPEP 2125)
Lin et al. does not teach:
wherein the protective layer contacts a side wall of the chip unit, a side wall of the first insulating layer and a side wall of the second insulating layer;
wherein a first thickness of the first insulating layer is greater than a second thickness of the second insulating layer.
Lin ‘324 teaches:
wherein the protective layer [286, Col. 25, Lines 51-56, Fig. 13g-13w] contacts a side wall of the chip unit [276, Col. 25, Lines 46-51, Fig. 13g-13w], a side wall of the first insulating layer [298, Col. 27, Lines 27-30, Fig. 13w] and a side wall of the second insulating layer [278, Col. 24, Lines 13-20, Fig. 13w];
wherein a first thickness of the first insulating layer [298, Fig. 13w] is greater than a second thickness of the second insulating layer [278, Fig. 13w].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Lin ‘324 into the teachings of Lin et al. to include the wherein the protective layer contacts a side wall of the chip unit, a side wall of the first insulating layer and a side wall of the second insulating layer; wherein a first thickness of the first insulating layer is greater than a second thickness of the second insulating layer. The ordinary artisan would have been motivated to modify Lin et al. in the above manner for the purpose of protecting features within the device, and insulating features within the device to prevent short circuits. See also, MPEP 2144.04(VI)(C) Rearrangement of Parts, and MPEP 2144.04(IV)(A) Changes in Size/Proportion.
Regarding claim 2, Lin et al. and Lin ‘324 teach the electronic device of claim 1.
Lin et al. further teaches:
wherein the first insulating layer [134, Fig. 7a] has a second side, and the chip unit [122, Fig. 7a] has a third side aligned with the second side.
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Regarding claim 4, Lin et al. and Lin ‘324 teach the electronic device of claim 1.
Lin et al. further teaches:
wherein the second insulating layer [152, Fig. 7a] exposes a portion of an upper surface of the first insulating layer [134, Fig. 7a].
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Regarding claim 10, Lin et al. teaches:
A method for manufacturing an electronic device, comprising:
providing a chip unit [122, Col. 8, Lines 12-15, Fig. 3b];
forming a first insulating layer [134, Col. 8, Lines 48-49, Fig. 3b] on the chip unit [122, Fig. 3b];
forming a second insulating layer [180, Col. 11, Lines 18-20, Fig. 7a] on the first insulating layer [134];
performing a dicing process [136 "saw blade or laser cutting tool", Col. 8, Lines 62-65, Fig. 3c] to form an electronic unit [124], wherein the second insulating layer [180, Fig. 7a] has a first side that overlaps the electronic unit [124] along a normal direction of the electronic unit [124] after the dicing process [136, Fig. 3c].
transferring the electronic unit [124] to a carrier substrate [52, Col. 6, Lines 13-37, Fig. 1] and forming a protective layer [148, Fig. 4c] surrounding the electronic unit [124, Fig. 4c].
a width of the second insulating layer [180, Col. 11, Lines 15-31, Fig. 7a] is less than a width of the chip unit [124, Col. 8, Lines 12-19, Fig. 7a].
Although not specifically mentioned, it can be seen in Fig. 7a that the width of insulating layer [180] in the horizontal or vertical direction is less than the width of the chip unit [124] in the horizontal or vertical direction. See also, MPEP 2144.04(IV)(A) Changes in Size/Proportion.
Lin et al. does not teach:
wherein the protective layer contacts a side wall of the chip unit, a side wall of the first insulating layer and a side wall of the second insulating layer;
wherein a first thickness of the first insulating layer is greater than a second thickness of the second insulating layer.
Lin ‘324 teaches:
wherein the protective layer [286, Col. 25, Lines 51-56, Fig. 13g-13w] contacts a side wall of the chip unit [276, Col. 25, Lines 46-51, Fig. 13g-13w], a side wall of the first insulating layer [298, Col. 27, Lines 27-30, Fig. 13w] and a side wall of the second insulating layer [278, Col. 24, Lines 13-20, Fig. 13w];
wherein a first thickness of the first insulating layer [298, Fig. 13w] is greater than a second thickness of the second insulating layer [278, Fig. 13w].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Lin ‘324 into the teachings of Lin et al. to include the wherein the protective layer contacts a side wall of the chip unit, a side wall of the first insulating layer and a side wall of the second insulating layer; wherein a first thickness of the first insulating layer is greater than a second thickness of the second insulating layer. The ordinary artisan would have been motivated to modify Lin et al. in the above manner for the purpose of protecting features within the device, and insulating features within the device to prevent short circuits. See also, MPEP 2144.04(VI)(C) Rearrangement of Parts, and MPEP 2144.04(IV)(A) Changes in Size/Proportion.
Regarding claim 11, Lin et al. and Lin ‘324 teach the method of claim 10.
Lin et al. further teaches:
wherein the first insulating layer [134, Fig. 7a] has a second side, and the chip unit [122, Fig. 7a] has a third side aligned with the second side after the dicing process.
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Regarding claim 19, Lin et al. and Lin ‘324 teach the method of claim 10.
Lin et al. further teaches:
further comprising forming a circuit layer on the electronic unit [124, Fig. 7j], wherein the circuit layer is electrically connected to the electronic unit [124, Fig. 7j].
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Regarding claim 20, Lin et al. and Lin ‘324 teach the method of claim 19.
Lin et al. further teaches:
wherein the circuit layer extends horizontally from an upper surface of the electronic unit [124, Fig. 7j] to an upper surface of the protective layer [148, Fig. 7j].
Regarding claim 21, Lin et al. and Lin ‘324 teach the electronic device of claim 1.
Lin et al. does not teach:
wherein the protective layer is in contact with the side wall of the first side of the second insulation layer.
Lin ‘324 teaches:
wherein the protective layer [286, Col. 25, Lines 46-65, Fig. 13w] is in contact with the side wall of the first side of the second insulation layer [278, Col. 24, Lines 13-28, Fig. 13w].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Lin ‘324 into the teachings of Lin et al. and Lin ‘324 to include wherein the protective layer is in contact with the side wall of the first side of the second insulation layer. The ordinary artisan would have been motivated to modify Lin et al. and Lin ‘324 in the above manner for the purpose of protecting features within the device, and insulating features within the device to prevent shot circuits. See also, MPEP 2144.04(VI)(C) Rearrangement of Parts.
Claims 3, 7-9, 12, and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 9607958 B2), in view of Lin ‘324 (US 9847324 B2), and Yueh et al. (US 10692799 B2).
Regarding claim 3, Lin et al. and Lin ‘324 teach the electronic device of claim 2.
Lin et al. further teaches:
wherein the second side of the first insulating layer [134] has a first roughness, and the third side of the chip unit [122] has a second roughness.
Lin et al. and Lin ‘324 do not teach:
wherein the first roughness is greater than the second roughness.
Yueh et al. teaches:
wherein the first roughness is greater than the second roughness [Col. 4, Lines 50-60]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Yueh et al. into the teachings of Lin et al. and Lin ‘324 to include wherein the first roughness is greater than the second roughness. The ordinary artisan would have been motivated to modify Lin et al. and Lin ‘324 in the above manner for the purpose of enhancing adhesion between features.
Given the finite number of roughness possibilities; and the predictable result that increasing roughness increases adhesion; it would have been obvious to one skilled in the art to try a first roughness for the second side of the first insulating layer [134] that is greater than the second roughness of the third side of the chip unit [122], for the purpose of increasing adhesion. [MPEP 2143(I)(Е) “Obvious to try"].
Regarding claim 7, Lin et al. and Lin ‘324 teach the electronic device of claim 1.
Lin et al. further teaches:
the first insulating layer [134] has first openings [See Fig. 4d below] and the second insulating layer [180] has second openings [See Fig. 7a below]; one of the first openings has a first sidewall with a third roughness; and one of the second openings has a second sidewall with a fourth roughness.
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Lin et al. and Lin ‘324 do not teach:
A fourth roughness that is less than the third roughness.
Yueh et al. teaches:
A fourth roughness that is less than the third roughness [Col. 4, Lines 50-60].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Yueh et al. into the teachings of Lin et al. and Lin ‘324 to include a fourth roughness that is less than the third roughness. The ordinary artisan would have been motivated to modify Lin et al. and Lin ’324 in the above manner for the purpose of enhancing adhesion between features.
Given the finite number of roughness possibilities; and the predictable result that increasing roughness increases adhesion; it would have been obvious to one skilled in the art to try a fourth roughness that is less than the third roughness, for the purpose of increasing adhesion. [MPEP 2143(1) (E) "Obvious to try"].
Regarding claim 8, Lin et al., Lin ‘324, and Yueh et al. teach the electronic device of claim 7.
Lin et al. further teaches:
Wherein the first sidewall has a concave shape.
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Regarding claim 9, Lin et al., Lin ‘324, and Yueh et al. teach the electronic device of claim 7.
Lin et al. further teaches:
wherein the electronic unit [124] further comprises conductive pads [132], and wherein the circuit layer is electrically connected to the conductive pads [132] of the electronic unit [124] through the first openings and the second openings.
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Regarding claim 12, Lin et al. and Lin ‘324 teach the method of claim 11.
Lin et al. further teaches:
wherein the second side of the first insulating layer [134] has a first roughness, and the third side of the chip unit [122] has a second roughness.
Lin et al. and Lin ’324 do not teach:
wherein the first roughness is greater than the second roughness.
Yueh et al. teaches:
wherein the first roughness is greater than the second roughness [Col. 4, Lines 50-60]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Yueh et al. into the teachings of Lin et al. and Lin ‘324 to include wherein the first roughness is greater than the second roughness. The ordinary artisan would have been motivated to modify Lin et al. and Lin ‘324 in the above manner for the purpose of enhancing adhesion between features.
Given the finite number of roughness possibilities; and the predictable result that increasing roughness increases adhesion; it would have been obvious to one skilled in the art to try a first roughness for the second side of the first insulating layer [134] that is greater than the second roughness of the third side of the chip unit [122], for the purpose of increasing adhesion. [MPEP 2143(I)(E) "Obvious to try"].
Regarding claim 14, , Lin et al. and Lin ‘324 teach the method of claim 10.
Lin et al. further teaches:
further comprising forming first openings in the first insulating layer [134] and forming second openings in the second insulating layer [180], wherein one of the first openings has a first sidewall with a third roughness, and one of the second openings has a second sidewall with a fourth roughness.
Lin et al. and Lin ’324 do not teach:
A fourth roughness that is less than the third roughness.
Yueh et al. teaches:
A fourth roughness that is less than the third roughness [Col. 4, Lines 50-60]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Yueh et al. into the teachings of Lin et al. and Lin ‘324 to include a fourth roughness that is less than the third roughness. The ordinary artisan would have been motivated to modify Lin et al. and Lin ‘324 in the above manner for the purpose of enhancing adhesion between features.
Given the finite number of roughness possibilities; and the predictable result that increasing roughness increases adhesion; it would have been obvious to one skilled in the art to try a fourth roughness that is less than the third roughness, for the purpose of increasing adhesion. [MPEP 2143(I) (E) "Obvious to try"].
Regarding claim 15, Lin et al., Lin ‘324 and Yueh et al. teach the method of claim 14.
Lin et al. further teaches:
wherein the step of forming the first opening comprises using a laser drilling process [135, Col. 8, Lines 59-61, Fig. 3b] to form the first openings, and wherein the step of forming the second openings comprises using a photolithography process [182, Col. 2, Lines 38-40, Fig. 7a] to form the second openings.
Regarding claim 16, Lin et al., Lin ‘324 and Yueh et al. teach the method of claim 15.
Lin et al. further teaches:
wherein the second insulating layer [180, Fig. 7a] exposes a portion of an upper surface of the first insulating layer [134, Fig. 7a] after the photolithography process.
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Regarding claim 17, Lin et al., Lin ‘324 and Yueh et al. teach the method of claim 14.
Lin et al. further teaches:
wherein the first sidewall has a concave shape.
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Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 9607958 B2), in view of Lin ‘324 (US 9847324 B2) as applied to claim 1 above, and further in view of Kwon et al. (US 9496488 B2).
Regarding claim 5, Lin et al. and Lin ‘324 teach the electronic device of claim 1.
Lin et al. further teaches:
an angle between the first side and a lower surface of the second insulating layer [180, Fig. 7a]
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Lin et al. does not teach:
The angle greater than or equal to 45° and less than 90°.
Kwon et al. teaches:
The angle greater than or equal to 45° and less than 90°. [Col. 6, Lines 65-67 to Col. 7, Lines 1-7].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Kwon et al. into the teachings of Lin et al. and Lin ‘324 to include the angle greater than or equal to 45° and less than 90°. The ordinary artisan would have been motivated to modify Lin et al. and Lin ’324 in the above manner for the purpose of enhancing adhesion between the two features.
Response to Arguments
Applicant's arguments filed December 4, 2025 have been fully considered but they are not persuasive. Applicant argues on page 8, Section: III. Claim Rejections – 35 U.S.C. § 103, in remarks filed December 4, 2025 that the current prior art of record does not teach the amendments to independent claims 1 and 10. This argument is not persuasive because the amendments to independent claims 1 and 10 can be overcome by primary reference Lin et al. (US 9607958 B2).
Applicant argues on page 10, Section: IV. New Claim 21, in remarks filed December 4, 2025 that new claim 21 is dependent on independent claim 1 and should now be allowable. Examiner disagrees with Applicant because the limitations of claim 21 can be overcome by secondary reference Lin ‘324 (US 9847324 B2), and the limitations of independent claim 1 can be overcome by Lin et al. (US 9607958 B2), in view of Lin ‘324 (US 9847324 B2).
In summary, the amendments to independent claims 1 and 10 can be overcome by primary reference Lin et al. (US 9607958 B2), and the limitations of new claim 21 can be overcome by secondary reference Lin ‘324 (US 9847324 B2). All claims directly or indirectly dependent on independent claims 1 and 10 are also rejected for at least the reasons mentioned above.
Conclusion
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/D.M.H./Examiner, Art Unit 2815 12/17/2025
/MONICA D HARRISON/Primary Examiner, Art Unit 2815
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