DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, filed 1/12/2026, with respect to the rejections of claims 1-20 under 35 USC § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejection is made in view of 35 USC § 103.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Crabtree et al. (US 20260046317 A1) in view of Ibanez et al. (US 20230127722 A1).
Regarding claim 1, Crabtree et al. teaches a network device comprising: a high-speed memory; and a logic circuitry operatively coupled to the high-speed memory, the logic circuitry being configured, via a pipeline operation comprising an arithmetic or bitwise operator, to route bi-directional traffic symmetrically through inserted services among two or more network sites or infrastructure, including a first network site or infrastructure and a second network site or infrastructure (Paragraph 308, 307, These passages teach logic circuitry implemented as a pipelined micro-op processing engine including arithmetic/bitwise operators (ADD, MIN/MAX, POPCNT, etc.) that processes and schedules bidirectional MF-TLP traffic across the fabric between nodes) by: receiving, via the logic circuitry, a packet of the bi-directional traffic for an application executing between computing resources located at the first network site or infrastructure and the second network site or infrastructure (Paragraph 222, 249, These passages teach the MC-NIC logic receiving MF-TLP packets over a packet-switched fabric from distributed compute nodes executing workloads, thereby receiving application traffic between different network sites); and routing the packet to one or more insertable network services in accordance with a policy or contract based at least in part on the output value of the arithmetic or bitwise operator (Paragraph 305, 315, 308, These passages teach routing/handling of packets through programmable micro-op services and scheduling engines based on policy/resource contracts and per-tenant QoS constraints).
Crabtree et al. does not explicitly teach determining, via the arithmetic or bitwise operator, an output value, wherein the arithmetic or bitwise operator uses routing data from a packet header of the packet to determine the output value.
However, Ibanez et al. teaches determining, via the arithmetic or bitwise operator, an output value, wherein the arithmetic or bitwise operator uses routing data from a packet header of the packet to determine the output value (Paragraph 34, 44, 46, These passages teach using packet header data (e.g., tuples/metadata) as inputs to ALU operations that perform arithmetic/bitwise processing to generate computed results used in packet handling decisions).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide determining, via the arithmetic or bitwise operator, an output value, wherein the arithmetic or bitwise operator uses routing data from a packet header of the packet to determine the output value as taught by Ibanez et al. in the system of Crabtree et al., so that it would enable the pipelined logic circuitry of Crabtree to perform arithmetic or bitwise processing on packet header routing information to compute output values that support policy-based packet handling and routing decisions within the programmable packet-processing pipeline.
Regarding claim 2, Crabtree et al. teaches the packet is received at a second network device of the second network site or infrastructure, the second network device being configured to (i) receive the packet via logic circuitries of the second network device, (ii) determine via an arithmetic or bitwise operator of the second network device a second output value, wherein the arithmetic or bitwise operator of the second network device uses the routing data from the packet header of the packet to determine the second output value, and (iii) route the packet to one or more insertable network services of the second network site or infrastructure in accordance with the policy or contract based at least in part on the second output value of the arithmetic or bitwise operator of the second network device (Paragraph 122, 123, 124, 127, 200, 249-251, 254, These passages teach that a second memory-node MC-NIC at another rack receives MF-TLP packets via its protocol parsing and execution logic circuitry, parses header fields (including opcode and identifiers), executes arithmetic or logical operations within the NIC to generate computed results based on header-defined transaction data, and—under programmable, policy-driven pipeline selection—routes the transaction to one or more in-NIC executable services (e.g., atomic/reduction engines or programmable action units) at that network site in accordance with transaction-layer policies and the computed output value).
Regarding claim 3, Crabtree et al. teaches the routing of the packet to the one or more insertable network services in accordance with the policy or contract employs (i) the output value of the arithmetic or bitwise operator and (ii) a flag or identifier associated with the destination address being a local network device of a network associated with the network device (Paragraph 122, 124, 126, 136, 137, 175, 201–202, 204, These passages collectively teach that packet processing and subsequent routing/handling decisions are governed by arithmetic or logical output values produced by atomic/reduction engines and by explicit header identifiers (e.g., CDID, TID, Scope, and address-based LA keys) that determine whether the destination is local (rack/LCC scope) or requires broader network routing).
Regarding claim 4, Crabtree et al. teaches the arithmetic or bitwise operator comprises an arithmetic comparator (Paragraph 124, 223, 231, These passages teach that the atomic execution block performs compare-and-swap operations that require comparing expected and current values before conditionally updating).
Regarding claim 5, Crabtree et al. teaches the arithmetic or bitwise operator comprises an XOR bitwise comparator (Paragraph 223, 231, 254, These passages teach that the atomic engine implements XOR as a bitwise operation and performs comparison-based atomic logic).
Regarding claim 6, Crabtree et al. teaches one or more insertable network services includes at least one of a deep packet inspection (DPI) service, a load balancing (LB) service, an intrusion prevention system (IPS) service, a malware protection service, and a firewall inspection service (Paragraph 180, 168, 240, 249, 255, 263, These passages teach in-fabric packet parsing, inspection of header fields, tenant/ACL enforcement, capability validation, rate policing, and traffic scheduling that collectively perform packet inspection, filtering, and traffic distribution functions characteristic of DPI, firewall inspection, IPS-like enforcement, and load-balancing services executed within the network fabric).
Regarding claim 7, Crabtree et al. teaches the policy or contract includes at least one of a security policy, a performance policy, a quality-of-service (QOS) policy, a disaster recovery policy, and a visibility policy (Paragraph 130, 133, 156, 161, 168, 189, 219, These passages collectively teach policies governing security (capability/ACL validation and AAD authentication), performance (deadline-aware ordering and quota enforcement), QoS (priority scheduling and traffic class control), disaster recovery (durability classes and two-site mirrored commit), and visibility/governance).
Regarding claim 8, Crabtree et al. teaches the high-speed memory maintains a logic table that selects, via a single lookup action of the high-speed memory, a network action to route the packet to the one or more insertable network services in accordance with the policy or contract or to bypass the network action (Paragraph 248, 249, 251, 252, These passages teach that a memory-resident table (PCT and lookup tables) is accessed in a single classification/lookup step based on packet header fields to select a specific program/action (i.e., a network action) that governs how the packet is processed or forwarded).
Regarding claim 9, Crabtree et al. teaches the high-speed memory comprises tertiary content addressable memory (TCAM) or content addressable memory (CAM) (Paragraph 214, 215, 242, These passages teach that the system’s memory structures include content-addressable memory (CAM) components (e.g., a CAM front-end and Context CAM) integrated within high-speed memory structures).
Regarding claim 10, Crabtree et al. teaches the logic table includes a first rule to select the network action to route the packet to the one or more insertable network services in accordance with the policy or contract based on a first value for the arithmetic or bitwise operator and a masked value for a flag or identifier associated with the destination address being a local network device of a network associated with the network device (Paragraph 204, 224, 249, 252, 254, 255, These passages teach a table-driven rule structure (parser/PCT) that selects a processing/routing action based on arithmetic/bitwise evaluation of header fields (including ADD/BITAND and bit slicing) and masked tenant/domain or scope identifiers associated with the destination/address).
Regarding claim 11, Crabtree et al. teaches the logic table includes a second rule to select the network action to route the packet to the one or more insertable network services in accordance with the policy or contract based on a first value for the arithmetic or bitwise operator and a second value for a flag or identifier associated with the destination address being a local network device of a network associated with the network device (Paragraph 240, 249, 251, 254, 255, These passages teach a table-driven classification rule (lookup table) that selects a packet-processing action (network action) based on arithmetic/bitwise operation fields (first value) and header identifiers such as tenant/domain and capability checks tied to the destination address).
Regarding claim 12, Crabtree et al. teaches the logic table includes a third rule to bypass the network action to route the packet to the one or more insertable network services in accordance with the policy or contract based on a first value for the arithmetic or bitwise operator and a second value for a flag or identifier associated with the destination address being a local network device of a network associated with the network device (Paragraph 120, 122, 124, 126, 175, 204, 206, These passages collectively teach a programmable logic engine that parses packets, evaluates arithmetic/logical operation results, and uses domain/tenant/coherence identifiers and scope bits to determine whether to process locally (LOCAL scope within the associated network/rack) rather than route through broader fabric actions).
Regarding claim 13, Crabtree et al. teaches the policy or contract is defined at an inter-site controller or an intra-site controller, the policy or contract being provided from the inter-site controller or the intra-site controller to configure the logic table (Paragraph 200, 206, 212, 216, 249, These passages teach that policy-defining information (e.g., Domain Descriptors, Meta policy bits, and PCB configuration data) is defined at centralized/global controllers (GCD/orchestration service) or rack-local controllers (LCC), and is then provided to MC-NICs to configure their operational control structures).
Regarding claim 14, Crabtree et al. teaches a processor; and a memory having instructions stored thereon, wherein execution of the instructions by the processor causes the processor to (i) receive the policy or contract and (ii) store a routing action of the policy or contract to the high-speed memory (Paragraph 121, 123, 173, 249, 202, 214, These passages teach a processor-based MC-NIC system with memory-resident instruction execution that receives structured MF-TLP packets carrying transaction-layer policy/contract semantics via headers and extension fields, parses those directives, and stores resulting routing/coherence actions as directory records and policy metadata in high-speed directory SRAM governing fabric routing and ownership behavior).
Regarding claim 15, Crabtree et al. teaches the packet is a multicast packet and is received at the second network device of the second network site or infrastructure and a third network device of the second network site or infrastructure (Paragraph 208, 212, 232, 237, These passages teach that a single MF-TLP control/data packet (e.g., INV_SET or BROADCAST DATA) is replicated via multicast/group replication and received by multiple devices within the same rack (site), including multiple sharer nodes).
Regarding claim 16, Crabtree et al. teaches the packet is a multicast packet and is received at the second network device of the second network site or infrastructure and a third network device of a third network site or infrastructure (Paragraph 204, 208, 210, 212, 232, These passages teach that an MF-TLP packet (e.g., INV_SET or REVOKE_RO) is multicast via fabric-supported group replication to multiple racks (network sites), where the same packet is received by multiple LCCs/MC-NICs (network devices) at different racks).
Regarding claim 17, Crabtree et al. teaches a system comprising: a processor; and a memory having instructions stored thereon, wherein execution of the instructions by the processor causes the processor to: receive a policy or contract for a set of one or more insertable network services to execute between two or more network sites or infrastructure, including a first network site or infrastructure and a second network site or infrastructure (Paragraph 274-275, These passages teach receiving and utilizing centrally-defined policies (contracts) for controlling services (access control, QoS, crypto) across distributed network infrastructure spanning multiple nodes/sites); and transmit the policy or contract to one or more first network devices of the first network site or infrastructure, including a first network device, and one or more second network devices of the second network site or infrastructure, including a second network device (Paragraph 274-275, These passages teach distributing the policy from a control entity to multiple network devices (MC-NICs across nodes/sites) via caching and synchronized updates, i.e., transmitting policy/contract information to multiple devices across infrastructure), wherein the first network device and the second network device are configured to symmetrically route bi-directional traffic among each other (Paragraph 121, 204, These passages teach packet-switched fabric routing between racks and nodes in a bidirectional, symmetric topology where both sides send and receive MF-TLP traffic under the same protocol), wherein the first network device includes a high-speed memory and a logic circuitry operatively coupled to the high-speed memory (Paragraph 200, 214, These passages teach a network device (memory node) including high-speed memory (SRAM/DRAM/HBM) and integrated MC-NIC logic circuitry operatively coupled to that memory for packet processing and coherence execution), the logic circuitry being configured, via a pipeline operation comprising an arithmetic or bitwise operator, to symmetrically route bi-directional traffic with the second network device (Paragraph 197, 229, 254, These passages teach pipelined logic circuitry executing arithmetic and bitwise operators within a structured processing pipeline that processes and routes MF-TLP traffic symmetrically between fabric endpoints).
Crabtree et al. does not explicitly teach wherein the arithmetic or bitwise operator uses routing data from a packet header of a packet in the bi-directional traffic.
However, Ibanez et al. teaches wherein the arithmetic or bitwise operator uses routing data from a packet header of a packet in the bi-directional traffic (Paragraph 33, 34, 44, These passages teach ALU/pipeline operations that use packet header data (e.g., tuples, metadata) for processing and routing decisions).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide wherein the arithmetic or bitwise operator uses routing data from a packet header of a packet in the bi-directional traffic as taught by Ibanez et al. in the system of Crabtree et al., so that the pipelined logic circuitry performing packet processing and symmetric routing in Crabtree et al. could efficiently utilize packet header information as input to arithmetic or bitwise operations to make routing and processing decisions for packets traveling between the network devices across the distributed network infrastructure.
Regarding claim 18, Crabtree et al. teaches the bi-directional traffic is received at the second network device of the second network site or infrastructure, the second network device being configured to (i) receive the packet of the bi-directional traffic via logic circuitries of the second network device, (ii) determine via an arithmetic or bitwise operator of the second network device an output value derived from the routing data located within the packet, and (iii) route the packet to one or more insertable network services of the second network site or infrastructure in accordance with the policy or contract based at least in part on the output value of the arithmetic or bitwise operator of the second network device (Paragraph 120, 122, 123, 126, 249, 250, These passages collectively teach that a second-site MC-NIC network device receives packetized traffic via its hardware parsing logic, extracts routing-relevant header data, applies arithmetic or logical operators to derive execution results, and based on that processed header information dispatches the packet to selected programmable in-network execution engines (e.g., atomic, reduction, or action units) under tenant/domain and policy controls carried in the packet metadata).
Regarding claim 19, Crabtree et al. teaches the first network device is configured to route a packet to the set of one or more insertable network services in accordance with the policy or contract using (i) an output value determined from the arithmetic or bitwise operator and (ii) a flag or identifier associated with the destination address being a local network device of a network associated with the first network device (Paragraph 120, 126, 128, 175, 201, 204, These passages collectively teach that the MC-NIC (first network device) routes MF-TLP packets through coordinated fabric switches and controllers based on header-defined domain identifiers and scope flags (policy/contract), while executing arithmetic or logical operations to generate results that determine subsequent in-network processing and routing behavior toward appropriate local or domain-associated network elements).
Regarding claim 20, Crabtree et al. teaches the arithmetic or bitwise operator comprises an arithmetic comparator or an XOR bitwise comparator (Paragraph 124, 126, 223, 254, These passages teach that the MC-NIC executes atomic compare-and-swap operations (which includes a comparison function) and explicitly supports XOR as a bitwise operation).
Allowable Subject Matter
Based on the specification, the applicant could consider adding concepts that emphasize the multi-site software-defined networking context in which the device operates, such as the presence of an inter-site controller or orchestrator coordinating with intra-site controllers to manage end-to-end policies across independent yet interconnected data center fabrics. The claim could further reflect that the routing and service insertion are performed in the context of multi-site application-centric infrastructure (ACI) deployments that support fault-domain isolation, disaster recovery, or separate change domains. Additional concepts that could be incorporated include that the inserted services comprise specific L4–L7 services (e.g., firewall, load balancing, intrusion prevention, malware protection, or deep packet inspection) arranged in an ordered service chain, and that the symmetric routing ensures consistent traversal of the same service chain for both directions of East–West inter-site data center traffic. The applicant might also add that traffic is associated with policy-defined endpoint groups (EPGs), where routing and service insertion decisions are governed by macro-segmentation policies or contracts applied to groups of endpoints spanning multiple sites, thereby tying the arithmetic or bitwise pipeline operation more explicitly to policy-driven, group-based service chaining across geographically distributed data centers.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sharif et al. (US 20190190816 A1)
Singh (US 10069734 B1)
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ANDREW SHAJI KURIAN/Examiner, Art Unit 2464
/IQBAL ZAIDI/Primary Examiner, Art Unit 2464