DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida et al. (US Patent No. 11,762,580), hereinafter referred to as YOSHIDA, in view of BERT (US PGPub 2021/0157720).
Consider Claim 1,
YOSHIDA teaches a storage device comprising:
a memory including a persistent memory cache device and a zoned namespace drive memory capacity device (YOSHIDA, e.g., Fig 1(5);Fig 9;Col 7:22-28, shared write buffer (SWB) separate from super blocks (SB).); and
a memory controller coupled to the memory (YOSHIDA, e.g., Fig 1(4), controller.), the memory controller to:
translate a zoned namespace drive address logical block address (LBA) associated with a user write to a memory address write, wherein the memory address write is associated with a physical address for the memory (YOSHIDA, e.g., Col 9:25-35, zone to block translation; Fig 10, shows logical to physical translation. Further, all memory writes are associated with a physical address.);
collect a plurality of memory address writes including the memory address write and other memory address writes in the persistent memory cache tier (YOSHIDA, e.g., Fig 20;Col 32:54-33:24, collect writes into shared write buffer.); and
transfer, via an append-type zoned namespace drive write command, the collected plurality of memory address writes from the persistent memory cache to the zoned namespace drive memory capacity (YOSHIDA, e.g., Col 33:18-24, transfer collected writes in SWB to zone super block (SB).).
YOSHIDA describes a partitioned memory system with one area serving as a buffer, but fails to expressly describe a tiered memory wherein the memory capacity device is separate from the persistent memory cache device. BERT is directed towards systems and methods for improved filesystem support in ZNS systems and is considered analogous prior art. BERT does describe the use of a tiered memory wherein the memory capacity device is separate from the persistent memory cache device (i.e., an SSD and NVDIMM) (BERT, e.g., ¶0021, hybrid storage; ¶0018, persistent cache; ¶0019, DRAM is used as a non-volatile buffer for metadata and host data; ¶0016, memory device includes an NVDIMM which is DRAM. It is noted that a hybrid system is plural distinct devices operating together. In this case it is an SSD and an NVDIMM.). It would have been obvious to a person of ordinary skill in the art, prior to the effective filing date of the claimed invention, to modify the system of YOSHIDA to include the hybrid/tiered memory as taught by BERT because it allows faster access to buffered/cached data due to the improved performance characteristics enabled by the multiple memories (BERT, e.g., ¶0018, persistent memory region is DRAM.).
Consider Claim 2,
The system of YOSHIDA and BERT, as combined, further teaches the memory controller further to: isolate the collected plurality of tiered memory address writes to one or more zones of the zoned namespace drive memory capacity device on one or more of the following basis: a virtual machine-by-virtual machine basis, an application instance-by-application instance basis, or a thread-by-thread basis (YOSHIDA, e.g., Col 15:51-57, application based zones.).
Consider Claim 3,
The system of YOSHIDA and BERT, as combined, further teaches the memory controller further to: reorder the collected plurality of tiered memory address writes to a sequential data order in response to an access pattern associated with an individual application, wherein the reorder of the collected plurality of tiered memory address writes is performed prior to the transfer from the persistent memory cache device to the zoned namespace drive memory capacity device (YOSHIDA, e.g., Fig 11, shows reordering data from SB1, SB11, SB12 of the shared write buffer into superblock SB10 of the zoned namespace.).
Consider Claim 4,
The system of YOSHIDA and BERT, as combined, further teaches the memory controller further to:
monitor a fullness of a write queue depth associated with the collected plurality of tiered memory address writes, wherein the write queue depth is equal to a single zone of the zoned namespace drive memory capacity device (YOSHIDA, e.g., Fig 20(S15), check if size of writes queued from a certain zone is equal to a zone size.); and
in response to the fullness of the write queue depth, performing the transfer of the collected plurality of tiered memory address writes from the persistent memory cache device to the zoned namespace drive memory capacity device (YOSHIDA, e.g., Fig 20(S16), transfer data in response to queue size filling one zone unit.).
Consider Claim 5,
The system of YOSHIDA and BERT, as combined, teaches the storage device of claim 1, above, and further teaches the memory controller further to: monitor a number of free zones in the zoned namespace drive memory capacity device (YOSHIDA, e.g., Col 30:45-53, empty/free zone list).
The system of YOSHIDA and BERT, as combined, describes garbage collection and the use of free zone lists, but fails to expressly describe performing garbage collection in response to the monitored number of free zones in the zoned namespace drive memory capacity device. The examiner takes official notice of the fact that performing garbage collection based on an amount of free space is notoriously well-known in the art. It would have been obvious to a person of ordinary skill in the art, prior to the effective filing date of the claimed invention, to modify the system of YOSHIDA and BERT to perform garbage collection in response to the monitored number of free zones in the zoned namespace drive memory capacity device because it improves system performance.
Consider Claim 6,
The system of YOSHIDA and BERT, as combined, teaches the storage device of claim 1, above, and further teaches the memory controller further to: monitor a validity of utilized zones in the zoned namespace drive memory capacity device (YOSHIDA, e.g., Fig 12, shows valid and invalid data.); and select a garbage collection zone in response to the monitored validity of the utilized zones (YOSHIDA, e.g., Fig 22, perform garbage collection based on data validity.).
Consider Claim 7,
The system of YOSHIDA and BERT, as combined, further teaches the memory controller further to: transfer data from both the persistent memory cache device and the zoned namespace drive memory capacity device in response to a user read request (YOSHIDA, e.g., Col 31:40-47, describes reading data from its current location; Fig 9, data may be located in SB of buffer or SB of zone.).
Consider Claim 8,
The system of YOSHIDA and BERT, as combined, further teaches wherein the persistent memory cache device has a first endurance level and a first performance speed that are both higher than a second endurance level and a second performance speed of the zoned namespace drive memory capacity device, and wherein the persistent memory cache device is a crosspoint persistent memory and the zoned namespace drive memory capacity device is a NAND memory (BERT, e.g., ¶0018 persistent memory region may be crosspoint memory and zoned namespace region is NAND.).
Claims 9-20 are directed towards an apparatus and media having substantially identical scope to claims 1-8 and are therefore rejected for the same reasons.
Response to Arguments
Applicant's arguments filed 01JAN2025 have been fully considered but they are not persuasive.
The applicant argues that YOSHIDA fails to teach a cache and a memory capacity distinct from the cache. The examiner notes that BERT is relied upon to teach these features as noted in the rejections above. Thus, in response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Since the applicant has not challenged or traversed the official notice taken in the previous office action the examiner will consider the subject matter of the official notice to be considered admitted prior art.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Gary W Cygiel whose telephone number is (571)270-1170. The examiner can normally be reached Monday - Thursday 11am-3pm PST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan P Savla can be reached at (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Gary W. Cygiel/Primary Examiner, Art Unit 2137