DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Drawing Objections
Applicant has amended the drawings at issue and the previous objections have therefore been withdrawn.
Claim Rejections – 35 USC 112
Applicant has amended the claims at issue and the previous rejections have therefore been withdrawn.
Claim Rejections – 35 USC 101
Applicant's arguments filed 5/21/2026 have been fully considered.
Applicant asserts claims 1, 12 do not recite an abstract idea, as the claims have been amended to recite processing performed by a signal processing system of a radar system or communication and an arrangement of dedicated circuitry to perform the FFT.
Examiner respectfully disagrees. The limitations added to the amended claims do not change the previously identified limitations reciting mathematical and/or mental processes, thus claims 1, 12 recite abstract ideas. Furthermore, the additional circuits recited in the amended claims are no more than reciting the equivalent of “apply it” to the judicial exceptions. The Examiner notes the recitation of “processing performed by a signal processing system of a radar system or communication system” is recited in the preamble of claims 1, 12. However, the preamble of claim 1 merely recites purpose or intended use as it does not provide structural limitations. See MPEP 2111.02. For claim 12, the recitation of “processing performed by a signal processing system of a radar system or communication system” is merely generally linking the invention to a technological field because the claimed invention does not integrate aspects of signal processing in a radar system or communication system such that it is more than merely reciting a technological field the claim is applied in. Therefore, claims 1, 12 are directed to a judicial exception.
Applicant asserts the claimed invention is integrated into a practical application of signal processing system of a radar system or communication system with a specific arrangement and function of circuitry, wherein the claimed system increases effective FFT resolution without increasing register width under fixed hardware resource constraints and improves digital signal processing pipeline operation.
Examiner respectfully disagrees. As discussed above, the application of a signal processing system of a radar system or communication system is merely generally linking the invention to a technological field, and the additional circuitry are the equivalent of reciting “apply it” to the mathematical and/or mental process functions. Furthermore, the improvement of the system of increasing FFT computation resolution of the claimed system of claims 1 and 12 is a result of the mathematical and/or mental process functions alone. However, the judicial exception alone cannot provide the improvement. See MPEP 2106.05(a). Therefore, claims 1, 12 are not integrated into a practical application.
Applicant asserts claims 1, 12 are significantly more than the judicial exception as the claimed circuitry and associated processing are not well-understood, routine, or conventional.
Examiner respectfully disagrees. The newly added additional elements of circuitry are merely the equivalent of reciting “apply it” to the judicial exception as discussed above and are not insignificant extra-solution activities. Thus, the analysis of the additional elements as well-understood, routine, or conventional only applies to the previously indicated “receiving” limitations and do not apply to the newly added additional elements of circuitry.
However, the Examiner notes claims 10-11, 19-20 would be patent eligible if rewritten in independent form. The claims are directed to accessing a lookup table that indicates the number of bits to be shifted based on the leading bit count when applying the adaptive right or left shift. Accessing the lookup table to indicate a number of bits to be shifted is an additional element that does not include mathematical calculation or mathematical relationship, and when provided in combination with the limitations of the claim as a whole, contributes to the improvement of increasing the effective FFT resolution without increasing register width under fixed hardware resource constraints. Therefore, the claimed system of claims 10-11, 19-20 recites a combination of additional elements that is more than reciting the equivalent of “apply it” to an abstract idea, and contributes to the improvement such that the improvement is not a result of the judicial exception alone. Therefore, the rejections for claims 10-11, 19-20 have been withdrawn, while the rejections for claims 1-9, 12-18 are maintained.
Claim Interpretation
The Examiner interprets the preamble of “a method for a signal processing system in a communication system or radar system to perform a Fast Fourier Transformation” of claims 1-11 as not limiting because the body of the claim describes a complete invention and the language recited solely in the preamble does not provide any distinct definition of any of the claimed invention’s limitations. Thus, the preamble of claims 1-11 are not considered a limitation and is of no significance to claim construction.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-9, 12-18 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding claim 1, at Step 1, the claim is directed to a method, which is a statutory category of invention (Process).
At Step 2A Prong 1, Examiner notes that the claims are directed towards an abstract idea. The claim language has been reproduced below:
A method for a signal processing system in a communication system or radar system to perform a Fast Fourier Transformation (FFT), the method comprising:
receiving a first input at a first radix kernel circuit signed binary integers, the signed binary integers of the first input each representing a component of a complex number associated with a time domain signal and having a bit width (mathematical relationship);
applying, by a left shift circuit of the first radix kernel circuit, a fixed left shift to the signed binary integers of the first input (mathematical process, mental process);
performing, by the first radix kernel circuit, a first radix kernel operation on the shifted first input at a higher bit resolution than the bit width (mathematical process);
applying, by a right shift circuit of the first radix kernel circuit, a fixed right shift to signed binary integers of an output of a butterfly circuit of the first radix kernel circuit which are mapped to the bit width to provide a first output (mathematical process, mental process) of a first stage of an FFT circuit;
determining, by a leading bit analyzer circuit coupled to a controller circuit, a leading bit count of signed binary integers in the first output (mathematical process, mental process);
receiving the first output at a second radix kernel circuit of the FFT circuit which is a second input to the second radix kernel circuit, wherein the first radix kernel circuit is coupled to the second radix kernel circuit to receive the first output as the second input;
applying, by a left shift circuit of the second radix kernel circuit, an adaptive left shift to signed binary integers of the second input based on the leading bit count (mathematical process, mental process), an indication of the adaptive left shift output (mathematical relationship) by the controller circuit the controller circuit coupled to the second radix kernel circuit;
performing, by the second radix kernel circuit, a second radix kernel operation on the shifted second input at the bit resolution higher than the bit width (mathematical process);
and applying, by a right shift circuit of the second radix kernel circuit, an adaptive right shift based on the leading bit count to signed binary integers of an output (mathematical process, mental process) of a butterfly circuit of the second radix kernel circuit which is mapped to the bit width to provide a second output (mathematical relationship) of a second stage of the FFT circuit, an indication of the adaptive right shift output (mathematical relationship) by the controller circuit;
wherein the adaptive left shift and adaptive right shift determines a resolution of the FFT which is based on the second output (mathematical relationship).
At Step 2A Prong 2, the additional elements are bolded above. The additional elements do not integrate the abstract ideas into a practical application because the computer elements, which are recited at a high level of generality, provide conventional computer functions that do not impose any meaningful limits on practicing the abstract ideas. See MPEP 2106.05(f). The limitations of a first radix kernel circuit, a left shift circuit of the first radix kernel circuit, a right shift circuit of the first radix kernel circuit, a butterfly circuit of the first radix kernel circuit, a leading bit analyzer circuit coupled to a controller circuit, a second radix kernel circuit of the FFT circuit, a left shift circuit of the second radix kernel circuit, a right shift circuit of the second radix kernel circuit, and a butterfly circuit of the second radix kernel circuit are the equivalent of reciting “apply it” with the judicial exception. The limitations of receiving a first input and receiving the first output are merely insignificant extra-solution activity of data gathering. Even when viewed in combination, these additional elements do not integrate the recited judicial exception into a practical application and the claim is directed to the judicial exception.
At Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception As set forth in step 2A prong 2 analysis, the functions of receiving a first input and receiving the first output is recognized by the courts as well-understood routine and conventional. See MPEP 2106.05(d)(II). Furthermore, the a first radix kernel circuit, a left shift circuit of the first radix kernel circuit, a right shift circuit of the first radix kernel circuit, a butterfly circuit of the first radix kernel circuit, a leading bit analyzer circuit coupled to a controller circuit, a second radix kernel circuit of the FFT circuit, a left shift circuit of the second radix kernel circuit, a right shift circuit of the second radix kernel circuit, and a butterfly circuit of the second radix kernel circuit are the equivalent of adding the words “apply it” to the judicial exception and are mere instructions to implement the abstract idea on a computer. Even when considered in combination, these additional elements represent mere insignificant extra-solution activities, which do not provide an inventive concept. The claim is not eligible.
Regarding claim 2, it is directed to the mathematical concept and/or mental process of until the first input is transformed into the frequency domain.
Under Step 2A Prong 2, the claim recites additional element “providing an output of one radix kernel circuit to an input of another radix kernel circuit”. The additional element does not integrate the abstract ideas into a practical application because the providing is recited at a high level of generality and do not impose any meaningful limits on practicing the abstract idea. Even when viewed in combination, these additional elements do not integrate the recited judicial exception into a practical application and the claim is directed to the judicial exception.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception. Even when considered in combination, these additional elements represent mere instructions to apply an exception and insignificant extra-solution activity, which do not provide an inventive concept. The claim is not eligible.
Regarding claims 3-9, the claims merely recite functions for determining the leading bit count, properties of the outputs, properties of the kernel operations, or properties of the adaptive shifting, that further mathematically limit the mathematical concepts, or provide additional mathematical functions, of claim 1. They do not include additional elements that would require further analysis under steps 2A prong 2 and step 2B.
Regarding claims 12, 15-18, the claims are directed to a system that performs the method of claims 1, 3, 5, 8-9, respectively. The system of claims 12, 15-18 performs all steps of the method of claims 1, 3, 5, 8-9, respectively. The analysis of claims 1, 3, 5, 8-9, respectively applies equally to claims 12, 15-18.
Regarding claims 13, the claims merely recite functions for properties of the kernel operation, or properties of the butterfly operation that further mathematically limit the mathematical concepts, or provide additional mathematical functions, of claim 12. They do not include additional elements that would require further analysis under steps 2A prong 2 and step 2B.
Allowable Subject Matter
Claims 1-9, 12-18 would be allowable if rewritten to overcome the rejections under 35 USC 101 set forth in this Office Action. Claims 10-11, 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The statement of reasons for the indication of allowable subject matter was provided in the Non-Final Office Action mailed 02/24/2026.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/P.N.L./
Phat LeExaminer, Art Unit 2182 (571) 272-0546
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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