DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
2. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Arguments
3. Applicant’s arguments (see Remarks dated 12/30/2025) with respect to the previous 103 rejection of claims 1-20 (over Hamada in view of Nishida) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, new grounds of rejection are made below, over reference Matsuyama (US 6724068 B2).
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 USC 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
5. Claims 1-12 and 15-20 are rejected under 35 USC 102(a)(1) as being anticipated by Matsuyama (US 6724068 B2).
Regarding claim 1, Matsuyama discloses a semiconductor optical device (Abstract) comprising:
a semiconductor layer (column 6 line 34, buffer layer 2) having a projection on an upper surface (Figs. 1 & 6, upwardly convex portion of 2), the projection extending in one stripe shape in a first direction and constituting a bottom of a mesa stripe structure (Fig. 5 & column 6 lines 35-40, ST);
a multiple quantum well layer (column 6 line 38, active layer 3) extending in the first direction on the projection of the semiconductor layer (Fig. 5, 3) and constituting another portion of the mesa stripe structure (column 6 lines 37-38, “ST has a laminated structure of…InGaAsP-MQW active layer 3”);
a pair of first semiconductor layers (column 6 line 48, burying layer 7) in contact with the mesa stripe structure on respective both sides in a second direction perpendicular to the first direction (Figs. 1 & 6-7, 7);
a pair of second semiconductor layers (column 6 lines 54-55, etching stop layer 11), on respective both sides of the projection in the second direction (Figs. 1 & 6-7, 11), on the upper surface of the semiconductor layer (Fig. 6, 11 is on the upper surface of 2);
a pair of resin layers (column 6 line 65, resin layer 13) above the pair of second semiconductor layers (Fig. 1, 13 is above 11);
a pair of third semiconductor layers (column 6 line 50, cladding layer 9) on the pair of second semiconductor layers (Figs. 1 & 7, 9 is on 11), each of the pair of third semiconductor layers surrounding a corresponding one of the pair of resin layers (Fig. 1, each 9 surrounds 13), the pair of third semiconductor layers being different in constituent material from the pair of second semiconductor layers (column 6 lines 48-59, 9 is made from p-type InP, 11 is made from p-type InGaAsP);
a first electrode (column 6 line 66, electrode 16) on a lower surface of the semiconductor layer (Fig. 1, 16 is on a lower surface of 2); and
a second electrode including a mesa electrode (column 6 line 62, electrode 14 and bonding pad 15) on a top surface of the mesa stripe structure (Fig. 1, 14 and 15 are on top of ST), the second electrode including a lead-out electrode extending in the second direction from the mesa electrode (Fig. 1, 14), the second electrode including a pad electrode above one of the pair of resin layers (Fig. 1, 15), the pad electrode being connected to the lead-out electrode (Fig. 1).
Regarding claim 2, Matsuyama discloses wherein the pair of first semiconductor layers, the pair of second semiconductor layers, and the pair of third semiconductor layers constitute a buried layer to the multiple quantum well layer (column 6 line 48, burying layer 7), the buried layer has a pair of recesses (Fig. 1, two large recesses shown), and the pair of resin layers are in the respective pair of recesses (Fig. 1, 13 is in the recesses).
Regarding claim 3, Matsuyama discloses wherein each of the pair of third semiconductor layers surrounds the corresponding one of the pair of resin layers from every circumferential direction including the first direction and the second direction (Fig. 1, 9 surrounds 13).
Regarding claim 4, Matsuyama discloses wherein each of the pair of third semiconductor layers has a side surface exposed in at least one of the first direction and the second direction (Fig. 1, 9).
Regarding claim 5, Matsuyama discloses wherein the pair of first semiconductor layers extend below the respective pair of second semiconductor layers (Fig. 6) and in contact with the upper surface of the semiconductor layer (Fig. 6).
Regarding claim 6, Matsuyama discloses wherein each of the pair of second semiconductor layers extends between a corresponding one of the pair of first semiconductor layers and a corresponding one of the pair of resin layers (Fig. 1).
Regarding claim 7, Matsuyama discloses wherein the pair of first semiconductor layers are different in the constituent material from the pair of second semiconductor layers (column 6 lines 48-59, 7 is made from p-type InP, 11 is made from p-type InGaAsP).
Regarding claim 8, Matsuyama discloses wherein the pair of third semiconductor layers are the same in the constituent material as the pair of first semiconductor layers (column 6 lines 48-50, 9 and 7 are made from p-type InP).
Regarding claim 9, Matsuyama discloses wherein each of the pair of third semiconductor layers is continuous to a corresponding one of the pair of first semiconductor layers (Fig. 7).
Regarding claim 10, Matsuyama discloses further comprising an inorganic insulating film interposed between each of the pair of resin layers and a corresponding one of the pair of second semiconductor layers (Fig. 1, 7 and 9).
Regarding claim 11, Matsuyama discloses wherein the inorganic insulating film is also interposed between each of the pair of resin layers and a corresponding one of the pair of first semiconductor layers (Fig. 1, 7 and 9).
Regarding claim 12, Matsuyama discloses wherein the inorganic insulating film is also interposed between each of the pair of resin layers and a corresponding one of the pair of third semiconductor layers (Fig. 1, 7 and 9).
Regarding claim 15, Matsuyama discloses an inorganic spacer interposed between the pad electrode and the one of the pair of resin layers (Fig. 1, 9 is between 15 and 13).
Regarding claim 16, Matsuyama discloses wherein the upper surface of the semiconductor layer, except for the projection, is lower than a bottom edge of the multiple quantum well layer (Fig. 1, upper surface of 2 is lower than bottom of 3).
Regarding claim 17, Matsuyama discloses wherein part of the mesa electrode is on the pair of resin layers (Fig. 1, 14 and 15 are on 13).
Regarding claim 18, Matsuyama discloses wherein the pair of resin layers are higher in height from the upper surface of the semiconductor layer than the pair of first semiconductor layers (Fig. 1, 13 is higher from 2 than 7).
Regarding claim 19, Matsuyama discloses wherein the semiconductor optical device is an electro-absorption modulator (column 5 lines 30-33).
Regarding claim 20, Matsuyama discloses a semiconductor laser (column 4 lines 28-30), wherein the semiconductor optical device is a modulator-integrated semiconductor laser (column 5 lines 30-33) in which the electro-absorption modulator and the semiconductor laser are monolithically integrated (Fig. 1).
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 USC 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. The factual inquiries for establishing a background for determining obviousness under 35 USC 103 are summarized as follows:
1) Determining the scope and contents of the prior art.
2) Ascertaining the differences between the prior art and the claims at issue.
3) Resolving the level of ordinary skill in the pertinent art.
4) Considering objective evidence present in the application indicating obviousness or nonobviousness.
8. Claims 13-14 are rejected under 35 USC 103 as being unpatentable over Matsuyama.
Regarding claims 13 and 14, Matsuyama fails to disclose wherein the pair of first semiconductor layers are made of a semi-insulating semiconductor, and wherein the pair of second semiconductor layers are made of an intrinsic semiconductor.
However, in each instance, it would have been obvious to one of ordinary skill in the art at the time the invention was made to adjust the material of Matsuyama’s first and second pairs of semiconductor layers such that the first pair of semiconductor layers was made of a semi-insulating semiconductor, and such that the second pair of semiconductor layers was made of an intrinsic semiconductors, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of design choice, In re Leshin, 125 USPQ 146.
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Daniel Jeffery Jordan whose telephone number is 571-270-7641. The examiner can normally be reached 9:30a-6:00p.
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/D. J. J./Examiner, Art Unit 2872
/STEPHONE B ALLEN/Supervisory Patent Examiner, Art Unit 2872
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