DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
1. Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file. a. Certified copy of application CN202010124376.9 was received on 10/14/22.
2. The present application is a continuation of application PCT/CN2021/073181 filed 01/22/2021.
Response to Arguments/Amendments
3. Regarding the 35 USC § 112(b) rejections, the Applicant’s amendments have been fully considered; the newly amended claim language overcomes the previously applied rejection, which has been withdrawn.
4. Regarding the prior art rejection in view of the amended claims, the Applicant’s arguments have been fully considered, but are not persuasive. The Applicant argues that the prior art does not teach two features of the amended claims: 1) the slave acknowledgement signal; and 2) the reset master interrupt and reset slave acknowledgement signals. Regarding element 1), secondary reference Hempstead (US 20070214374 A1) discloses a secondary processor sending an ACK signal in response to being switched on by the primary processr (see paragraph [0049] and Table 2 and Fig. 3) This is an acknowledgement signal from a slave, i.e. a slave acknowledgement. Regarding 2), the instant application explicitly discloses that the reset signals can be understood to be the absence of the parent signals (e.g. the “reset master interrupt” is essentially the lack of the “master interrupt”; see paragraph [0041] of the instant application). The primary reference discloses this in the transmission of the primary “master interrupt” signal as a finite duration message (i.e. it also discloses the transmission of the absence of the signal). The Applicant’s arguments are therefore unpersuasive.
Claim Objections
5. Claims 2 – 3 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
6. Claim 4 is objected to because of the following informalities: there are a number of instances in the claim which reference “dada” packets or sub packets. This is intended to be “data”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
7. Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 4 recites a “second threshold”. There is no first threshold in claim 4 or the parent claim. A second threshold requires a first threshold, and it is unclear to the Examiner if this is intended to incorporate the “first threshold” of unrelated claims 2 and 3. The claim is therefore indefinite, and rejected.
8. Claims 5 – 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 5 recites “in response to detecting a downlink packet… generating… a data transmission instruction” and then further recites “generating the downlink packet… based on the data transmission instruction”. The Examiner notes that the order of operations here contains an inconsistency—the instruction is generated based on detecting the DL packet, but the packet is also claimed to be generated based on the instruction. The claim is therefore indefinite, and rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. Claim(s) 1, 9 – 17, and 19 - 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20210099972 A1) in view of Hempstead (US 20070214374 A1).
Regarding claim 1, Lee discloses subject matter related to coprocessor processing of data. Specifically, Lee discloses a processor communication method, implemented by an electronic device comprising a first processor and a second processor (CP and AP; see, paragraph [0103] and Fig. 8) and the method comprising;
transmitting a master interrupt signal to the second processor by the first processor in response to detecting a downlink packet (CP transmits activation request/user data TX to AP in response to earlier paging message; see paragraphs [0120 – 0129] and Fig. 8; the Examiner notes that paging messages indicate a DL packet; AP can be activated after user data is received; see paragraph [0145]; this signal can be an interrupt; see paragraph [0197]);
receiving, by the first processor, a first slave acknowledge signal returned by the second processor based on the first master interrupt signal (CP receives transmit user data response signal from AP based on the first master interrupt signal; see paragraph [0147] and Fig. 8)
transmitting the downlink packet to the second processor based on the slave acknowledge signal and (data is transmitted to AP; see paragraph [0144] and Fig. 8);
upon completion of transmitting the downlink packet, resetting, by the first processor, the master interrupt signal and transmitting a reset master interrupt signal to the second processor (activation request/user data TX are transmitted as transient signals (i.e. after they are transmitted, they stop being transmitted); see paragraphs [0129 – 0148] an Fig. 8; the Examiner understands the “reset master interrupt signal” to be the absence of the “master interrupt signal”, as is consistent with the instant Specification at e.g. paragraph [0041]); wherein the reset master interrupt signal is configured to instruct the second processor to reset the slave acknowledge signal and transmit a reset slave acknowledge signal to the first processor after completion of processing the downlink packet (AP transmits user data response signal to CP following processing of data as a transient signal (i.e. after they are transmitted, they stop being transmitted); see paragraph [0147] and Fig. 8; the Examiner understands the “reset slave acknowledge signal” to be the absence of the “slave acknowledge signal”, as is consistent with the instant Specification at e.g. paragraph [0041]).
Lee does not explicitly disclose transmitting the DL packet based on the slave acknowledge signal.
Hempstead discloses subject matter relating to coprocessors. Specifically, Hempstead discloses:
(when activating the coprocessor with SWITCHON command, first processor expects an ACK from second (slave) processor, which is followed by a data write; see paragraph [0049] and Table 2 and Fig. 3)
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to combine the disclosure of Lee with Hempstead by specifying that the first interrupt signal is ACKed, prior to sending the data. One of ordinary skill in the art would have found it obvious to do so, as this would let the first processor know that it is OK to send data to the second processor; Lee also indirectly discloses part of this (see paragraph [0206]), and discloses an acknowledgement signal for subsequent communication steps (see paragraph [0147 - 0148]). Further, ACK are widely used in the art prior to sending data, and doing so would have been a use of a technique known in the art to improve a similar device, with predictable results, which has been determined by the Supreme Court to be obvious (see KSR Int'l Co. v. Teleflex, Inc., 550 U.S. 398 (2007)).
Regarding claims 9 and 19, Lee and Hempstead teach the subject matter of the parent claim(s). Lee and Hempstead do not explicitly disclose the process of claims 9 and 19.
However, it would be obvious to modify the teaching of Lee and Hempstead to be used with UL packets as well as DL packets (meeting the limitations of claims 9 and 19). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to do so, as the method of using another processor to process packets would work equally well with UL as with DL, and would allow more processing to be offloaded from the main processor. The choice to use UL rather than DL is a selection between a finite number of options, with a reasonable expectation of success, which has been determined by the Supreme Court (see KSR Int'l Co. v. Teleflex, Inc., 550 U.S. 398 (2007)) to be obvious to one of ordinary skill in the art at the time of the invention.
Regarding claim 10, Lee and Hempstead teach the subject matter of the parent claim(s). Lee further discloses
acquiring a data transmission request initiated by an application (paging message; see paragraph [0124] and Fig. 8);
calling a data interface corresponding to a data type contained in the data transmission request (service type is identified; see paragraph [0125 – 0126] and Fig. 8; the Examiner understands a data interface to be any use of data); and
generating, by the first processor in response to the data interface belonging to the first processor, the downlink packet based on data received by the data interface; or, generating by the first processor, in response to the data interface belonging to the second processor, the uplink packet based on data received by the data interface (packet is processed based on service type; see Fig. 8 and associated description).
Regarding claim 11, Lee and Hempstead teach the subject matter of the parent claim(s). Lee further discloses wherein the first processor and the second processor are connected through a master interrupt interface, a slave acknowledge interface, a slave interrupt interface, a master acknowledge interface, and a data transmission interface (AP and CP share an interface; see Fig. 7; the Examiner understands an interface that sends a particular signal to be an interface of that type);
the master interrupt interface is configured to transmit the master interrupt signal and the reset master interrupt signal (CP transmits activation request/user data TX to AP in response to earlier paging message; see paragraphs [0120 – 0129] and Fig. 8; data is transmitted to AP; see paragraph [0144] and Fig. 8; the Examiner understands the broadest reasonable interpretation of an interrupt signal as any signal alerting the processor to do something, and understands the transmission of user data to fall under this)
the slave acknowledge interface is configured to transmit the slave acknowledge signal and the reset slave acknowledge signal (AP transmits user data response signal to CP following processing of data; see paragraph [0147 - 0148] and Fig. 8).
the slave interrupt interface is configured to transmit the slave interrupt signal and the reset slave interrupt signal (AP transmits user data response signal to CP following processing of data; see paragraph [0147 - 0148] and Fig. 8);
the master acknowledge interface is configured to transmit the master acknowledge signal and the reset master acknowledge signal (CP transmits activation request to AP in response to earlier paging message; see paragraphs [0120 – 0129] and Fig. 8; data is transmitted to AP; see paragraph [0144] and Fig. 8; the Examiner notes that the master acknowledgement signals are taught by the combination of Lee and Hempstead in the parent claim)
the data transmission interface is configured to transmit at least one of the downlink packet and the uplink packet (transmit user data; see Fig. 8)
Regarding claim 12, Lee and Hempstead teach the subject matter of the parent claim(s). Lee further discloses wherein the first processor and the second processor are further connected through a data transmission interface (AP and CP are connected; see Fig. 8), and after transmitting a master interrupt signal to the second processor by the first processor, the method further comprises:
making, by the second processor based on the first master interrupt signal, the data transmission interface be available for transmission of the downlink packet (data is transmitted; see Fig. 8), and returning, by the second processor, the slave acknowledge signal to the first processor (CP receives transmit user data response signal from AP based on the first master interrupt signal; see paragraph [0147] and Fig. 8)
Regarding claim 13, Lee and Hempstead teach the subject matter of the parent claim(s). Lee further discloses wherein the first processor and the second processor are further connected through a slave acknowledge interface, and the method, after making, by the second processor based on the master interrupt signal the data transmission interface available for transmission of the downlink packet, further comprises:
setting the slave acknowledge interface to a high-level state by the second processor; wherein the high-level state represents the slave acknowledge signal (AP activates; see paragraph [0130] and Fig. 8)
Regarding claim 14, Lee and Hempstead teach the subject matter of the parent claim(s). Lee further discloses wherein the method, after transmitting the reset slave acknowledge signal by the second processor, further comprises:
setting the slave acknowledge interface to a low-level state by the second processor; wherein the low-level state represents the reset slave acknowledge signal (AP idles when not in use (i.e. after second slave ACK); see paragraph [0104]; AP switches to active state when needed; see paragraphs [0130] and Fig. 8)
Regarding claim 15, Lee and Hempstead teach the subject matter of the parent claim(s). Lee further discloses after setting the slave acknowledge interface to a low-level state by the second processor, further comprising:
Making, by the second processor the data transmission interface available for transmission of other data (interface is eventually used; see paragraphs [0104], [0206 – 0207] and Fig. 8)
Regarding claim 16, Lee and Hempstead teach the subject matter of the parent claim(s). Lee further discloses wherein the first processor integrates a first system, the second processor integrates a second system (AP and CP; see Fig. 7; the Examiner notes that they necessarily integrate their own systems), and power consumption of the first system is higher than power consumption of the second system (AP idles while CP is active; see paragraph [0104] and Fig. 8).
Regarding claim 17, Lee discloses an electronic device, wherein the electronic device comprises a memory, a first processor, and a second processor, and the first processor and the second processor are connected through a data transmission interface (device with connected processors and memory; see Fig. 2); the memory is stored with a computer program (code; see paragraph [0204]), and the computer program is configured to, when executed by the first processor, cause the first processor to implement:
transmitting a master interrupt signal to the second processor in response to detecting a downlink packet (CP transmits activation request/user data tx to AP in response to earlier paging message; see paragraphs [0120 – 0129] and Fig. 8; the Examiner notes that paging messages indicate a DL packet; AP can be activated after user data is received; see paragraph [0145]; this signal can be an interrupt; see paragraph [0197]), wherein the master interrupt signal is configured to instruct the second processor to make the data transmission interface available for the transmission of the downlink packet upon receiving the first master interrupt signal, and return a slave acknowledge signal (AP activates (locks); see paragraph [0130] and Fig. 8; CP receives transmit user data response signal from AP based on the first master interrupt signal; see paragraph [0147] and Fig. 8);
receiving the slave acknowledge signal returned by the second processor (CP receives transmit user data response signal from AP; see paragraph [0147] and Fig. 8)
transmitting, through the data transmission interface, the downlink packet to the second processor based on the slave acknowledge signal and (data is transmitted to AP; see paragraph [0144] and Fig. 8);
upon completion of transmitting the downlink packet, resetting, by the first processor, the master interrupt signal and transmitting a reset master interrupt signal to the second processor (activation request/user data TX are transmitted as transient signals (i.e. after they are transmitted, they stop being transmitted); see paragraphs [0129 – 0148] an Fig. 8; the Examiner understands the “reset master interrupt signal” to be the absence of the “master interrupt signal”, as is consistent with the instant Specification at e.g. paragraph [0041]); wherein the reset master interrupt signal is configured to instruct the second processor to reset the slave acknowledge signal and transmit a reset slave acknowledge signal to the first processor after completion of processing the downlink packet (AP transmits user data response signal to CP following processing of data as a transient signal (i.e. after they are transmitted, they stop being transmitted); see paragraph [0147] and Fig. 8; the Examiner understands the “reset slave acknowledge signal” to be the absence of the “slave acknowledge signal”, as is consistent with the instant Specification at e.g. paragraph [0041]).
Lee does not explicitly disclose transmitting the DL packet based on the slave acknowledge signal.
Hempstead discloses subject matter relating to coprocessors. Specifically, Hempstead discloses:
(when activating the coprocessor with SWITCHON command, first processor expects an ACK from second (slave) processor, which is followed by a data write; see paragraph [0049] and Table 2 and Fig. 3)
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to combine the disclosure of Lee with Hempstead by specifying that the first interrupt signal is ACKed, prior to sending the data. One of ordinary skill in the art would have found it obvious to do so, as this would let the first processor know that it is OK to send data to the second processor; Lee also indirectly discloses part of this (see paragraph [0206]), and discloses an acknowledgement signal for subsequent communication steps (see paragraph [0147 - 0148]). Further, ACK are widely used in the art prior to sending data, and doing so would have been a use of a technique known in the art to improve a similar device, with predictable results, which has been determined by the Supreme Court to be obvious (see KSR Int'l Co. v. Teleflex, Inc., 550 U.S. 398 (2007)).
Regarding claim 20, Lee discloses a non-transitory computer-readable storage medium stored with a computer program, wherein the computer program is configured to, when executed by a first processor of an electronic device (memory with code of a device; see paragraph [0204] and Fig. 2), implement a processor communication method on the first processor. and the method comprises:
setting, in response to detecting a downlink packet, a master interrupt interface of the first processor from a second value to a first value to thereby transmit a master interrupt signal to a second processor of the electronic device (CP transmits activation request/user data tx to AP in response to earlier paging message; see paragraphs [0120 – 0129] and Fig. 8; the Examiner notes that paging messages indicate a DL packet; AP can be activated after user data is received; see paragraph [0145]; this signal can be an interrupt; see paragraph [0197]; the Examiner understands the values to be a reflection of the state of having transmitted the interrupts),
transmitting, in response to receiving a first slave acknowledge signal, the downlink packet to the second processor (data is transmitted to AP; see paragraph [0144] and Fig. 8;), wherein the first slave acknowledge signal is returned by the second processor based on the master interrupt signal (CP receives transmit user data response signal from AP based on the first master interrupt signal; see paragraph [0147] and Fig. 8);
restoring the value of the master interrupt interface to be the second value after completion of transmitting the downlink packet (CP transmits activation request/user data tx to AP as a transient signal (i.e. resets to second value); see paragraphs [0120 – 0129] and Fig. 8; wherein the first processor is prohibited from transmitting another master interrupt signal until receiving a second slave acknowledge signal transmitted from the second processor, and the second slave acknowledge signal is returned by the second processor after completion of processing the downlink packet (CP transmits user data response signal to AP following processing of data; see paragraph [0147 - 0148] and Fig. 8; the Examiner understands this to be a first and second slave ack; CP does not transmit another interrupt signal until after the second slave ACK).
Lee does not explicitly disclose transmitting the DL packet based on the slave acknowledge signal.
Hempstead discloses subject matter relating to coprocessors. Specifically, Hempstead discloses:
(when activating the coprocessor with SWITCHON command, first processor expects an ACK from second (slave) processor, which is followed by a data write; see paragraph [0049] and Table 2 and Fig. 3)
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to combine the disclosure of Lee with Hempstead by specifying that the first interrupt signal is ACKed, prior to sending the data. One of ordinary skill in the art would have found it obvious to do so, as this would let the first processor know that it is OK to send data to the second processor; Lee also indirectly discloses part of this (see paragraph [0206]), and discloses an acknowledgement signal for subsequent communication steps (see paragraph [0147 - 0148]). Further, ACK are widely used in the art prior to sending data, and doing so would have been a use of a technique known in the art to improve a similar device, with predictable results, which has been determined by the Supreme Court to be obvious (see KSR Int'l Co. v. Teleflex, Inc., 550 U.S. 398 (2007)).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEPHEN STEINER whose telephone number is (571)272-9825. The examiner can normally be reached M - R 08:00 - 16:00; F 08:00 - 12:00.
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/S.S./ Examiner, Art Unit 2464
/RICKY Q NGO/ Supervisory Patent Examiner, Art Unit 2464
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