DETAILED ACTION
1. Claims 1-20 are pending in the application.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nandi et al (hereafter Nandi)(US Pub. 20160092170) in view of Wei et al (hereafter Wei)(US Pub. 2020/0065065).
Nandi was cited in the IDS filed 08/23/2022
5. As to claim 1, Nandi discloses an apparatus (abstract) comprising:
a carry generation circuit that comprises a first NAND logic circuit configured to receive a first input and a second input and to generate a carry ([0005] and [0027] carry generation circuit and [0028], first NAND logic circuit) and
a carry propagation circuit that comprises a first boolean logic circuit configured to receive the first input, the second input, and a third input and to generate a propagated output ([0017] and [0027] sum generation circuit),
wherein the carry generation circuit and the carry propagation circuit are configured to collectively form a carry output generation circuit ([0027]-[0028] generating output),
wherein the carry output generation circuit comprises a second NAND logic circuit configured to receive the generated carry of the first NAND logic circuit and the propagated output of the first boolean logic circuit and to generate a final carry as an output ([0028] second NAND circuit),
further includes a sum generation circuit that comprises a second boolean logic circuit and an exclusive NOR logic circuit and that is configured to generate a sum output (abstract and fig. 2, exclusive NOR),
wherein the second boolean logic circuit includes the carry generation circuit and is configured to receive the first input, the second input, and the generated carry and to generate an exclusive NOR output ([0035]), and
wherein the exclusive NOR logic circuit is configured to receive the exclusive NOR output and the third input and to generate the sum output (fig. 2 output).
6. Nandi does not explicitly disclose an integrated circuit including a static complementary metal-oxide-semiconductor (CMOS) based Full Adder (FA) circuit.
However, Wei discloses an integrated circuit including a static complementary metal-oxide-semiconductor (CMOS) based Full Adder (FA) circuit ([0028] CMOS Full adder circuit).
7. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Nandi by applying a CMOS based Full Adder circuit, as taught by Wei, for the benefit of reducing calculation delay and increasing speed of the full adder (Wei, [0001] and [0004]).
8. As to claims 2, 4, 10, and 18 the combination of Nandi and Wei discloses wherein the first NAND logic circuit comprises:
a first PMOS transistor whose gate terminal is configured to receive the first input (Nandi [0029] a first PMOS transistor 212 whose gate terminal receives the first input A 202); and a
second PMOS transistor whose gate terminal is configured to receive the second input, wherein a source terminal of each of the first PMOS transistor and the second PMOS transistor is coupled to a power terminal, wherein a drain terminal of each of the first PMOS transistor and the second PMOS transistor is coupled to a node (Nandi [0029] A gate terminal of a second PMOS transistor 214 receives the second input B 204 and a drain terminal of the second PMOS transistor 214 is coupled to the first node X 215. A source terminal of each of the first PMOS transistor 212 and the second PMOS transistor 214 is coupled to a power terminal VDD.),
wherein the first NAND logic circuit further comprises:
a first NMOS transistor whose gate terminal is configured to receive the first input and whose drain terminal is coupled to the node (Nandi [0030]); and
a second NMOS transistor whose gate terminal is configured to receive the second input and whose drain terminal is coupled to a source terminal of the first NMOS transistor, wherein a source terminal of the second NMOS transistor is coupled to a ground terminal, and wherein the first NAND logic circuit is further configured to generate the carry at the node (Nandi [0030] and fig. 2).
9. As to claim 3, 5, and 11, the combination of Nandi and Wei discloses wherein the first boolean logic circuit comprises:
a first PMOS transistor whose gate terminal is configured to receive the third input; and a second PMOS transistor whose gate terminal is configured to receive the first input, wherein a source terminal of each of the first PMOS transistor and the second PMOS transistor is coupled to a power terminal (Nandi [0029] a first PMOS transistor 212 whose gate terminal receives the first input A 202 and whose drain terminal is coupled to a first node X 215. A gate terminal of a second PMOS transistor 214 receives the second input B 204 and a drain terminal of the second PMOS transistor 214 is coupled to the first node X 215. A source terminal of each of the first PMOS transistor 212 and the second PMOS transistor 214 is coupled to a power terminal VDD.),
wherein the first boolean logic circuit further comprises:
a third PMOS transistor whose gate terminal is configured to receive the second input and whose source terminal is coupled to a drain terminal of the second PMOS transistor; and
a first NMOS transistor whose gate terminal is configured to receive the third input, wherein a drain terminal of each of the first PMOS transistor, the third PMOS transistor, and the first NMOS transistor is coupled to a node, wherein the first boolean logic circuit further comprises: a second NMOS transistor whose gate terminal is configured to receive the first input and whose drain terminal is coupled to a source terminal of the first NMOS transistor; and a third NMOS transistor whose gate terminal is configured to receive the second input and whose drain terminal is coupled to the source terminal of the first NMOS transistor, and wherein the first boolean logic circuit is further configured to generate the propagated output at the node (Nandi [0029]-[0032] and fig. 2).
10. As to claims 6 and 12, the combination of Nandi and Wei discloses wherein the exclusive NOR logic circuit comprises:a first PMOS transistor whose gate terminal is configured to receive the exclusive NOR output; and a second PMOS transistor whose gate terminal is configured to receive the third input, wherein a source terminal of each of the first PMOS transistor and the second PMOS transistor is coupled to a power terminal, and wherein the exclusive NOR logic circuit further comprises: a first NMOS transistor whose gate terminal is configured to receive the exclusive NOR output and whose drain terminal is coupled to drain terminals of the first PMOS transistor and the second PMOS transistor to form a node; and a second NMOS transistor whose gate terminal is configured to receive the third input and whose source terminal is coupled to a ground terminal (Nandi fig. 2 exclusive NOR logic circuit 205).
11. As to claims 7, 13, and 19, the combination of Nandi and Wei discloses wherein the exclusive NOR logic circuit further comprises:
a third PMOS transistor whose gate terminal is coupled to the node; and a fourth PMOS transistor whose gate terminal is configured to receive the exclusive NOR output, wherein a source terminal of each of the third PMOS transistor and the fourth PMOS transistor is coupled to the power terminal (Nandi, [0031])),
wherein the exclusive NOR logic circuit further comprises:
a fifth PMOS transistor whose gate terminal is configured to receive the third input and whose source terminal is coupled to a drain terminal of the third PMOS transistor (Nandi [0032], fifth PMOS transistor);
a third NMOS transistor whose gate terminal is coupled to the node and whose drain terminal is coupled to a drain terminal of each of the third PMOS transistor and the fifth PMOS transistor to form another node ([Nandi [0031]);
a fourth NMOS transistor whose gate terminal is configured to receive the exclusive NOR output; and a fifth NMOS transistor whose gate terminal is configured to receive the third input, wherein a source terminal of each of the fourth NMOS transistor and the fifth NMOS transistor is coupled to the ground terminal (Nandi [0033]),
wherein a drain terminal of each of the fourth NMOS transistor and the fifth NMOS transistor is coupled to a source terminal of the third NMOS transistor, and wherein the exclusive NOR logic circuit is further configured to generate the sum output at the other node (Nandi fig 2).
12. As to claim 8, the combination of Nandi and Wei disclose wherein the static CMOS based FA circuit further includes: no more than 6 MOS transistors that are configured to receive the first input; and no more than 6 MOS transistors that are configured to receive the second input (Nandi fig. 2).
13. As to claim 9, Nandi discloses an apparatus (abstract) comprising:
a carry generation circuit that comprises a first NAND logic circuit configured to receive a first input and a second input and to generate a carry ([0005] and [0027] carry generation circuit and [0028], first NAND logic circuit);
a carry propagation circuit that comprises a first boolean logic circuit configured to receive the first input, the second input, and a third input and to generate a propagated output ([0017] and [0027] sum generation circuit); and
a carry output generation circuit that comprises a second NAND logic circuit configured to receive the generated carry of the first NAND logic circuit and the propagated output of the first boolean logic circuit and to generate a final carry as an output, wherein the carry generation circuit and the carry propagation circuit are configured to collectively form the carry output generation circuit ([0027]-[0028] generating output),
further includes a sum generation circuit that comprises a second boolean logic circuit, a first inverter, a third boolean logic circuit, and a second inverter and that is configured to generate a sum output (abstract and fig. 2, exclusive NOR),
wherein the second boolean logic circuit includes the carry generation circuit and is configured to receive the first input, the second input, and the generated carry and to generate an exclusive NOR output ([0035]),
wherein the first inverter is configured to invert the exclusive NOR output of the second boolean logic circuit and to generate an inverted exclusive NOR output ([0027]),
wherein the third boolean logic circuit is configured to receive the exclusive NOR output, the inverted exclusive NOR output, the propagated output, and the third input and to generate the sum output, and wherein the second inverter is configured to invert the generated sum output (fig. 2 output).
14. Nandi does not explicitly disclose an integrated circuit including a static complementary metal-oxide-semiconductor (CMOS) based Full Adder (FA) circuit.
However, Wei discloses an integrated circuit including a static complementary metal-oxide-semiconductor (CMOS) based Full Adder (FA) circuit ([0028] CMOS Full adder circuit).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Nandi by applying a CMOS based Full Adder circuit, as taught by Wei, for the benefit of reducing calculation delay and increasing speed of the full adder (Wei, [0001] and [0004]).
15. As to claim 14, the combination of Nandi and Wei discloses wherein the first inverter comprises: a PMOS transistor whose gate terminal is configured to receive the exclusive NOR output and whose source terminal is coupled to a power terminal; and an NMOS transistor whose gate terminal is configured to receive the exclusive NOR output and whose drain terminal is coupled to a drain terminal of the PMOS transistor to form a node, and wherein the first inverter is configured to generate the inverted exclusive NOR output at the node (Nandi [0046]-[0051] and fig 2).
16. As to claim 15, the combination of Nandi and Wei discloses wherein the third boolean logic circuit comprises: a first PMOS transistor whose gate terminal is configured to receive the third input; and a second PMOS transistor whose gate terminal is configured to receive the exclusive NOR output, wherein a source terminal of each of the first PMOS transistor and the second PMOS transistor is coupled to a power terminal, wherein the third boolean logic circuit further comprises: a third PMOS transistor whose gate terminal is configured to receive the inverted exclusive NOR output and whose source terminal is coupled to a drain terminal of the first PMOS transistor; and a fourth PMOS transistor whose gate terminal is configured to receive the propagated output and whose source terminal is coupled to a drain terminal of the second PMOS transistor, wherein a drain terminal of each of the third PMOS transistor and the fourth PMOS transistor is coupled to a node, and wherein the second inverter comprises a fifth PMOS transistor whose gate terminal is coupled to the node and whose source terminal is coupled to the power terminal (Nandi fig. 2).
17. As to claim 16, the combination of Nandi and Wei discloses wherein the third boolean logic circuit further comprises:a first NMOS transistor whose gate terminal is configured to receive the inverted exclusive NOR output; and a second NMOS transistor whose gate terminal is configured to receive the exclusive NOR output, wherein a drain terminal of each of the first NMOS transistor and the second NMOS transistor is coupled to the drain terminal of each of the third PMOS transistor and the fourth PMOS transistor to form the node, wherein the third boolean logic circuit further comprises:a third NMOS transistor whose gate terminal is configured to receive the propagated output and whose drain terminal is coupled to a source terminal of the first NMOS transistor; and a fourth NMOS transistor whose gate terminal is configured to receive the third input and whose drain terminal is coupled to a source terminal of the second NMOS transistor, wherein the drain terminal of each of the third NMOS transistor and the fourth NMOS transistor is coupled to a ground terminal, wherein the second inverter further comprises a fifth NMOS transistor whose gate terminal is coupled to the node, wherein a drain terminal of the fifth PMOS transistor is coupled with a drain terminal of the fifth NMOS transistor to form another node, wherein a source terminal of the fifth NMOS transistor is coupled to the ground terminal, and wherein the inverted generated sum output is generated at the other node (Nandi [0046]-[0051] and fig 2).
18. As to claim 17, the claim is rejected for similar reasons as to claims 1 and 9 above.
19. As to claim 20, the combination of Nandi and Wei discloses wherein the inverter comprises:a sixth PMOS transistor whose gate terminal is coupled to the second node and whose source terminal is coupled to the power terminal; and a sixth NMOS transistor whose gate terminal is coupled to the second node and whose source terminal is coupled to the ground terminal, wherein a drain terminal of the sixth NMOS transistor is coupled to a drain terminal of the sixth PMOS transistor to form a sum node, and wherein the inverted sum output is generated at the sum node (Nandi fig. 2).
Conclusion
20. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Pat. 4,905,179 – related to integrated circuits, and, more particularly to an elementary C-MOS cell for executing logic addition with fast carry propagation. This adder is the basic element of complex arithmetic logic units.
US Pub. 2021/0124558 – related to adder circuits and more specifically to full adder circuits utilized in compressor circuits.
US Pub. 2022/0236950 – related to a full adder integrated circuit and a 4-2 compressor integrated circuit, and more particularly, to a 4-2 compressor integrated circuit based on a full adder integrated circuit.
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/MICHAEL D. YAARY/Primary Examiner, Art Unit 2151