Prosecution Insights
Last updated: April 18, 2026
Application No. 17/822,173

STACKED FET SUBSTRATE CONTACT

Non-Final OA §102
Filed
Aug 25, 2022
Examiner
CHANG, LEONARD
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
International Business Machines Corporation
OA Round
3 (Non-Final)
56%
Grant Probability
Moderate
3-4
OA Rounds
3y 5m
To Grant
86%
With Interview

Examiner Intelligence

Grants 56% of resolved cases
56%
Career Allow Rate
146 granted / 263 resolved
-12.5% vs TC avg
Strong +31% interview lift
Without
With
+30.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
10 currently pending
Career history
273
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
60.0%
+20.0% vs TC avg
§102
19.8%
-20.2% vs TC avg
§112
16.5%
-23.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 263 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/15/25 has been entered. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-8, and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al. (US PGPub 2019/0189521, hereinafter referred to as “Li”). Li discloses the semiconductor method as claimed. See figures 20 and corresponding text, where Li teaches, in claim 1, a semiconductor device comprising: a shallow trench isolation (STI) region (111) substrate contact located above a substrate (110); (figures 2 and 20; [0041-0043], [0100-0103]) a first epitaxy region (250) located on the substrate and at a bottom of the STI region substrate contact, and connecting the substrate and the substrate contact; and a substrate contact (160) partially filling the STI region and in direct contact with the epitaxy region a second epitaxy region located below and in contact with a source/drain gate contact (figure 20; [0100-0103]) (See examiner’s interpretation below) . . PNG media_image1.png 478 640 media_image1.png Greyscale PNG media_image2.png 261 488 media_image2.png Greyscale PNG media_image3.png 315 401 media_image3.png Greyscale Li teaches, in claim 2, wherein the first epitaxy region is grown on a well implant having a same type as the first epitaxy region ([0102-0103]). Li teaches, in claim 3, wherein the first epitaxy region is selected from the group consisting of an n-type epitaxial region and a p-type epitaxial region ([0102-0103]). Li teaches, in claim 4, further comprising: at least one additional contact, wherein the substrate contact and the at least one additional source/drain gate contact include a same metallic material ([0102-0103]). Li teaches, in claim 5, a stacked field effect transistor (FET) device comprising: a shallow trench isolation (STI) region substrate contact located above a substrate; two types of epitaxy regions, wherein a first one of the two types of epitaxy region is located at a bottom of the STI region substrate contact, and connecting the substrate and the substrate contact; and a first substrate contact partially filling the STI region and in direct contact with the one type of epitaxy region located at the bottom of the STI region a second epitaxy region located below and in contact with a source/drain gate contact, wherein the first epitaxy region and the second epitaxy region are not within a same horizontal plane of the device ([0102-0103]). Li teaches, in claim 6, wherein the one of the two types of first epitaxy region is located on a same type of a well implant ([0102-0103]). Li teaches, in claim 7, wherein the first epitaxy region is selected from a group consisting of an n-type epitaxial region and a p-type epitaxial region ([0102-0103]). Li teaches, in claim 8, further comprising: at least one additional source/drain gate contact, wherein the first substrate contact the source/drain gate contact and the at least one additional source/drain gate contact include a same metallic material ([0102-0103]). Li teaches, in claim 21, further comprising: at least one additional source/drain gate contact, wherein the substrate contact, the source/drain gate contact and the at least one additional source/drain gate contact include a same metallic material ([0102-0103]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 10-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STANETTA D ISAAC/ Examiner, Art Unit 2898 January 7, 2026
Read full office action

Prosecution Timeline

Aug 25, 2022
Application Filed
May 29, 2025
Non-Final Rejection — §102
Jul 31, 2025
Interview Requested
Aug 13, 2025
Applicant Interview (Telephonic)
Aug 13, 2025
Examiner Interview Summary
Aug 27, 2025
Response Filed
Sep 30, 2025
Final Rejection — §102
Nov 02, 2025
Interview Requested
Dec 01, 2025
Response after Non-Final Action
Dec 15, 2025
Request for Continued Examination
Jan 06, 2026
Response after Non-Final Action
Feb 07, 2026
Non-Final Rejection — §102
Mar 08, 2026
Interview Requested
Apr 01, 2026
Response Filed

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604520
MICROELECTRONIC DEVICES INCLUDING VERTICAL INVERTERS, AND ELECTRONIC SYSTEMS
2y 5m to grant Granted Apr 14, 2026
Patent 8980742
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2y 5m to grant Granted Mar 17, 2015
Patent 8962460
NULL
2y 5m to grant Granted Feb 24, 2015
Patent 8946051
NULL
2y 5m to grant Granted Feb 03, 2015
Patent 8922002
PACKAGED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING PACKAGED MICROELECTRONIC DEVICES
2y 5m to grant Granted Dec 30, 2014
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
56%
Grant Probability
86%
With Interview (+30.6%)
3y 5m
Median Time to Grant
High
PTA Risk
Based on 263 resolved cases by this examiner. Grant probability derived from career allow rate.

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