DETAILED ACTION
This action is responsive to: the amendment filed August 15, 2024. Claims 18, 26, and 27 are canceled. Claims 1-17, 19-25, and 28-32 are pending. Claims 1, 8, 14, and 19 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The additional Information Disclosure Statement(s) filed on or before January 22, 2025 have been considered.
Response to Arguments
Applicant's arguments filed August 15, 2024 have been fully considered but they are not persuasive.
Claim 1:
Applicant disputes the Schaefer reference does not disclose the following:
“An error correction code (ECC) circuit configured to receive the first codeword from the first memory die and the second codeword from the second memory die, and further configured to pool the first codeword and the second codeword, and to detect one or more errors in the pooled first and second codeword based, in part, on the first plurality of parity bits and the second plurality of parity bits.”
Applicants’ arguments are not persuasive. Schaefer discloses an ECC Block can retrieve two SEC codewords from the memory array of multiple memory die. Specifically in paragraph 64, the Schaefer reference refers to, “the ECC block 265 may retrieve . . . two (2) 8-bit SEC codewords from the memory array.” Each of Schaefer’s memory die (e.g. Fig. 1: 160-a and 160-b) have the ECC block 265, and the block is connected to the IO, which communicates through channels 115 to the memory controller 105. The rejection of claim 1 is maintained.
Claims 8, 14, and 19:
Applicant argues claims 8, 14, and 19 are similar to claim 1 and therefore the rejection should be withdrawn.
Claims 8, 14, and 19 arguments are similar to claim 1 and therefore are not persuasive. The 102 rejection is maintained. The 102 rejections to claims 1, 8, 14, and 19 are maintained therefore the 102 rejections to the dependent claims 2-7, newly added claims 28-32, as well as 9-13, 15-17, and 20-25 are maintained.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6-7, 8-13, 14-17, 19-24, 31 and 32 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Schaefer et al. (US 20200278908).
Regarding independent claim 1, Schaefer discloses an apparatus (Fig. 1: 100) comprising:
a first memory die (Fig. 1: 160-a; see esp. Fig. 5: the 128-bit array on the left) configured to provide a first codeword (Fig. 2: 205, see para. 64) including a first plurality of data bits (Fig. 5: any of D0-D127 for data pins DQ0-DQ7) and a first plurality of parity bits (Fig. 5: 515-a) as part of a read operation (Fig. 2, see para. 63);
a second memory die (Fig. 1: 160-b, see para. 18 explaining “for ease of description the one or more memory devices may be described as a single memory device”; see esp. Fig. 5: the 128-bit array on the right) configured to provide a second codeword (Fig. 2: 205, see para. 64) including a second plurality of data bits (Fig. 5: D0-D127 for data pins DQ8-DQ15) and a second plurality of parity bits (Fig. 5: 515-c) as part of the read operation (Fig. 2, see para. 63 and 89); and
an error correction code (ECC) circuit (see Fig. 2: 265 for 160-a, as well as 265 for 160-b, but also see 105, see para. 64) configured to receive (Fig. 1: 110, see para. 33) the first codeword (Fig. 2: 205, see para. 64) from the first memory die (Fig. 1: 160-a) and the second codeword (Fig. 2: 205, see para. 64) from the second memory die (Fig. 1: 160-b), and further configured to pool (see para. 64) the first codeword (Fig. 2: 205, see para. 64) and the second codeword (Fig. 2: 205, see para. 64), and detect one or more errors (Fig. 2: 265, see para. 66) in the pooled (see para. 64) first and second codeword based (Fig. 2: 205), in part, on the first plurality of parity bits (Fig. 5: 515-a) and the second plurality of parity bits (Fig. 5: 515-c).
Regarding claim 2, Schaefer discloses the first memory die (Fig. 1: 160-a; see esp. Fig. 5: the 128-bit array on the left) has at least one data terminal (Fig. 5: any of DQ0-DQ7) configured to provide at least some of the first plurality of data bits (Fig. 5: D0-D127) and at least one parity terminal (Fig. 5: 515-a) configured to provide at least some of the first plurality of parity bits (Fig. 5: 515-a, 0-15), and wherein the second memory die (Fig. 1: 160-b, see para. 18; see esp. Fig. 5: the 128-bit array on the right) has at least one data terminal (any of Fig. 5: DQ8-DQ15) configured to provide at least some of the second plurality of data bits (Fig. 5: D0-D127) and at least one parity terminal (Fig. 5: 515-b, 0-15) configured to provide at least some of the second plurality of parity bits (Fig. 5: 515-c).
Regarding claim 3, Schaefer discloses the ECC circuit (see Fig. 2: 265; Fig. 3: 330) is configured to correct the detected one or more errors (Fig. 2: 265, see para. 14, lines 17-24).
Regarding claim 4, Schaefer discloses the first memory die (Fig.1: 160-a; see esp. Fig. 5: the 128-bit array on the left) and the second memory die (Fig. 1: 160-b, see para. 18; see esp. Fig. 5: the 128-bit array on the right) are packaged together on a memory module (Fig. 1: 100), and wherein the ECC circuit (Fig. 3: 330) is part of module logic (Fig. 2: 255, 265) of the module (see para. 18).
Regarding claim 6, Schaefer discloses the ECC circuit (see Fig. 2: 265; Fig. 3: 330) is configured to receive the first plurality of data bits (Fig. 5: D0-D127) of the first codeword (Fig. 2: 205, see para. 64) along a first number of data bus lines (Fig. 1: 140, see para. 83) and provide the first plurality of data bits (Fig. 5: D0-D127) to a second number of external data terminals (Fig. 5: DQ8-DQ15), wherein the first number is larger than the second number (Fig. 5).
Regarding claim 7, Schaefer discloses the first memory die (Fig. 1: 160-a; see esp. Fig. 5: the 128-bit array on the left) is configured to provide the first codeword (Fig. 2: 205, see para. 64) as one or more multi-bit signals (Fig. 1: 110, see para. 48), and wherein the second memory die (Fig. 1: 160-b, see para. 18; see esp. Fig. 5: the 128-bit array on the right) is configured to provide the second codeword (Fig. 2: 205, see para. 64) as one or more multi-bit signals (Fig. 1: 110, see para. 48).
Regarding independent claim 8, Schaefer discloses an apparatus (Fig. 1: 100) comprising:
a plurality of memory dies (Fig. 1: 160, see para. 18; see also, Fig. 5: the 128-bit array on the left and right); and
an error correction code (ECC) circuit (Fig. 2: 265, see para. 69) configured to receive a plurality of codewords (Fig. 2: 205, see para. 69each from a respective one of the plurality of memory dies (Fig. 1: 160, see para. 18),
wherein each of the plurality of codewords (Fig. 2: 205, see para. 69) includes a respective plurality of data bits (Fig. 5: D0-D127 for either or both arrays) and a respective plurality of parity bits (e.g., Fig. 5: 515-a; see also Fig. 5: 515-b, 515-c)), and
wherein the ECC circuit (Fig. 3: 330) is configured to detect errors in the plurality of codewords (Fig. 2: 205, see para. 69) based on ones of the plurality of parity bits (Fig. 5: 515-a) included in at least two of the plurality of codewords (Fig. 2: 205, see para. 69).
Regarding claim 9, Schaefer discloses the plurality of memory dies (Fig. 1: 160, see para. 18) and the ECC circuit (Fig. 3: 330) are packaged on a memory module (Fig. 1: 100).
Regarding claim 10, Schaefer discloses the ECC circuit (Fig. 3: 330) is not located on any of the plurality of memory dies (Fig. 1: 160, see para. 18).
Regarding claim 11, Schaefer discloses the ECC circuit (Fig. 3: 330) is configured to correct the detected errors (see para. 14) in the plurality of codewords (Fig. 2: 205, see para. 69).
Regarding claim 12, Schaefer discloses the ECC circuit (Fig. 3: 330) is configured to correct multi-bit errors (see para. 43) in the plurality of codewords (Fig. 2: 205, see para. 69).
Regarding claim 13, Schaefer discloses the ECC circuit (Fig. 3: 330) is configured to provide the plurality of data bits (Fig. 5: D0-D127) from the plurality of codewords (Fig. 2: 205, see para. 69) to external data terminals (Fig. 5: DQ8-DQ15).
Regarding independent claim 14, Schaefer discloses an apparatus (Fig. 1: 100) comprising:
module logic (Fig. 2: 255, 265) including an error correction code (ECC) circuit (Fig. 3: 330);
a plurality of memory dies (Fig. 1: 160) including a memory array (e.g., Fig. 1: 170; see also, Fig. 5) configured to store a plurality of data bits (Fig. 5: D0-D127) and a plurality of parity bits (Fig. 5: 515-a);
a data bus (Fig. 1: 140; or alternately, Fig. 1: 190) configured to transmit the plurality of data bits (Fig. 5: D0-D127) from the plurality of memory dies (Fig. 1: 160) to the ECC circuit (Fig. 2: 265) as part of a read operation (Fig. 2, see para. 63); and
a parity bus (Fig. 5: 515) configured to transmit the plurality of parity bits (Fig. 5: 515-a) from the plurality of memory dies (Fig. 1: 160) to the ECC circuit (Fig. 3: 330) as part of the read operation (Fig. 2, see para. 63).
Regarding claim 15, Schaefer discloses the plurality of memory dies (Fig. 1: 160; see also, Fig. 5) include a plurality of data terminals (e.g., Fig. 5: DQ0-DQ7) configured to couple the plurality of data bits (Fig. 5: D0-D127) to the data bus (Fig. 1: 140, see para. 83; see also, Fig. 1: 190; see also, Fig. 5: DQ0-DQ15) and at least one parity terminal (Fig. 5: 515a) configured to couple the plurality of parity bits (Fig. 5: 515a, 515-c) to the parity bus (Fig. 5: 515).
Regarding claim 16, Schaefer discloses the data bus (Fig. 1: 140, see para. 83) includes a first number of lines (Fig. 5: data only, which is received on DQ0-DQ15), and wherein the module logic (Fig. 2: 255, 265) is configured to provide the plurality of data bits (Fig. 5: D0-D127) to a second number of external data terminals (Fig. 5: DQ0-DQ15 and the terminals for the parity bits), wherein the second number is different than the first number (data plus parity is a different number than data alone).
Regarding claim 17, Schaefer discloses the plurality of memory dies (Fig.1: 160) are configured to provide the plurality of data bits (Fig. 5: D0-D127) along the data bus (Fig. 1: 140, see para. 83; see also Fig. 1: 190) as a multi-bit signal (Fig. 1: 110, see para. 48), and wherein the module logic (Fig. 2: 255, 265) is configured to provide the plurality of data bits (Fig. 5: D0-D127) as a binary signal (Fig. 2: 215, see para. 58) to external data terminals (Fig. 5: DQ0-DQ15).
Regarding independent claim 19, Schaefer discloses a method (Abstract) comprising:
receiving a first codeword (Fig. 2: 205, see para. 64) from a first memory die (Fig. 1: 160-a; Fig. 5: array on left) and a second codeword (Fig. 2: 205, see para. 64) from a second memory die (Fig. 1: 160-b, see para. 18; Fig. 5: array on right) at an error correction code (ECC) circuit (Fig. 2: 265) as part of a read operation (Fig. 2, see para. 63);
pooling (Fig. 1: 110, see para 33), by the ECC circuit (see Fig. 2: 265), the first codeword and the second codeword (Fig. 2: 265) into a set of data bits (Fig. 5: DQs) and a set of parity bits (Fig. 5: 515); and
detecting errors (Fig. 3: 330) in the set of data bits (Fig. 5: D0-D127) based on the set of error bits (Fig. 2: 265, see para. 66) and the set of parity bits (Fig. 5: 515) with the ECC circuit (Fig. 2: 265).
Regarding claim 20, Schaefer discloses the method of claim 19, further comprising providing the set of data bits (Fig. 5: D0-D127) to external data terminals (Fig. 5: DQ1-DQ7).
Regarding claim 21, Schaefer discloses the method of claim 20, further comprising:
receiving the first codeword (Fig. 2: 205, see para. 64) along a first number of lines of a first data bus (Fig. 1: 140);
receiving the second codeword (Fig. 2: 205, see para. 64) along the first number of lines of a second data bus; and
providing a first plurality of data bits of the first codeword (Fig. 2: 205, see para. 64) to a second number of external data terminals; and
providing a second plurality of data bits of the second codeword (Fig. 2: 205, see para. 64) to the second number of external data terminals (Fig. 5: DQ8-DQ15), wherein the first number is different than the second number (Fig. 5).
Regarding claim 22, Schaefer discloses the method of claim 19, further comprising correcting the detected errors (Fig. 1: 120, see para. 21) in the set of data bits (Fig. 5: D0-D127).
Regarding claim 23, Shaefer discloses the method of claim 19, further comprising receiving the first codeword (Fig. 2: 205, see para. 64) and the second codeword (Fig. 2: 205, see para. 64) as multi-bit signals (Fig. 1: 110, see para. 48).
Regarding claim 24, Schaefer discloses the method of claim 19, further comprising receiving a read command (Fig. 3: 305, see para. 72) at module logic (Fig. 2: 255, 265) and providing the read command to the first memory die (Fig.1: 160-a) and the second memory die (Fig. 1: 160-b, see para. 18) as part of the read command (Fig. 3: 305, see para. 72).
Regarding claim 31, Schaefer discloses wherein the first and second memory dies (Fig. 1: 160-a, 160-b) are included in a channel (Fig. 1: 192) of a plurality of channels (Fig. 1: 115), each channel (Fig. 1: 186, 188, 190, 192) of the plurality of channels (Fig. 1: 115) including multiple memory dies (Fig. 1: 160-a to 160-N, see para. 18; see also, Fig. 5: the 128-bit array on the left and right).
Regarding claim 32, Schaefer discloses wherein the ECC circuit (see Fig. 2: 265; Fig. 3: 330) is configured to use a first portion (Fig. 2: 215, see para. 57) of the pooled (see para. 64) first and second codeword (Fig. 2: 205, see para. 64) comprising the pooled (see para. 64) first and second plurality of parity bits (Fig. 5: 515-a) to implement a first error correction/detection scheme (Fig. 265: 61 & 62) and to use a second portion (Fig. 2: 215, see para. 57) of the pooled first and second codeword (Fig. 2: 205, see para. 64) comprising the pooled first and second plurality of parity bits (Fig. 5: 515-a) to implement a second error correction/detection scheme (Fig. 265: 61 & 62) different from the first error correction/detection scheme (Fig. 265: 61 & 62).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Schaefer et al. (US 20200278908) in view of D’Abreu et al. (US 20130007350).
Regarding claim 5, Schaefer teaches the limitations of claim 4.
Schaefer does not teach:
wherein the module logic further comprises a deserializer circuit configured to deserialize the first codeword and the second codeword, and wherein the ECC circuit is configured to detect errors based on the deserialized first codeword and the deserialized second codeword.
However, D’Abreu teaches:
wherein the module logic (Fig. 3: 342) further comprises a deserializer circuit (Fig. 7: 720) configured to deserialize (Fig. 2: 214) the first codeword (Fig. 1: 152) and the second codeword (see Fig. 1: 152), and wherein the ECC circuit (Fig. 2: 228) is configured to detect errors (Fig. 2 112, see para. 42) based on the deserialized (Fig. 2: 214) first codeword (Fig. 1: 152) and the deserialized (Fig. 2: 214) second codeword (Fig. 1: 152).
It is found that the substituted serializer/deserializer circuit and its functions of deserializing codewords to further enlist the ECC circuit to detect errors based on the deserialized codewords are known in the art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Schaefer’s data matrix, memory controller, and memory system to D’ Abreu’s serializer/deserializer and ECC circuitry for the purpose of converting data from parallel to serial during transmit then converting from serial to parallel once the receiver receives the data. The motivation of the combination is to move data quickly and limit the I/O for efficiency and speed.
Regarding claim 25, Schaefer teaches the limitations of claim 19.
Schaefer does not teach:
further comprising deserializing the first codeword and the deserializing the second codeword at the ECC circuit.
However, D’Abreu teaches:
further comprising deserializing (Fig. 2: 214) the first codeword (Fig. 1: 152) and the deserializing (Fig. 2: 214) the second codeword (Fig. 1: 152) at the ECC circuit (Fig. 2: 228).
It is found that the substituted serializer/deserializer circuit and its functions of deserializing codewords are known in the art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Schaefer’s data matrix, memory controller, and memory system to D’ Abreu’s serializer/deserializer and ECC circuitry for the purpose of converting data from parallel to serial during transmit then converting from serial to parallel once the receiver receives the data. The motivation of the combination is to move data quickly and limit the I/O for efficiency and speed.
Claims 28-30 are rejected under 35 U.S.C. 103 as being unpatentable over Schaefer et al. (US 20200278908) in view of Zhu et al. (US 9183078).
Regarding claim 28, Schaefer teaches the limitations of claim 1.
Schaefer does not teach:
“Wherein values of at least some of the second plurality of parity bits are based at least in part on data bits in the first plurality of data bits.”
However, Zhu teaches:
wherein values of at least some of the second plurality of parity bits (Fig. 3: 308) are based at least in part on data bits (Fig. 3: DXX, representing one block which is one byte, which is 8 data bits) in the first plurality of data bits (Fig. 3: D00).
It is found that the second plurality of parity bits and first plurality of data bits were known in the art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the Schaefer’s apparatus with Zhu’s parity bit and data bit description for the purpose of detecting data errors.
Regarding claim 29, Schaefer teaches the limitations of claim 1.
Schaefer does not teach:
“Wherein values of at least some of the second plurality of parity bits are based on the first plurality of data bits and the second plurality of data bits.”
However, Zhu teaches:
wherein values of at least some of the second plurality of parity bits (Fig. 3: 308) are based on the first plurality of data bits (Fig. 3: D00) and the second plurality of data bits (Fig. 3: D01).”
It is found that the second plurality of parity bits and first plurality of data bits were known in the art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the Schaefer’s apparatus with Zhu’s parity bit and data bit description for the purpose of detecting data errors.
Regarding claim 30, Schaefer teaches the limitations of claim 1.
Schaefer does not teach:
“Wherein values of the second plurality of parity bits are not based on the second plurality of data bits.”
However, Zhu teaches:
Wherein values of the second plurality of parity bits (Fig. 3: 308) are not based on the second plurality of data bits (Fig. 3: D01).
It is found that the second plurality of parity bits and first plurality of data bits were known in the art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the Schaefer’s apparatus with Zhu’s parity bit and data bit description for the purpose of detecting data errors.
Conclusion
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/TRACY HAMPTON/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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