Prosecution Insights
Last updated: October 02, 2026
Application No. 17/826,933

USB TYPE-C SUBSYSTEM

Non-Final OA §102§103
Filed
May 27, 2022
Examiner
UNELUS, ERNEST
Art Unit
2181
Tech Center
2100 — Computer Architecture & Software
Assignee
Intel Corporation
OA Round
3 (Non-Final)
77%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
423 granted / 548 resolved
+22.2% vs TC avg
Strong +39% interview lift
Without
With
+38.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
22 currently pending
Career history
578
Total Applications
across all art units

Statute-Specific Performance

§101
5.5%
-34.5% vs TC avg
§103
41.0%
+1.0% vs TC avg
§102
45.9%
+5.9% vs TC avg
§112
2.5%
-37.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 548 resolved cases

Office Action

§102 §103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . RESPONSE TO AMENDMENT Claim rejections based on prior art A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/18/2026 has been entered. Applicant’s arguments filed on 04/15/2026 with respect to claims 1-5 and 7-20 have been fully considered but are moot in view of newly interpretation of the cited reference based on most recent amendment. OBJECTIONS TO THE CLAIMS Claims 9-16 are objected to as being indefinite for failing to particularly point out and distinctly claim the subject matter which applicant regards as the invention. As per claim 9, line 13, discloses the phrase ‘the Rx. Detect procedure’. There is insufficient antecedent basis for this limitation in the claim. ‘An Rx. Detect procedure’ was not previously disclosed. Correction is needed. REJECTIONS BASED ON PRIOR ART Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 1. Claims 1, 2, 4, 5, 7-11 and 13-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sugumar et al. (US pub. # 2019/0236037), hereinafter, “Sugumar”. At the outset, Applicant is reminded that claims subject to examination will be given their broadest reasonable interpretation in light of the supporting disclosure. In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023,1027-28 (Fed. Cir. 1997). With this in mind, the discussion will focus on how the terms and relationships between the terms in the claims are met by the references. 2. As per claim 1, Sugumar discloses a universal serial bus (USB) host (computing device 201 of fig. 2) comprising: a USB port (USB Type-C interface 236) to couple with a USB device (a USB PD source, as discloses in paragraph 0072) by a USB cable and communicate with the USB device in accordance with a USB protocol (see fig. 2 and paragraphs 0019 and 0022); and a USB host controller (PMIC 204 of fig. 3) communicatively coupled with the USB port by a first data lane (pin CC1) and a second data lane (pin CC2) (see figs. 2 and 3), wherein the USB host controller is to: perform a far-end receiver termination detection (Rx.Detect) (note, ‘a far-end receiver termination detection (Rx.Detect)’ is not a well-known term in the art) procedure on both of the first and second data lanes, using an Rx.Detect circuit (logic block 302 of fig. 3) [see paragraph 0042, which teaches a detection ‘procedure’ by logic block 302, the function called by a ‘Rx.Detect circuit’. For example, paragraph 0042 discloses “a pinout diagram 320 shows the various signals of a USB-C interface (shown with pin numbers A1-A12 and B1-B12 in FIG. 2). The USB-C interface is symmetrical, enabling a USB-C cable connector to be inserted into a USB-C port in one of two orientations (referred to a “right-side up” or “upside down”). The orientation is detected by CC logic block 302 by measuring voltage levels for signals CC1 and CC2 for pins CC1 and CC2. The detection process is initiated in response to insertion of a USB-C cable or device plug, which will result in the VBUS voltage level detected by VBUS detection block 300 and voltage levels for CC1 and CC2 being detected by CC logic block 302” ]; identify that the Rx.Detect procedure was successful on only one of the first and second data lanes (see paragraph 0043, which discloses “once the connector orientation is determined, CC logic block 302 configures one of the CC1 and CC2 signals to be used for serial communication”); identify, based on which of the first and second data lanes the Rx.Detect procedure was successful on, an orientation of a USB cable in the USB port (see paragraph 0042, which discloses “the orientation is detected by CC logic block 302 by measuring voltage levels for signals CC1 and CC2 for pins CC1 and CC2”); identify, based on the orientation, a configuration lane for communication with the USB device via the USB cable in accordance with the USB protocol [see paragraph 0043 and claim 5 of Sugumar, which discloses “5. The method of claim 4, wherein the computing device includes a USB Type-C receptacle having a plurality of pins including CC1 and CC2 pins coupled to the PMIC, the method further comprising: detecting a USB Type-C plug coupled to a USB power source has been inserted into the USB Type-C receptacle; configuring a CC communication channel between the USB power source and the PMIC using one of the CC1 and CC2 pins; and performing a USB power negotiation process under which the USB power source operates as a USB power delivery (PD) source, and the computing device operates as a USB PD sink, wherein during the power negotiation process messages are communicated between a sink policy engine implemented on the processor and the PMIC using the low-pin count link, and messages are communicated between the PMIC and the USB power source using the CC communication channel”], wherein the Rx.Detect procedure is performed without a power delivery (PD) controller or a type-C port controller (TCPC) [see fig. 2, which doesn’t specifically disclose a ‘power delivery (PD) controller’. Note, a negative limitation such as this can be confusing because the performances can be done without a lot of things, close to an infinite number of things. Also, a location of a power delivery (PD) controller or a type-C port controller (TCPC) being part of the host, system is not recited]. 3. As per claim 2, Sugumar discloses “The USB host of claim 1” [See rejection to claim 1 above], wherein the USB host controller is further to: identify, if the Rx.Detect procedure is successful on the first data lane, the first data lane as the configuration lane; and identify, if the Rx.Detect procedure is successful on the second data lane, the second data lane as the configuration lane (see paragraphs 0042 and 0043). 4. As per claims 4 and 13, Sugumar discloses wherein the USB port is a USB Type-C port (see paragraph 0036). 5. As per claims 5 and 14, Sugumar discloses wherein the USB host controller is further communicatively coupled with the USB port by at least two data lanes (see fig. 3). 6. As per claim 7, Sugumar discloses wherein the USB host further includes a first communication channel (CC1) (D+ signal pin, as discloses in paragraph 0044) and a second communication channel (CC2) (D+ signal pin) coupled with the USB port, wherein CC1 and CC2 are different from the first and second data lanes (see figs. 2 and 3). 7. As per claim 8, Sugumar discloses wherein the USB host controller is further to perform the Rx.Detect procedure subsequent to a reset procedure (see paragraph 0020). 8. As per claim 9, Sugumar discloses a universal serial bus (USB) host (computing device 201 of fig. 2) comprising: a USB port (USB Type-C interface 236) to couple with a USB device (a USB PD source, as discloses in paragraph 0072) by a USB cable and communicate with the USB device in accordance with a USB protocol (see fig. 2 and paragraphs 0019 and 0022); and a USB host controller (PMIC 204 of fig. 3) communicatively coupled with the USB port by a first configuration channel (CC1) [first configuration channel (CC1)] and a second communication channel (CC2) [second configuration channel (CC2)], wherein the USB host controller is to: identify, using a voltage comparator module (logic block 302 of fig. 3) [see paragraph 0042 discloses “a pinout diagram 320 shows the various signals of a USB-C interface (shown with pin numbers A1-A12 and B1-B12 in FIG. 2). The USB-C interface is symmetrical, enabling a USB-C cable connector to be inserted into a USB-C port in one of two orientations (referred to a “right-side up” or “upside down”). The orientation is detected by CC logic block 302 by measuring voltage levels for signals CC1 and CC2 for pins CC1 and CC2. The detection process is initiated in response to insertion of a USB-C cable or device plug, which will result in the VBUS voltage level detected by VBUS detection block 300 and voltage levels for CC1 and CC2 being detected by CC logic block 302” ], a voltage change on one of CC1 or CC2 (see paragraphs 0041 and 0042), wherein the voltage change is based on the USB cable being plugged into the USB port (see paragraphs 0041 and 0042); identify, based on which of CC1 and CC2 the voltage change was identified on, an orientation of a USB cable in the USB port (see paragraph 0042); and identify, based on the orientation, a configuration lane (see paragraph 0043, which discloses “once the connector orientation is determined, CC logic block 302 configures one of the CC1 and CC2 signals to be used for serial communication”) for communication with the USB device via the USB cable in accordance with the USB protocol (see paragraphs 0042 and 0043), wherein the Rx.Detect procedure is performed without a power delivery (PD) controller or a type-C port controller (TCPC) [see fig. 2, which doesn’t specifically disclose a ‘power delivery (PD) controller’. Note, a negative limitation such as this can be confusing because the performances can be done without a lot of things, close to an infinite number of things. Also, a location of a power delivery (PD) controller or a type-C port controller (TCPC) being part of the host, system is not recited]. 9. As per claim 10, Sugumar discloses wherein the voltage change is based on a voltage provided by the USB device to the USB cable (see paragraph 0043). 10. As per claim 11, Sugumar discloses wherein the USB host controller is further to identify, based which of CC1 and CC2 the voltage change was identified on, CC1 or CC2 as the configuration lane (see paragraphs 0042 and 0043). 11. As per claim 15, Sugumar discloses wherein: if the voltage change is identified on CC1, the USB host controller is to identify the first data lane as the configuration lane; and if the voltage change is identified on CC2, the USB host controller is to identify the second data lane as the configuration lane (see paragraphs 0041 and 0042). 12. As per claim 16, Sugumar discloses wherein the identification of the voltage change is performed without a power delivery (PD) controller (see fig. 2, which doesn’t specifically disclose a ‘power delivery (PD) controller’) or a type-C port controller (TCPC). 13. As per claim 17, Sugumar discloses a universal serial bus (USB) system (architecture 200 of fig. 2) comprising: a USB port (USB Type-C interface 236) to couple with another electronic device (a USB PD source, as discloses in paragraph 0072) by a USB cable and communicate with the other electronic device in accordance with a USB protocol (see fig. 2 and paragraphs 0019 and 0022); and a USB dual-role controller (PMIC 204 of fig. 3) communicatively coupled with the USB port by a first data lane, a second data lane, a first communication channel (CC), and a second CC (see fig. 3), wherein the USB dual-role controller is to: identify, based on a previously input setting, whether the system is to act in accordance with a USB host functionality or a USB device functionality (see paragraph 0043); alter one or more switches related to a Type-C state machine to enact the USB host functionality or the USB device functionality based on the previously input setting (see paragraph 0039). wherein the Rx.Detect procedure and the identification of the orientation and the configuration lane are performed without a power delivery (PD) controller or a type-C port controller (TCPC) [see fig. 2, which doesn’t specifically disclose a ‘power delivery (PD) controller’. Note, a negative limitation such as this can be confusing because the performances can be done without a lot of things, close to an infinite number of things. Also, a location of a power delivery (PD) controller or a type-C port controller (TCPC) being part of the host, system is not recited]. 14. As per claim 18, Sugumar discloses wherein alteration of the switches changes to which of a device-related resistor and host-related resistor the first CC and the second CC are coupled (see fig. 3). 15. As per claim 19, Sugumar discloses wherein, if the system is to act in accordance with the USB host functionality, the USB dual-role controller is further to: identify, using a voltage comparator module, a voltage change on one of the first CC or the second CC, wherein the voltage change is based on the USB cable being plugged into the USB port; identify, based on which of the first CC and the second CC the voltage change was identified on, an orientation of a USB cable in the USB port; and identify, based on the orientation, a configuration lane for communication with the USB device via the USB cable in accordance with the USB protocol (see paragraphs 0042 and 0043). 16. As per claim 20, Sugumar discloses wherein, if the system is to act in accordance with the USB host functionality, the USB host/device controller is further to: perform a far-end receiver termination detection (Rx.Detect) procedure on both of the first and second data lanes using an Rx.Detect circuit; identify that the Rx.Detect procedure was successful on only one of the first and second data lanes; identify, based on which of the first and second data lanes the Rx.Detect procedure was successful on, an orientation of a USB cable in the USB port; and identify, based on the orientation, a configuration lane for communication with the USB device via the USB cable in accordance with the USB protocol (see paragraphs 0042-0044). Claim Rejections - 35 USC § 103 17. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 18. Claims 3 and 12 are rejected under 35 U.S.C. 103(a) as being unpatentable over Sugumar et al. (US pub. # 2019/0236037), hereinafter, “Sugumar”, in view of Lin et al. (US pub. # 2020/0012614), hereinafter, “Lin”. 19. As per claims 3 and 12, Sugumar discloses “The USB host of claim 1” [See rejection to claim 1 above], but fails to expressly discloses wherein the USB protocol is a USB 3.2 protocol. Lin discloses wherein the USB protocol is a USB 3.2 protocol (see paragraph 0027). It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Lin’s teaching of adjusting a signal transmission direction in a cable that’s configured to be electrically coupled between a first interface port and a second interface port, into Sugumar’s teaching of a Power Management Integrated Circuit (PMIC) of a host device to perform various functions, such as battery management, voltage regulation, and charging functions, for the ability/benefit of having the USB Type-C plug connector and receptacle connector connected bi-directionally, introducing a dual-role capability. CLOSING COMMENTS CONCLUSION a. STATUS OF CLAIMS IN THE APPLICATION The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i): a (1) CLAIMS REJECTED IN THE APPLICATION Per the instant office action, claims 1-5 and 7-20 have received a first action on the merits and are subject of a first action non-final. b. DIRECTION OF FUTURE CORRESPONDENCES Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Ernest Unelus whose telephone number is (571) 272- 8596. The examiner can normally be reached on Monday to Friday 9:00 AM to 5:00 PM. IMPORTANT NOTE If attempts to reach the above noted Examiner by telephone are unsuccessful, the Examiner's supervisor, Mr. Idriss Alrobaye, can be reached at the following telephone number: Area Code (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PMR system, see her//pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217- 91 97 (toll-free). /Ernest Unelus/ Primary Examiner Art Unit 2181
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Prosecution Timeline

Show 3 earlier events
Dec 30, 2025
Response Filed
Feb 24, 2026
Final Rejection mailed — §102, §103
Mar 23, 2026
Applicant Interview (Telephonic)
Mar 23, 2026
Examiner Interview Summary
Apr 15, 2026
Response after Non-Final Action
May 18, 2026
Request for Continued Examination
May 20, 2026
Response after Non-Final Action
Sep 22, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
77%
Grant Probability
99%
With Interview (+38.7%)
3y 1m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 548 resolved cases by this examiner. Grant probability derived from career allowance rate.

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