DETAILED ACTION
This Office Action is in response to communications filed on November 6th, 2025 for Application
No. 17/827,354, in which claims 1, 3-6, 8-10, 12-14, and 16-17 are presented for examination. The amendments filed on November 6th, 2025 have been entered, where claims 1, 3-5, 8-10, 12-13, and 16 are amended and claims 2, 7, 11, and 15 are canceled.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) are:
“artificial intelligence (AI) engine” in Claims 1, 6, 9, 10, 14, and 17.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA
35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure
described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or
pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them
being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting
sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim
limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being
interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Objections
Claims 1, 3-6, 8-10, 12-14, and 16-17 objected to because of the following informalities:
After introducing the shorthand “ML” for “machine learning (ML) model” (Claim 1, ln. 12; Claim 10, ln. 11), it is inconsistently referred to as both “the machine learning model” (Claim 1, ln. 13 and 16-17; Claim 10, ln. 13-14) and “the ML model” (Claim 1, ln. 20; Claim 10, ln. 20), which should be modified to maintain consistency and improve clarity (objection applies equally to dependent claims 3-6, 8-9, 12-14, and 16-17).
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1, 3-6, 8-10, 12-14, and 16-17 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding Claim 1, the claim recites the term “dominant” (ln. 2, 4, 5, 14, 25, 30, 32, and 37), which is a relative term that renders the claim indefinite. The term “dominant” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. As a result, it is not clear which “tunable . . . component[s]” should be considered “tunable dominant components” (see for example ln. 2). As a result, the claim is indefinite. Therefore, it is rejected. The claim should be amended to provide a standard for ascertaining the requisite degree of dominance required by the limitation.
Regarding Claim 3, the claim is rejected because it is dependent on a rejected claim.
Regarding Claims 4-5, the claims recite the term “dominant” (Claim 4, ln. 3 and 6; Claim 5, ln. 2-3), which is indefinite for substantially the same reasoning as articulated in regard to the rejection of Claim 1 above. Therefore, the claims are similarly rejected and should be amended in a similar manner. Additionally, the claims are rejected because they are dependent on a rejected claim.
Regarding Claim 6, the claim is rejected because it is dependent on a rejected claim.
Regarding Claim 8, the claim recites the term “dominant” (ln. 1-2 and 4), which is indefinite for substantially the same reasoning as articulated in regard to the rejection of Claim 1 above. Therefore, the claim is similarly rejected and should be amended in a similar manner. Additionally, the claim is rejected because it is dependent on a rejected claim.
Regarding Claim 9, the claim is rejected because it is dependent on a rejected claim.
Regarding Claims 10 and 12-13, the claims recite the term “dominant” (Claim 10, ln. 3, 5, 6, 15, 24, 29, 31, and 36; Claim 12, ln. 3 and 6; Claim 13, ln. 2-3), which is indefinite for substantially the same reasoning as articulated in regard to the rejection of Claim 1 above. Therefore, the claims are similarly rejected and should be amended in a similar manner. Additionally, the claims are rejected because they are dependent on a rejected claim.
Regarding Claim 14, the claim is rejected because it is dependent on a rejected claim.
Regarding Claim 16, the claim recites the term “dominant” (ln. 1-2 and 4), which is indefinite for substantially the same reasoning as articulated in regard to the rejection of Claim 1 above. Therefore, the claim is similarly rejected and should be amended in a similar manner. Additionally, the claim is rejected because it is dependent on a rejected claim.
Regarding Claim 17, the claim is rejected because it is dependent on a rejected claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-6, 10, and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Andraud et al. (hereinafter Andraud) (“From on-chip self-healing to self-adaptivity in analog/RF ICs: challenges and opportunities”) in view of Kupp et al. (hereinafter Kupp) (“Post-Production Performance Calibration in Analog/RF Devices”) and Carter et al. (hereinafter Carter) (UK Pat. App. Pub. GB-2171546-A).
Regarding Claim 1, Andraud teaches an Integrated Circuit (IC), comprising (Pg. 131 Fig. 1, “ON-CHIP”, where computer chips are integrated circuits; see also Pg. 131, Title, “. . . on-chip . . . analog/RF ICs . . .”, where “IC” stands for integrated circuit):
an analog circuit (Pg. 131, Col. 2, Sect. “SOTA AND TAXONOMY OF ANALOG/RF SELF-HEALING / SELF-ADAPTATION”, Para. 1, “A typical circuit with healing capabilities is illustrated in Fig.1. In this subsection, the term healing is used as a general term, referring to an additional intelligence built to heal/adapt the circuit under consideration (referred as the circuit to heal in Fig.1)”, where “the circuit to heal” is an “ANALOG” circuit and, while “self-healing” is compared with “Self-adaptation” in subsequent sections, see Pg. 132, Col. 1, Sect. “A. Nomenclature used for the taxonomy”, the “circuit to heal in Fig. 1” includes “intelligence built to heal/adapt the circuit” and is therefore a more general taxonomy; see also Pg. 131, Col. 2, Para. 2, “In this subsection, the term healing is used as a general term, referring to an additional intelligence built to heal/adapt the circuit under consideration”; furthermore, where appropriate, teachings taught within the contexts of “self-calibration” or “self-healing”, is generally applicable to provide additional details elements of “self-adaptation” because the functionality of “self-calibration” is subsumed by “self-adaption”, see Pg. 132, Col. 1, Sect. “A. Nomenclature used for the taxonomy” and Pg. 132, Fig. 2, “Compensated variations”)
comprising one or more tunable . . . components . . . wherein each of the one or more tunable . . . components is configured to change its electrical characteristics such that the one or more tunable . . . components are enabled to retune the analog circuit to attain a predefined set of electrical characteristics (Pg. 131, Col. 2, Para. 3, “the circuit to heal is equipped with . . . tuning knobs to adjust circuit’s performances . . . each tuning knob setting . . . [is] appl[ied] in response to measured conditions”, where the “tuning knobs” must be inherently associated with tunable components to function, and where adjusting the “knob setting” changes the electrical characteristics to collectively retune the circuit to a set of electrical characteristics, see Pg. 133, Col. 1, Para. 3, “An on-chip optimizer is then used to find the optimal tuning settings. Results show that power can be significantly reduced, from 2.1 mW to 0.6 mW, with the same performance”; Pg. 131, Col. 2, Para. 3, “tuning knobs to adjust circuit’s performances”, where analog circuit performance is electrical; and Pg. 132, Col. 2, Para. 1, “most SotA rely on an embedded optimizer”;, which are predefined based either in a “look-Up Table” in “Off-chip” or predefined in either a “searchable” list or “optimizer” with predefined mathematical logic in “On-chip”, see Pg. 132, Col. 1, Para. 3, “Off-chip . . . using a Look-Up Table (LUT) . . .The algorithm . . . choos[es] the corresponding tuning knob setting regarding these conditions . . . On-chip . . . without prior model being built . . . Finding the best tuning setting . . . can be done for example using an exhaustive search . . . of possible tuning combinations . . . [or] an embedded optimizer, driven by general optimization constraints and a fitness functions to be measured”; see also Pg. 131, Col. 2, Para. 3, “core self-healing algorithm, which essentially decides each tuning knob setting to apply in response to measured conditions”; Pg. 133, Col. 2, Para. 3, “Challenge 1: maintaining adaptation quality without large area cost. As the number of variations to be considered and the complexity of the systems increase, healing and adaptation algorithms become bigger . . . Simplifying this optimization task is crucial to integrate these adaptation strategies without sacrificing accuracy”; Pg. 134, Col. 1, Para. 3, “Machine-learning techniques can enable a very compact model representation of the mapping between sensors and tuning knobs”, where “a very compact model representation of the mapping between sensors and tuning knobs”, is proposed to “simplify this optimization task”);
a Process, Voltage, Temperature (PVT) monitor comprising a plurality of PVT sensors (Pg. 131, Col. 2, Para. 3, “the circuit to heal is equipped with . . . sensors to monitor all types of considered variations”, where the plural “sensors” demonstrates plurality, the “sensors [are] to monitor” “variations” characteristics, and the considered variations include process “manufacturing variations or defects” otherwise known as “process variations”, voltage “voltage”, and temperature “temperature changes”, see Pg. 131, Col. 1, Para. 2, “variations can be broadly classified in three categories: static, quasi-static, and dynamic. Static variations . . . [are] experienced due to manufacturing variations or defects . . . Dynamic variations affect the circuit with rapidly-varying impact, such as e.g. variations due to temperature changes, voltage variations, operating conditions, etc”; see also Pg. 132, Col. 2, Para. 3, “Most self-healing methodologies developed in the literature are largely focused on process variations”),
each collocated with the analog circuit, a tuning memory, and an artificial intelligence (AI) engine (Pg. 131, Col. 2, Para. 3, “the circuit to heal is equipped with . . . sensors to monitor all types of considered variations” and Pg. 131, Fig. 1, where once “Load settings” occurs, the tuning memory “BUILD MODEL Best tuning Conditions”, AI engine “SELF-HEALING ALGORITHM”, and the analog circuit “CIRCUIT TO HEAL” are all collocated “ON-CHIP” with the “SENSORS”),
wherein the plurality of PVT sensors are configured to provide on- the-fly PVT signal inputs (Pg. 131, Fig. 1, where the “SENSORS” provide “STATIC” measurements of “manufacturing variations or defects”, Pg. 131, Col. 1, Para. 2, “Static variations only affect the circuit once and remain constant. This is e.g. experienced due to manufacturing variations or defects”, which must be in real-time to be combined with “dynamic variations” for “compensating”, see Pg. 132, Col. 1, Para. 2, “Self-adaptation, capable of compensating for static, quasi-static and dynamic variations”; alternatively, the “SENSORS” provide real-time “DYNAMIC” measurements of “operating conditions”, which is also within the broadest reasonable interpretation of process, see Pg. 131, Col. 1, Para. 2, “Dynamic variations affect the circuit with rapidly-varying impact, such as e.g. variations due to . . . operating conditions”; Pg. 131, Fig. 1, where the “SENSORS” provide real-time “DYNAMIC” measurements of “voltage”, see Pg. 131, Col. 1, Para. 2, “Dynamic variations affect the circuit with rapidly-varying impact, such as e.g. variations due to . . . voltage variations”; Pg. 131, Fig. 1, where the “SENSORS” provide real-time “DYNAMIC” measurements of “temperature”, see Pg. 131, Col. 1, Para. 2, “Dynamic variations affect the circuit with rapidly-varying impact, such as e.g. variations due to temperature changes”);
the tuning memory embedded with a machine learning (ML) model of the analog circuit (Pg. 131, Fig. 1, where the “model” is a machine learning model of the analog circuit, which is embedded with a “Best tuning [for] conditions” tuning memory after training is complete, see Pg. 134, Col. 1, Para. 3, “Machine-learning techniques can enable a very compact model representation of the mapping between sensors and tuning knobs”; see generally Pg. 132-133, Col. 2-1, Para. 3-1, “Machine learning techniques are then used to correlate the sensor values to the circuit’s performances, to predict the performances solely based on the sensor measurements” and Pg. 133, Col. 1, Para. 3, “This enables, after training, to predict a figure of merit (FoM) for a low-noise amplifier, representative of a trade-off between its main performances”),
wherein the machine learning model is configured to change the electrical characteristics of only the one or more tunable . . . components of the analog circuit (Pg. 131. Col. 2, Fig. 1; Pg. 131, Col. 2, Para. 3, “the term healing is used as a general term, referring to an additional intelligence built to heal/adapt the circuit under consideration (referred as the circuit to heal in Fig.1). The self-healing framework then aims at compensating for part of, or all the variations experienced by the circuit (i.e. static and/or quasi-static and/or dynamic)”; and Pg. 134, Col. 1, Para. 3, “Machine-learning techniques can enable a very compact model representation of the mapping between sensors and tuning knobs”, where the machine learning model, “MODEL” with “Machine-learning”, is configured to change the characteristics of the one or more tunable components or the “circuit” by “mapping between sensors and tuning knobs”, which as discussed above, are used to change the characteristics of the tunable components and only the tunable components, meaning the components associated with the “tuning knobs” are adjusted to allow for “compensating for part of, or all the variations experienced by the circuit”; see also Pg. 131. Col. 1, Para. 2, “Over the last decade, these different types of variations have increasingly started to impact analog and Radio-Frequency (RF) circuit performance”, where the “circuit” is “analog”; and where adjusting the “knob setting” changes the electrical characteristics to collectively retune the circuit to a set of electrical characteristics, see Pg. 133, Col. 1, Para. 3, “An on-chip optimizer is then used to find the optimal tuning settings. Results show that power can be significantly reduced, from 2.1 mW to 0.6 mW, with the same performance” and Pg. 131, Col. 2, Para. 3, “tuning knobs to adjust circuit’s performances”, where analog circuit performance is electrical; and Pg. 132, Col. 2, Para. 1, “most SotA rely on an embedded optimizer”); and
the AI engine (Pg. 131, Col. 2, Para. 3, “an additional intelligence built to heal/adapt the circuit under consideration (referred as the circuit to heal in Fig.1) . . . To achieve this, the circuit to heal is equipped with several key features . . . a core self-healing algorithm”, where the “core self-healing algorithm”, and associated “CHIP” hardware components the “MODEL” is “Load[ed]” to and the “ALGORITHM” is run on, collectively compose the artificial intelligence engine, see also Pg. 131, Fig. 1)
configured to (i) receive the on-the- fly PVT signal inputs from the plurality of PVT sensors (Pg. 131, Fig. 1, where the “measur[ed] conditions” of the “SENSORS” are transmitted to the “SELF-HEALING ALGORITHM”; see also Pg. 131, Col. 1, Para. 2, “variations can be broadly classified in three categories: static, quasi-static, and dynamic. Static variations . . . [are] experienced due to manufacturing variations or defects . . . Dynamic variations affect the circuit with rapidly-varying impact, such as e.g. variations due to temperature changes, voltage variations, operating conditions, etc” and Pg. 132, Col. 2, Para. 3, “Most self-healing methodologies developed in the literature are largely focused on process variations”, where, as discussed above, the receiving is on the fly when “Dynamic” and the inputs, and therefore the sensors, are P, “manufacturing variations or defects” otherwise known as “process variations”, V “voltage”, T “temperature changes”)
and (ii) retrieve the machine learning model embedded in the tuning memory (Pg. 131, Fig. 1, where an arrow connects the “MODEL” to the “SELF-HEALING ALGORITHM” indicating the “ALGORITHM” is configured to receive the “MODEL”),
wherein the AI engine is configured to: fetch the on-the-fly PVT signal inputs from the plurality of PVT sensors (Pg. 131, Col. 2, Para. 3, “a core self-healing algorithm, which essentially decides each tuning knob setting to apply in response to measured conditions”; Pg. 131, Fig. 1, where the “SELF-HEALING ALGORITHM” receives, as indicated by the arrow, “DYNAMIC” signal inputs from the “SENSORS” as “Measure[d] conditions”, where, as discussed the inputs are PVT inputs and therefore the sensors are PVT sensors, and where receiving is within the broadest reasonable of fetching and the process is on-the-fly because “compensating for . . . dynamic operating conditions”, Pg. 132, Col. 1, Para. 2, requires on-the-fly processes; see generally Pg. 132, Col. 1, Para. 3, “On-chip . . . In this case, the system finds its optimal tuning knob values on the fly as it measures the current conditions”, where, despite being discussed in regard to “on-chip” model, illustrates that “measur[ing] current conditions” is “on the fly”);
compute, using the on-the-fly PVT signal inputs and the ML model, electrical characteristics of the analog circuit under an encountered set of PVT conditions (Pg. 131. Col. 2, Fig. 1; Pg. 131, Col. 2, Para. 3, “the term healing is used as a general term, referring to an additional intelligence built to heal/adapt the circuit under consideration (referred as the circuit to heal in Fig.1). The self-healing framework then aims at compensating for part of, or all the variations experienced by the circuit (i.e. static and/or quasi-static and/or dynamic)”; and Pg. 132-133, Col. 2-1, Para. 3-1, “Machine learning techniques are then used to correlate the sensor values to the circuit’s performances, to predict the performances solely based on the sensor measurements”, where the signal inputs, “sensor values”, and the ML model, “MODEL” with “Machine learning” techniques, are used to compute the characteristic of the circuit, “predict the performances” of the “circuit”, under an encountered set of conditions, “variations experienced by the circuit (i.e. static and/or quasi-static and/or dynamic)”; see also Pg. 133, Col. 1, Para. 3, “An on-chip optimizer is then used to find the optimal tuning settings. Results show that power can be significantly reduced, from 2.1 mW to 0.6 mW, with the same performance”, where the analog circuit characteristics must be electrical characteristics for “power . . . [to] be significantly reduced” and Pg. 131, Col. 2, Para. 3, “tuning knobs to adjust circuit’s performances”, where analog circuit performance is electrical; see also Pg. 131, Col. 1, Para. 2, “variations can be broadly classified in three categories: static, quasi-static, and dynamic. Static variations . . . [are] experienced due to manufacturing variations or defects . . . Dynamic variations affect the circuit with rapidly-varying impact, such as e.g. variations due to temperature changes, voltage variations, operating conditions, etc” and Pg. 132, Col. 2, Para. 3, “Most self-healing methodologies developed in the literature are largely focused on process variations”, where, as discussed above, the receiving is on the fly when “Dynamic” and the inputs, and therefore the sensors and sensed conditions, are P, “manufacturing variations or defects” otherwise known as “process variations”, V “voltage”, T “temperature changes”; see also Pg. 131. Col. 1, Para. 2, “Over the last decade, these different types of variations have increasingly started to impact analog and Radio-Frequency (RF) circuit performance”, where the “circuit” is “analog”)
determine . . . the electrical characteristics under the encountered set of PVT conditions and the predefined set of electrical characteristics (Pg. 132-133, Col. 2-1, Para. 3-1, “Machine learning techniques are then used to correlate the sensor values to the circuit’s performances, to predict the performances solely based on the sensor measurements”, where the characteristics of the circuit are determined through a calculated prediction, “predict the performances” of the “circuit”, under an encountered set of conditions, “variations experienced by the circuit (i.e. static and/or quasi-static and/or dynamic)”; see also Pg. 133, Col. 1, Para. 3, “An on-chip optimizer is then used to find the optimal tuning settings. Results show that power can be significantly reduced, from 2.1 mW to 0.6 mW, with the same performance”, where characteristics of the tunable components and collective whole of the circuit must be electrical characteristics for “power . . . [to] be significantly reduced”, Pg. 131, Col. 2, Para. 3, “tuning knobs to adjust circuit’s performances”, where analog circuit performance is electrical; Pg. 132, Col. 1, Para. 3, “Off-chip . . . using a Look-Up Table (LUT) . . .The algorithm . . . choos[es] the corresponding tuning knob setting regarding these conditions . . . On-chip . . . without prior model being built . . . Finding the best tuning setting . . . can be done for example using an exhaustive search . . . of possible tuning combinations . . . [or] an embedded optimizer, driven by general optimization constraints and a fitness functions to be measured”, where the “model” uses a predefined set of characteristics, which are determined from a “look-Up Table” in “Off-chip” or predefined in either a “searchable” list or “optimizer” with predefined mathematical logic in “On-chip”;);
determine . . . required adjustments to the one or more tunable . . . components that bring the electrical characteristics of the analog circuit to the predefined set of electrical characteristics; generate . . . [tuning] needed to change the electrical characteristics of the one or more tunable . . . components (Pg. 131, Col. 2, Para. 3, “The self-healing framework then aims at compensating for part of, or all the variations experienced by the circuit (i.e. static and/or quasi-static and/or dynamic), in an autonomous manner . . . a core self-healing algorithm, which essentially decides each tuning knob setting to apply in response to measured conditions” and Pg. 132-133, Col. 2-1, Para. 3-1, “Machine learning techniques are then used to correlate the sensor values to the circuit’s performances, to predict the performances solely based on the sensor measurements”, where the required adjustments to the one or more tunable components to adjust the characteristics of the analog circuit are determined and the tuning decisions to change the characteristics of the one or more tunable components are generated, “a core self-healing algorithm, which essentially decides each tuning knob setting to apply in response to measured conditions” to “compensating for part of, or all the variations experienced by the circuit” based on the “the circuit’s . . . predict[ed] the performances”; see also Pg. 133, Col. 1, Para. 3, “An on-chip optimizer is then used to find the optimal tuning settings. Results show that power can be significantly reduced, from 2.1 mW to 0.6 mW, with the same performance”, where characteristics of the tunable components and collective whole of the circuit must be electrical characteristics for “power . . . [to] be significantly reduced”, Pg. 131, Col. 2, Para. 3, “tuning knobs to adjust circuit’s performances”, where analog circuit performance is electrical; see also Pg. 132, Col. 1, Para. 3, “Off-chip . . . using a Look-Up Table (LUT) . . .The algorithm . . . choos[es] the corresponding tuning knob setting regarding these conditions . . . On-chip . . . without prior model being built . . . Finding the best tuning setting . . . can be done for example using an exhaustive search . . . of possible tuning combinations . . . [or] an embedded optimizer, driven by general optimization constraints and a fitness functions to be measured”, where the “model” uses a predefined set of characteristics from a “look-Up Table” in “Off-chip” or predefined in either a “searchable” list or “optimizer” with predefined mathematical logic in “On-chip”);
. . . [tuning knobs] being connected to one of the one or more tunable . . . components of the analog circuit (Pg. 131, Col. 2, Para. 3, “the circuit to heal is equipped with . . . tuning knobs to adjust circuit’s performances . . . each tuning knob setting . . . [is] appl[ied] in response to measured conditions”, where the “tuning knobs” must be inherently associated with tunable components to function);
. . . ; and
retune the analog circuit to attain the predefined set of electrical characteristics by changing the electrical characteristics of the one or more tunable . . . components . . . (Pg. 131, Col. 2, Para. 3, “a core self-healing algorithm, which essentially decides each tuning knob setting to apply in response to measured conditions”; Pg. 132, Fig. 3, where for both “Off-chip” and “On-chip”, a “MODEL” is used to “Tune knobs”, which adjusts the associated tunable components in conformity with the “setting” in order to retune the analog circuit, see Pg. 131, Col. 1, Abstract, “The numerous variations that affect analog and RF circuits are becoming a limiting factor in the design of these circuits in deeply scaled CMOS technologies. An emerging idea to counteract these effects is to let the circuit compensate for these variations itself, referred to as self-healing”; see also Pg. 133, Col. 1, Para. 3, “An on-chip optimizer is then used to find the optimal tuning settings. Results show that power can be significantly reduced, from 2.1 mW to 0.6 mW, with the same performance”, where characteristics of the tunable components and collective whole of the circuit must be electrical characteristics for “power . . . [to] be significantly reduced”, Pg. 131, Col. 2, Para. 3, “tuning knobs to adjust circuit’s performances”, where analog circuit performance is electrical; see also Pg. 132, Col. 1, Para. 3, “Off-chip . . . using a Look-Up Table (LUT) . . .The algorithm . . . choos[es] the corresponding tuning knob setting regarding these conditions . . . On-chip . . . without prior model being built . . . Finding the best tuning setting . . . can be done for example using an exhaustive search . . . of possible tuning combinations . . . [or] an embedded optimizer, driven by general optimization constraints and a fitness functions to be measured”, where the “model” uses a predefined set of characteristics from a “look-Up Table” in “Off-chip” or predefined in either a “searchable” list or “optimizer” with predefined mathematical logic in “On-chip”).
Andraud does not explicitly disclose . . . dominant (subsequent recitations omitted) . . . each configured to respond to a plurality of change control bits . . . deviations between . . . using the deviations . . . from the deviations, a plurality of change control bits . . . store the plurality of change control bits in a change control register, wherein each change control bit . . . apply the plurality of change control bits in parallel through one or more digital switches . . . upon activation of the one or more digital switches (where the control bits, registers, digital switches, and dominance of the tunable components are not taught).
However, Kupp teaches . . . [tunable] dominant [components, where only the tunable dominant components are changed] (Pg. 7, Fig. 7; Pg. 7, Col. 1, Para. 1, “In our device design, we selected three key bias voltages to include as tuning knobs, as these provided maximal control over performances”, where “three key bias voltages”, tunable components, are “include[d] as tuning knobs” based on their dominance, “maximal control over performances”, which allows only these tunable components to be changed)
. . . [determine] deviations between [the electrical characteristics of circuit under encountered conditions and a predefined set of electrical characteristics] . . . (Pg. 3, Col. 1, Fig. 5, where the “Low-Cost Alternate Tests” are used to represent the electric characteristics of the circuit under encountered conditions, see Pg. 1, Col. 2, Para. 2, “the alternate tests are explicitly measured on every device and used in conjunction with the trained regression models to predict performances” and Pg. 7, Col. 2, Para. 3, “On every device in our dataset, we collected four performances: S11, Noise Figure (NF), Gain, and S22. We also collected a power measurement and the four low-cost amplitude sensor (peak detector) alternate test measurement”, and the “Specs” are a predefined set of electrical characteristics, see Pg. 1, Col. 2, Para. 1, “The current industry-standard practice for determining the functional health of analog/RF devices is specification testing . . . each fabricated device under test (DUT) undergoes a series of tests designed to compare a measured set of performances to a corresponding list of specification limit” and Pg. 7, Col. 2, Para. 3, “On every device in our dataset, we collected four performances: S11, Noise Figure (NF), Gain, and S22. We also collected a power measurement and the four low-cost amplitude sensor (peak detector) alternate test measurement”, and where the determination of whether any of the “Predicted Performances” of the “trained regression model” is “Compliant To Specs” represents deviations between the two values)
[determine,] using the deviations [, required adjustments to the one or more tunable dominant components that bring the electrical characteristics of the analog circuit to the predefined set of electrical characteristics] . . . [and generate,] from the deviations [the changes] (Pg. 3, Col. 1, Fig. 8, where the “Yes” path from “Any Compliant To Specs?” , which uses the deviations, determines the required adjustments of the one or more tunable dominant components, “Select Knob Setting”, that brings the electrical characteristics of the analog circuit to the predefined set of electrical characteristics, which are subsequently generated, “Any Compliant To Specs” through “Pass”, see also Pg. 1, Col. 2, Para. 1, “The current industry-standard practice for determining the functional health of analog/RF devices is specification testing . . . each fabricated device under test (DUT) undergoes a series of tests designed to compare a measured set of performances to a corresponding list of specification limit” and Pg. 7, Col. 2, Para. 3, “On every device in our dataset, we collected four performances: S11, Noise Figure (NF), Gain, and S22. We also collected a power measurement and the four low-cost amplitude sensor (peak detector) alternate test measurement”).
Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to combine the integrated circuit, comprising an analog circuit with one or more tunable components, a plurality of PVT sensors, a tuning memory embedded with a machine learning model, and an AI Engine, wherein the AI engine is configured to determine electrical characteristics under an encountered set of PVT conditions and a predefined set of electrical characteristics, determine required adjustments to the one or more tunable components that bring the electrical characteristics of the analog circuit to the predefined set of electrical characteristics; and generate tuning needed to change the electrical characteristics of the one or more tunable components of Andraud with the use of only tunable dominant components in an analog circuit, wherein deviations between the electrical characteristics of circuit under encountered conditions and a predefined set of electrical characteristics are determined and used to determine required adjustments to the one or more tunable dominant components that bring the electrical characteristics of the analog circuit to the predefined set of electrical characteristics and to generate the changes of Kupp in order to restrict the analog circuit component considered for tuning to only the most influential (Kupp, Pg. 7, Col. 1, Para. 1, “In our device design, we selected three key bias voltages to include as tuning knobs, as these provided maximal control over performances”), which will reduce computational complexity of the AI engine operations (see Kupp, Pg. 1, Col. 1, Para. 4, “To date, post-production performance calibration has not achieved widespread use due to the perceived complexity and cost of implementation. This is not an unreasonable perception: knobs have apparently complex interdependent effects on performances, and iterative specification test-tune cycles to explore the large space of knob settings are prohibitively costly”), and to adjust circuit components using a direct comparison between analog circuit characteristics under experienced conditions and industry standards for circuit performance (Kupp, Pg. 1, Col. 1, Abstract, “we develop a detailed cost model permitting direct comparison of performance calibration methods to industry standard specification testing”), which allows highly accurate classifications of self-healing/self-adapting analog circuits and selections of adjustment settings (Kupp, Pg. 10, Col. 1, Para. 4, “This method achieves highly accurate healable/unhealable classification, with a 0.62% test escape rate and a 0.48% yield loss rate, and a 99.2% correct-heal rate using the Mahalanobis distance metric to select a knob setting on the healable devices”) with greatly reduced computational costs (compare Andraud, Pg. 133, Col. 2, Para. 3, “Challenge 1: maintaining adaptation quality without large area cost. As the number of variations to be considered and the complexity of the systems increase, healing and adaptation algorithms become bigger . . . Simplifying this optimization task is crucial to integrate these adaptation strategies without sacrificing accuracy” with Kupp, Pg. 3, Col. 1, Para. 4, “By appropriately modeling the knob- and performance variation axes, we are able to achieve an extreme reduction in the number of alternate tests which must be collected”).
Additionally, Carter teaches . . . [circuit components,] each configured to respond to a plurality of change control bits . . . (Pg. 12, Col. 1, Ln. 18-32, “a structure is described which allows changing the configuration of a finished integrated circuit from time to time . . . This is accomplished by providing a number of "configurable logical elements” . . . which are capable of being electrically interconnected by switches operated in response to control bits”, where the “switches operated in response to control bits” change the electric characteristics of the “circuit” components to conform with the predefined set of logic-based-electrical characteristics, see Pg. 16, Col. 1, Ln. 40-50, “The particular function to be carried out by a configurable logic element is determined by control signals applied to the configurable logic element from control logic. Depending on the control signals, a configurable logic element can function as an AND gate, an OR gate, a NOR gate, a NAND gate, or an exclusive OR gate or any one of a number of other logic functions without change in physical structure. Structure is provided on chip to allow any one of a plurality of functions to be implemented by the configurable logic element”)
[generate, using control signals,] . . . a plurality of change control bits . . . (Pg. 12, Col. 1-2, Ln. 61-68, “In general, a given set of control signals in the form of control bits is transmitted from the control logic to a configurable logic element. The actual set of control bits provided to the configurable logic element on the integrated circuit depends on the function carried out by the configurable logic element on the chip”)
store the plurality of change control bits in a change control register (Pg. 15, Col. 1, Ln. 22-34, “This input signal (shown in Figure 6D) contains bitstream to be stored in the shift register as configuration control bits to configure the configurable logic element to perform a desired logic function or to configure (program) an access junction or a general interconnect junction between general interconnect leads in a manner to be described shortly. Thus the sequence of pulses applied to input lead 58 represents those pulses which when stored in the storage cells of the shift register will activate the configuration control bits in the proper manner to achieve the desired functional and/or interconnection result”, where the “shift register” is within the broadest reasonable definition of a change control register because it is a “register” that stores the changing “control bits”),
wherein each change control bit [is connected to functional components of a circuit] . . . (Pg. 12, Col. 1, Ln. 29-34, “By configurable logic element is meant a combination of devices which are capable of being electrically interconnected by switches operated in response to control bits stored on the chip (or transmitted to the chip) to perform any one of a 95 plurality of logical functions”)
apply the plurality of change control bits in parallel through one or more digital switches (Pg. 16, Col. 2, Ln. 82-86, “each of the switches 102 through 107 may be configured to provide a selected 1 of its two input signals as its output signal. Thus, for example, for one selection of configuration control bits, switch 107 provides signal D”, where the “control bits” are applied through the “switches” that provide “output signal[s]” and where the “switches” are within the broadest reasonable interpretation of digital because they are operated in response to “control bits” and implement digital logic, see Pg. 13, Col. 2, Ln. 17-39, Fig. 1, and where the plurality of change control bits, “control bits”, can be implemented in “parallel”, see Pg. 14, Col. 2, Ln. 124-126, “The configuration control bits can be input into the configurable logic array either in series or in parallel depending upon design considerations”)
. . . [perform an action] upon activation of the one or more digital switches (Pg. 16-17, Col. 2-1, Ln. 82-4, “each of the switches 102 through 107 may be configured to provide a selected 1 of its two input signals as its output signal. Thus, for example, for one selection of configuration control bits, switch 107 provides signal D . . . For another selection of configuration control bits, switch 107 provides feedback signal Q from storage circuit 120 and switches 101 through 103 and 104 through 107 and 113 and 114 are configured as before . . . In general, for any first selection of three of the four variables A, B, C and D/Q, and for any second selection of three of the four variables A, B, C and D/Q . . . implements one of the . . . logic functions”, where, as discussed above, the “switches” are the one or more digital switches, which lead to performance of an action, such as “implement[ing] one of the . . . logic functions”, upon activation, “provid[ing a] signal”).
Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to combine the analog circuit, comprising one or more tunable dominant components and an AI engine configured to determine deviations between the electrical characteristics of an analog circuit under an encountered set of PVT conditions and to generate tuning changes, from the deviations, needed to change the electrical characteristics of one or more tunable dominant components of Andraud in view of Kupp with the circuit components configured to respond to change control bits, wherein the change control bits are connected to functional components of a circuit, stored in a change control register and are applied in parallel through one or more digital switches, wherein an action is performed upon activation of the digital switches of Carter in order to utilize digital logic switches to alter the characteristics of the tunable circuit components, which leads to predictable results (Carter, Pg. 13, Ln. 17-39, where the “function” of each “gate” can be predictably summarized) and has a wide variety of useful functions (Carter, Pg. 13, Col. 1, Ln. 18-21, “Figure 2 illustrates the internal logic structure of one possible configurable logic element capable of implementing a number of useful functions of two variables A and B”), and to store control bits with reduced complexity and reduce semi-conductor area (Carter, Pg. 15, Col. 2, Ln. 121-125, “the dynamic shift register (static latch) can be easily fabricated as part of a configurable logic element without adding significant complexity to the circuit or consuming significant semi- conductor area”), where use of digital logic to control an analog circuit and the use of change control bits to activate switches on circuits were well-established in the art before the effective filing date of the invention (Wilamowski et al., “Digitally Tuned Analog VLSI Controllers”, Pg. 1185, Col. 1, Abstract, “Digitally controlled analog circuits have the following advantages: lower cost, high speed and small signal latency, parallel processing, direct implementation of continuous time designs, and smaller system noise important for a precision control”; Wilamowski et al., Pg. 1187, Col. 1, Para. 2, “The digitally adjusted analog controller concept”; Bhattacharya et al., Pat. No. US 7,057,545 B1, Pg. 6, Col. 1, Ln. 14-21, “Many integrated circuits (ICs) . . . employ resistance compensation circuitry . . .The resistance compensation circuitry generally attempts to minimize an overall variation of resistance as a function of process, supply voltage and/or temperature (PVT) conditions to which the ICs may be subjected”; Bhattacharya et al., Pg. 11, Col. 12, Claim 19, “The integrated circuit of claim 12, wherein the control signals comprise a plurality of digital bits, each bit corresponding to a given one of the switches, the bits forming a digital code word which is indicative of an amount of at least one of process, voltage and temperature variation in the resistor circuit”).
Regarding Claim 4, Andraud in view of Kupp and Carter teach the Integrated Circuit of Claim 1, wherein the ML model is configured to (Andraud, Pg. 131, Fig. 1, “MODEL”)
represent the correlations between the electrical characteristics of the one or more tunable dominant components and the electrical characteristics of the analog circuit (Andraud, Pg. 131, Fig. 1, “BUILD MODEL Best tuning Conditions”, where a trained model represents correlations, through its configuration to transform input data into output data; Andraud, Pg. 133, Col. 2, Para. 2, “An emerging solution recently proposed is the use of self-learning [7]. In this case, the circuit builds its own training data by experimenting when the system is not used, and learns itself the best adaptation settings regarding the experienced conditions. All types of variations are implicitly considered by this technique and the learning can be updated during the whole circuit lifetime”, where the correlations must include correlations between changes in tunable components, which as discussed above in regard to the rejection of claim 1, are tunable dominate components, see Kupp, Pg. 7, Fig. 7; Kupp, Pg. 7, Col. 1, Para. 1, “In our device design, we selected three key bias voltages to include as tuning knobs, as these provided maximal control over performances”, where “three key bias voltages”, tunable components, are “include[d] as tuning knobs” based on their dominance, “maximal control over performances”, which allows only these tunable components to be changed, and changes in the analog circuit to “learns itself the best adaptation settings” from “all variation” of the “circuit”; Andraud, 133, Col. 1, Para. 3, “An on-chip optimizer is then used to find the optimal tuning settings. Results show that power can be significantly reduced, from 2.1 mW to 0.6 mW, with the same performance”, where characteristics of the tunable dominant components and collective whole of the circuit must be electrical characteristics for “power . . . [to] be significantly reduced”; Pg. 131, Col. 2, Para. 3, “tuning knobs to adjust circuit’s performances”, where analog circuit performance is electrical; see also Andraud Pg. 132, Col. 2, Para. 1, “most SotA rely on an embedded optimizer”)
under each encountered set of PVT conditions (Andraud, Pg. 134, Col. 1, Para. 3, “Machine-learning techniques can enable a very compact model representation of the mapping between sensors and tuning knobs”),
to accurately predict the new electrical characteristics of the analog circuit after the changes of the one or more tunable dominant components are applied during the re-tuning process (Andraud, Pg. 131, Col. 2, Para. 3, “the circuit to heal is equipped with . . . tuning knobs to adjust circuit’s performances . . . each tuning knob setting . . . [is] appl[ied] in response to measured conditions”; Andraud, Pg. 133, Col. 2, Para. 2, “An emerging solution recently proposed is the use of self-learning [7]. In this case, the circuit builds its own training data by experimenting when the system is not used, and learns itself the best adaptation settings regarding the experienced conditions. All types of variations are implicitly considered by this technique and the learning can be updated during the whole circuit lifetime”, where the model must accurately predict new characteristics of the analog circuit after re-tuning of the model in order to “learns itself the best adaptation settings regarding the experienced conditions”; Andraud, 133, Col. 1, Para. 3, “An on-chip optimizer is then used to find the optimal tuning settings. Results show that power can be significantly reduced, from 2.1 mW to 0.6 mW, with the same performance”, where the analog circuit characteristics must be electrical characteristics for “power . . . [to] be significantly reduced”; Pg. 131, Col. 2, Para. 3, “tuning knobs to adjust circuit’s performances”, where analog circuit performance is electrical; see also Andraud, Pg. 132, Col. 2, Para. 1, “most SotA rely on an embedded optimizer”).
The reasons for obviousness were discussed in regard to the rejection of claim 1 above and remain applicable here.
Regarding Claim 5, Andraud in view of Kupp and Carter the Integrated Circuit of Claim 1, wherein the ML model is configured to (Andraud, Pg. 131, Fig. 1, “MODEL”)
identify an electrical characteristic value of each tunable dominant component of the one or more tunable dominant components (Andraud, Pg. 134, Col. 1, Para. 3, “Machine-learning techniques can enable a very compact model representation of the mapping between sensors and tuning knobs”, where the “model” identifies characteristic values for the tunable components, which as discussed above in regard to the rejection of claim 1, Kupp, Pg. 7, Fig. 7; Kupp, Pg. 7, Col. 1, Para. 1, “In our device design, we selected three key bias voltages to include as tuning knobs, as these provided maximal control over performances”, where “three key bias voltages”, tunable components, are “include[d] as tuning knobs” based on their dominance, “maximal control over performances”, which allows only these tunable components to be changed, and inherently associated with the “tuning knobs”; Andraud, Pg. 133, Col. 2, Para. 2, “An emerging solution recently proposed is the use of self-learning [7]. In this case, the circuit builds its own training data by experimenting when the system is not used, and learns itself the best adaptation settings regarding the experienced conditions. All types of variations are implicitly considered by this technique and the learning can be updated during the whole circuit lifetime”, where “all types of variations” of “the circuit builds” demonstrates the identified characteristics are for each tunable dominant component; Andraud, 133, Col. 1, Para. 3, “An on-chip optimizer is then used to find the optimal tuning settings. Results show that power can be significantly reduced, from 2.1 mW to 0.6 mW, with the same performance”, where the characteristics must be electrical for “power . . . [to] be significantly reduced”; Pg. 131, Col. 2, Para. 3, “tuning knobs to adjust circuit’s performances”, where analog circuit performance is electrical; see also Andraud Pg. 132, Col. 2, Para. 1, “most SotA rely on an embedded optimizer”)
to re-tune the analog circuit to attain the predefined set of electrical characteristics (Andraud, Pg. 132, Col. 1, Para. 3, “Off-chip . . . using a Look-Up Table (LUT) . . .The algorithm . . . choos[es] the corresponding tuning knob setting regarding these conditions . . . On-chip . . . without prior model being built . . . Finding the best tuning setting . . . can be done for example using an exhaustive search . . . of possible tuning combinations . . . [or] an embedded optimizer, driven by general optimization constraints and a fitness functions to be measured”, where the “model” uses a predefined set of characteristics from a “look-Up Table” in “Off-chip” or predefined in either a “searchable” list or “optimizer” with predefined mathematical logic in “On-chip”; Andraud, Pg. 131, Col. 2, Para. 3, “the circuit to heal is equipped with . . . tuning knobs to adjust circuit’s performances . . . each tuning knob setting . . . [is] appl[ied] in response to measured conditions”, where the “tuning” is to retune the circuit; Andraud, 133, Col. 1, Para. 3, “An on-chip optimizer is then used to find the optimal tuning settings. Results show that power can be significantly reduced, from 2.1 mW to 0.6 mW, with the same performance”, where the predefined set must also be electrical characteristics for “power . . . [to] be significantly reduced”; Pg. 131, Col. 2, Para. 3, “tuning knobs to adjust circuit’s performances”, where analog circuit performance is electrical; see also Andraud Pg. 132, Col. 2, Para. 1, “most SotA rely on an embedded optimizer”).
The reasons for obviousness were discussed in regard to the rejection of claim 1 above and remain applicable here.
Regarding Claim 6, Andraud in view of Kupp and Carter teach the Integrated Circuit of Claim 1, wherein the Al engine is further configured to issue on- the-fly change controls to negate adverse de-tuning effects of real-time PVT variations affecting the analog circuit (Andraud, Pg. 131, Col. 2, Para. 3, “a core self-healing algorithm, which essentially decides each tuning knob setting to apply in response to measured conditions” that occur in real time, where the decisions are on-the-fly because they are based on “measured” PVT signal “conditions” that occur in real-time; Andraud, Pg. 132, Col. 1, Para. 3, “Off-chip . . . using a Look-Up Table (LUT) [which uses a model, see Pg. 132, Fig. 3] . . .The algorithm . . . choos[es] the corresponding tuning knob setting regarding these conditions . . . On-chip . . . without prior model being built . . . Finding the best tuning setting”, where for both “Off-chip” and “On-chip”, a “model” converts inputs into outputs on “the corresponding tuning knob setting regarding these conditions” or the “best tuning setting”, which are designed to negate negative outcomes predicted based on a model inferencing process; and where the “dynamic” nature of the and learning “during the whole circuit lifetime” demonstrates the tuning will include negating adverse effects, de-tuning, of previous real time decisions, see Andraud, Pg. 131, Fig. 1, “VARIATIONS EXPERIENCED . . . DYNAMIC”; Andraud, Pg. 133, Col. 2, Para. 2, “All types of variations are implicitly considered by this technique and the learning can be updated during the whole circuit lifetime”; see also Andraud, Pg. 132, Fig. 3, where the computed decisions on which and how to “tune” the plurality of “knobs” are analog circuit control decisions)
to attain the predefined set of electrical characteristics (Andraud, Pg. 132, Col. 1, Para. 3, “Off-chip . . . using a Look-Up Table (LUT) . . .The algorithm . . . choos[es] the corresponding tuning knob setting regarding these conditions . . . On-chip . . . without prior model being built . . . Finding the best tuning setting . . . can be done for example using an exhaustive search . . . of possible tuning combinations . . . [or] an embedded optimizer, driven by general optimization constraints and a fitness functions to be measured”, where the “model” uses a predefined set of characteristics from a “look-Up Table” in “Off-chip” or predefined in either a “searchable” list or “optimizer” with predefined mathematical logic in “On-chip”; Andraud, Pg. 131, Col. 2, Para. 3, “the circuit to heal is equipped with . . . tuning knobs to adjust circuit’s performances . . . each tuning knob setting . . . [is] appl[ied] in response to measured conditions”, where the “tuning” is to retune the circuit; Andraud, 133, Col. 1, Para. 3, “An on-chip optimizer is then used to find the optimal tuning settings. Results show that power can be significantly reduced, from 2.1 mW to 0.6 mW, with the same performance”, where the predefined set must also be electrical characteristics for “power . . . [to] be significantly reduced”; Pg. 131, Col. 2, Para. 3, “tuning knobs to adjust circuit’s performances”, where analog circuit performance is electrical; see also Andraud Pg. 132, Col. 2, Para. 1, “most SotA rely on an embedded optimizer”).
Regarding Claim 10, Andraud in view of Kupp and Carter teach a method of automatically re-tuning an analog circuit on an Integrated Circuit, the method comprising (Andraud, Pg. 131, Col. 2, Sect. “SOTA AND TAXONOMY OF ANALOG/RF SELF-HEALING / SELF-ADAPTATION”, Para. 1, “A typical circuit with healing capabilities is illustrated in Fig.1. In this subsection, the term healing is used as a general term, referring to an additional intelligence built to heal/adapt the circuit under consideration (referred as the circuit to heal in Fig.1)”, where “the circuit to heal” is an “ANALOG” circuit, contained in a integrated circuit, see Andraud, Pg. 131, Title, “. . . on-chip . . . analog/RF ICs . . .”, where “IC” stands for integrated circuit; where the retuning is automatic, see Andraud, Pg. 131, Col. 2, Para. 3, “The self-healing framework then aims at compensating for part of, or all the variations experienced by the circuit (i.e. static and/or quasi-static and/or dynamic), in an autonomous manner”; and, while “self-healing” is compared with “Self-adaptation” in subsequent sections, see Andraud, Pg. 132, Col. 1, Sect. “A. Nomenclature used for the taxonomy”, the “circuit to heal in Fig. 1” includes “intelligence built to heal/adapt the circuit” and is therefore a more general taxonomy that includes methods for “adapt[ation]”; see also Andraud, Pg. 131, Col. 2, Para. 2, “In this subsection, the term healing is used as a general term, referring to an additional intelligence built to heal/adapt the circuit under consideration”; furthermore, where appropriate, teachings taught within the contexts of “self-calibration” or “self-healing”, is generally applicable to provide additional details elements of “self-adaptation” because the functionality of “self-calibration” is subsumed by “self-adaption”, see Andraud, Pg. 132, Col. 1, Sect. “A. Nomenclature used for the taxonomy” and Andraud, Pg. 132, Fig. 2):
configuring one or more tunable dominant components of the analog circuit to respond to a plurality of change control bits, wherein each of the one or more tunable dominant components is configured to change its electrical characteristics such that the one or more tunable dominant components are enabled to retune the analog circuit to attain a predefined set of electrical characteristics (Andraud, Pg. 131, Col. 2, Para. 3, “the circuit to heal is equipped with . . . tuning knobs to adjust circuit’s performances . . . each tuning knob setting . . . [is] appl[ied] in response to measured conditions”, where the “tuning knobs” must be inherently associated with tunable components to function, and where adjusting the “knob setting” changes the electrical characteristics to collectively retune the circuit to a set of electrical characteristics, see Andraud, 133, Col. 1, Para. 3, “An on-chip optimizer is then used to find the optimal tuning settings. Results show that power can be significantly reduced, from 2.1 mW to 0.6 mW, with the same performance” and Andraud, Pg. 132, Col. 2, Para. 1, “most SotA rely on an embedded optimizer”, which are predefined based either in a “look-Up Table” in “Off-chip” or predefined in either a “searchable” list or “optimizer” with predefined mathematical logic in “On-chip”, see Andraud, Pg. 132, Col. 1, Para. 3, “Off-chip . . . using a Look-Up Table (LUT) . . .The algorithm . . . choos[es] the corresponding tuning knob setting regarding these conditions . . . On-chip . . . without prior model being built . . . Finding the best tuning setting . . . can be done for example using an exhaustive search . . . of possible tuning combinations . . . [or] an embedded optimizer, driven by general optimization constraints and a fitness functions to be measured”; where, in view of Carter, change “control bits” are used to effectuate the “tuning” of circuit electrical characteristics, see Carter, Pg. 12, Col. 1, Ln. 18-32, “a structure is described which allows changing the configuration of a finished integrated circuit from time to time . . . This is accomplished by providing a number of "configurable logical elements” . . . which are capable of being electrically interconnected by switches operated in response to control bits”, see also Carter, Pg. 16, Col. 1, Ln. 40-50, “The particular function to be carried out by a configurable logic element is determined by control signals applied to the configurable logic element from control logic. Depending on the control signals, a configurable logic element can function as an AND gate, an OR gate, a NOR gate, a NAND gate, or an exclusive OR gate or any one of a number of other logic functions without change in physical structure. Structure is provided on chip to allow any one of a plurality of functions to be implemented by the configurable logic element”; see also Kupp, Pg. 7, Col. 1, Para. 1, “In our device design, we selected three key bias voltages to include as tuning knobs, as these provided maximal control over performances”, where “three key bias voltages”, tunable components, are “include[d] as tuning knobs” based on their dominance, “maximal control over performances”, which allows only these tunable components to be changed; see also Kupp, Pg. 7, Col. 2, Para. 3, “On every device in our dataset, we collected four performances: S11, Noise Figure (NF), Gain, and S22. We also collected a power measurement and the four low-cost amplitude sensor (peak detector) alternate test measurement”);
obtaining, by a PVT monitor comprising a plurality of PVT sensors (Andraud, Pg. 131, Col. 2, Para. 3, “the circuit to heal is equipped with . . . sensors to monitor all types of considered variations”, where the plural “sensors” demonstrates plurality, the PVT signal inputs are obtained by “sensors to monitor” “variations” characteristics, and the considered variations include process “manufacturing variations or defects” otherwise known as “process variations”, voltage “voltage”, and temperature “temperature changes”, see Andraud, Pg. 131, Col. 1, Para. 2, “variations can be broadly classified in three categories: static, quasi-static, and dynamic. Static variations . . . [are] experienced due to manufacturing variations or defects . . . Dynamic variations affect the circuit with rapidly-varying impact, such as e.g. variations due to temperature changes, voltage variations, operating conditions, etc”; see generally Andraud, Pg. 132, Col. 2, Para. 3, “Most self-healing methodologies developed in the literature are largely focused on process variations”),
each collocated with the analog circuit, a tuning memory and an artificial intelligence (AI) engine (Andraud, Pg. 131, Col. 2, Para. 3, “the circuit to heal is equipped with . . . sensors to monitor all types of considered variations” and Andraud, Pg. 131, Fig. 1, where once “Load settings” occurs, the tuning memory “BUILD MODEL Best tuning Conditions”, AI engine “SELF-HEALING ALGORITHM”, and the analog circuit “CIRCUIT TO HEAL” are all collocated “ON-CHIP” with the “SENSORS”),
wherein the plurality of PVT sensors are configured to provide on-the-fly PVT signal inputs (Andraud, Pg. 131, Fig. 1, where the “SENSORS” provide “STATIC” measurements of “manufacturing variations or defects”, Andraud, Pg. 131, Col. 1, Para. 2, “Static variations only affect the circuit once and remain constant. This is e.g. experienced due to manufacturing variations or defects”, which must be in real-time to be combined with “dynamic variations” for “compensating”, see Andraud, Pg. 132, Col. 1, Para. 2, “Self-adaptation, capable of compensating for static, quasi-static and dynamic variations”; alternatively, the “SENSORS” provide real-time “DYNAMIC” measurements of “operating conditions”, which is also within the broadest reasonable interpretation of process, see Andraud, Pg. 131, Col. 1, Para. 2, “Dynamic variations affect the circuit with rapidly-varying impact, such as e.g. variations due to . . . operating conditions”; Andraud, Pg. 131, Fig. 1, where the “SENSORS” provide real-time “DYNAMIC” measurements of “voltage”, see Andraud, Pg. 131, Col. 1, Para. 2, “Dynamic variations affect the circuit with rapidly-varying impact, such as e.g. variations due to . . . voltage variations”; Andraud, Pg. 131, Fig. 1, where the “SENSORS” provide real-time “DYNAMIC” measurements of “temperature”, see Andraud, Pg. 131, Col. 1, Para. 2, “Dynamic variations affect the circuit with rapidly-varying impact, such as e.g. variations due to temperature changes”);
reconstituting, by the AI engine, a Machine Learning (ML) model from a tuning model embedded in the tuning memory (Andraud, Pg. 131, Fig. 1, where the “model” is a machine learning model of the analog circuit, which is reconstituted “Load settings”, as effectuated by the AI Engine “SELF-HEALING ALGORITHM”, from embedded tunning memory “Best tuning [for] conditions” after training is complete, see Andraud, Pg. 134, Col. 1, Para. 3, “Machine-learning techniques can enable a very compact model representation of the mapping between sensors and tuning knobs”; see generally Andraud, Pg. 132-133, Col. 2-1, Para. 3-1, “Machine learning techniques are then used to correlate the sensor values to the circuit’s performances, to predict the performances solely based on the sensor measurements” and Andraud, Pg. 133, Col. 1, Para. 3, “This enables, after training, to predict a figure of merit (FoM) for a low-noise amplifier, representative of a trade-off between its main performances”),
wherein the machine learning model is configured to change the electrical characteristics of only the one or more tunable dominant components of the analog circuit (Andraud, Pg. 131. Col. 2, Fig. 1; Andraud, Pg. 131, Col. 2, Para. 3, “the term healing is used as a general term, referring to an additional intelligence built to heal/adapt the circuit under consideration (referred as the circuit to heal in Fig.1). The self-healing framework then aims at compensating for part of, or all the variations experienced by the circuit (i.e. static and/or quasi-static and/or dynamic)”; and Andraud, Pg. 134, Col. 1, Para. 3, “Machine-learning techniques can enable a very compact model representation of the mapping between sensors and tuning knobs”, where the machine learning model, “MODEL” with “Machine-learning”, is configured to change the characteristics of the one or more tunable components or the “circuit” by “mapping between sensors and tuning knobs”, which as discussed above, are used to change the characteristics of the tunable components and only the tunable components, meaning the components associated with the “tuning knobs” are adjusted to allow for “compensating for part of, or all the variations experienced by the circuit”; see also Andraud, Pg. 131. Col. 1, Para. 2, “Over the last decade, these different types of variations have increasingly started to impact analog and Radio-Frequency (RF) circuit performance”, where the “circuit” is “analog”; and where adjusting the “knob setting” changes the electrical characteristics to collectively retune the circuit to a set of electrical characteristics, see Andraud, Pg. 133, Col. 1, Para. 3, “An on-chip optimizer is then used to find the optimal tuning settings. Results show that power can be significantly reduced, from 2.1 mW to 0.6 mW, with the same performance” and Andraud, Pg. 131, Col. 2, Para. 3, “tuning knobs to adjust circuit’s performances”, where analog circuit performance is electrical; and Andraud, Pg. 132, Col. 2, Para. 1, “most SotA rely on an embedded optimizer”; see also Kupp, Pg. 7, Fig. 7; Pg. 7, Col. 1, Para. 1, “In our device design, we selected three key bias voltages to include as tuning knobs, as these provided maximal control over performances”, where “three key bias voltages”, tunable components, are “include[d] as tuning knobs” based on their dominance, “maximal control over performances”, which allows only these tunable components to be changed);
fetching, by the AI engine, the on-the-fly PVT signal inputs from the plurality of PVT sensors (Andraud, Pg. 131, Col. 2, Para. 3, “a core self-healing algorithm, which essentially decides each tuning knob setting to apply in response to measured conditions”; Andraud, Pg. 131, Fig. 1, where the “SELF-HEALING ALGORITHM” receives, as indicated by the arrow, “DYNAMIC” signal inputs from the “SENSORS” as “Measure[d] conditions”, where, as discussed the inputs are PVT inputs and therefore the sensors are PVT sensors, and where receiving is within the broadest reasonable of fetching and the process is on-the-fly because “compensating for . . . dynamic operating conditions”, Andraud, Pg. 132, Col. 1, Para. 2, requires on-the-fly processes; see generally Andraud, Pg. 132, Col. 1, Para. 3, “On-chip . . . In this case, the system finds its optimal tuning knob values on the fly as it measures the current conditions”, where, despite being discussed in regard to “on-chip” model, illustrates that “measur[ing] current conditions” is “on the fly”);
computing, by the AI engine, electrical characteristics of the analog circuit under an encountered set of PVT conditions using the on-the-fly PVT signal inputs and the ML model (Andraud, Pg. 131. Col. 2, Fig. 1; Andraud, Pg. 131, Col. 2, Para. 3, “the term healing is used as a general term, referring to an additional intelligence built to heal/adapt the circuit under consideration (referred as the circuit to heal in Fig.1). The self-healing framework then aims at compensating for part of, or all the variations experienced by the circuit (i.e. static and/or quasi-static and/or dynamic)”; and Andraud, Pg. 132-133, Col. 2-1, Para. 3-1, “Machine learning techniques are then used to correlate the sensor values to the circuit’s performances, to predict the performances solely based on the sensor measurements”, where the signal inputs, “sensor values”, and the ML model, “MODEL” with “Machine learning” techniques, are used to compute the characteristic of the circuit, “predict the performances” of the “circuit”, under an encountered set of conditions, “variations experienced by the circuit (i.e. static and/or quasi-static and/or dynamic)”; see also Andraud, Pg. 133, Col. 1, Para. 3, “An on-chip optimizer is then used to find the optimal tuning settings. Results show that power can be significantly reduced, from 2.1 mW to 0.6 mW, with the same performance”, where the analog circuit characteristics must be electrical characteristics for “power . . . [to] be significantly reduced” and Andraud, Pg. 131, Col. 2, Para. 3, “tuning knobs to adjust circuit’s performances”, where analog circuit performance is electrical; see also Andraud, Pg. 131, Col. 1, Para. 2, “variations can be broadly classified in three categories: static, quasi-static, and dynamic. Static variations . . . [are] experienced due to manufacturing variations or defects . . . Dynamic variations affect the circuit with rapidly-varying impact, such as e.g. variations due to temperature changes, voltage variations, operating conditions, etc” and Andraud, Pg. 132, Col. 2, Para. 3, “Most self-healing methodologies developed in the literature are largely focused on process variations”, where, as discussed above, the receiving is on the fly when “Dynamic” and the inputs, and therefore the sensors and sensed conditions, are P, “manufacturing variations or defects” otherwise known as “process variations”, V “voltage”, T “temperature changes”; see also Andraud, Pg. 131. Col. 1, Para. 2, “Over the last decade, these different types of variations have increasingly started to impact analog and Radio-Frequency (RF) circuit performance”, where the “circuit” is “analog”; see also Kupp, Pg. 7, Col. 2, Para. 3, “On every device in our dataset, we collected four performances: S11, Noise Figure (NF), Gain, and S22. We also collected a power measurement and the four low-cost amplitude sensor (peak detector) alternate test measurement”);
determining deviations between the electrical characteristics under the encountered set of PVT conditions and the predefined set of electrical characteristics (Andraud, Pg. 132-133, Col. 2-1, Para. 3-1, “Machine learning techniques are then used to correlate the sensor values to the circuit’s performances, to predict the performances solely based on the sensor measurements”, where the characteristics of the circuit are determined through a calculated prediction, “predict the performances” of the “circuit”, under an encountered set of conditions, “variations experienced by the circuit (i.e. static and/or quasi-static and/or dynamic)”; see also Andraud, Pg. 133, Col. 1, Para. 3, “An on-chip optimizer is then used to find the optimal tuning settings. Results show that power can be significantly reduced, from 2.1 mW to 0.6 mW, with the same performance”, where characteristics of the tunable components and collective whole of the circuit must be electrical characteristics for “power . . . [to] be significantly reduced”, Andraud, Pg. 131, Col. 2, Para. 3, “tuning knobs to adjust circuit’s performances”, where analog circuit performance is electrical; Andraud, Pg. 132, Col. 1, Para. 3, “Off-chip . . . using a Look-Up Table (LUT) . . .The algorithm . . . choos[es] the corresponding tuning knob setting regarding these conditions . . . On-chip . . . without prior model being built . . . Finding the best tuning setting . . . can be done for example using an exhaustive search . . . of possible tuning combinations . . . [or] an embedded optimizer, driven by general optimization constraints and a fitness functions to be measured”, where the “model” uses a predefined set of characteristics, which are determined from a “look-Up Table” in “Off-chip” or predefined in either a “searchable” list or “optimizer” with predefined mathematical logic in “On-chip”, which, in view of Kupp, are deviations between the two, see Kupp, Pg. 3, Col. 1, Fig. 5, where the “Low-Cost Alternate Tests” are used to represent the electric characteristics of the circuit under encountered conditions, see Kupp, Pg. 1, Col. 2, Para. 2, “the alternate tests are explicitly measured on every device and used in conjunction with the trained regression models to predict performances” and Kupp, Pg. 7, Col. 2, Para. 3, “On every device in our dataset, we collected four performances: S11, Noise Figure (NF), Gain, and S22. We also collected a power measurement and the four low-cost amplitude sensor (peak detector) alternate test measurement”, and the “Specs” are a predefined set of electrical characteristics, see Kupp, Pg. 1, Col. 2, Para. 1, “The current industry-standard practice for determining the functional health of analog/RF devices is specification testing . . . each fabricated device under test (DUT) undergoes a series of tests designed to compare a measured set of performances to a corresponding list of specification limit” and Kupp, Pg. 7, Col. 2, Para. 3, “On every device in our dataset, we collected four performances: S11, Noise Figure (NF), Gain, and S22. We also collected a power measurement and the four low-cost amplitude sensor (peak detector) alternate test measurement”, and where the determination of whether any of the “Predicted Performances” of the “trained regression model” is “Compliant To Specs” represents deviations between the two values);
determining, using the deviations, required adjustments to the one or more tunable dominant components that bring the electrical characteristics of the analog circuit to the predefined set of electrical characteristics; generating, by the AI engine, a plurality of change control bits needed to change the electrical characteristics of the one or more tunable dominant components from the deviations (Andraud, Pg. 131, Col. 2, Para. 3, “The self-healing framework then aims at compensating for part of, or all the variations experienced by the circuit (i.e. static and/or quasi-static and/or dynamic), in an autonomous manner . . . a core self-healing algorithm, which essentially decides each tuning knob setting to apply in response to measured conditions” and Andraud, Pg. 132-133, Col. 2-1, Para. 3-1, “Machine learning techniques are then used to correlate the sensor values to the circuit’s performances, to predict the performances solely based on the sensor measurements”, where the required adjustments to the one or more tunable components to adjust the characteristics of the analog circuit are determined and the tuning decisions to change the characteristics of the one or more tunable components are generated, “a core self-healing algorithm, which essentially decides each tuning knob setting to apply in response to measured conditions” to “compensating for part of, or all the variations experienced by the circuit” based on the “the circuit’s . . . predict[ed] the performances”; see also Andraud, Pg. 133, Col. 1, Para. 3, “An on-chip optimizer is then used to find the optimal tuning settings. Results show that power can be significantly reduced, from 2.1 mW to 0.6 mW, with the same performance”, where characteristics of the tunable components and collective whole of the circuit must be electrical characteristics for “power . . . [to] be significantly reduced”, Andraud, Pg. 131, Col. 2, Para. 3, “tuning knobs to adjust circuit’s performances”, where analog circuit performance is electrical; see also Andraud, Pg. 132, Col. 1, Para. 3, “Off-chip . . . using a Look-Up Table (LUT) . . .The algorithm . . . choos[es] the corresponding tuning knob setting regarding these conditions . . . On-chip . . . without prior model being built . . . Finding the best tuning setting . . . can be done for example using an exhaustive search . . . of possible tuning combinations . . . [or] an embedded optimizer, driven by general optimization constraints and a fitness functions to be measured”, where the “model” uses a predefined set of characteristics from a “look-Up Table” in “Off-chip” or predefined in either a “searchable” list or “optimizer” with predefined mathematical logic in “On-chip”, where, in view of Kupp, the operations are done using the deviations and from the deviations, see Kupp, Pg. 3, Col. 1, Fig. 8, where the “Yes” path from “Any Compliant To Specs?” , which uses the deviations, determines the required adjustments of the one or more tunable dominant components, “Select Knob Setting”, that brings the electrical characteristics of the analog circuit to the predefined set of electrical characteristics, which are subsequently generated, “Any Compliant To Specs” through “Pass”, see also Kupp, Pg. 1, Col. 2, Para. 1, “The current industry-standard practice for determining the functional health of analog/RF devices is specification testing . . . each fabricated device under test (DUT) undergoes a series of tests designed to compare a measured set of performances to a corresponding list of specification limit” and Kupp, Pg. 7, Col. 2, Para. 3, “On every device in our dataset, we collected four performances: S11, Noise Figure (NF), Gain, and S22. We also collected a power measurement and the four low-cost amplitude sensor (peak detector) alternate test measurement” and the tunable components are dominant, see also Kupp, Pg. 7, Col. 1, Para. 1, “In our device design, we selected three key bias voltages to include as tuning knobs, as these provided maximal control over performances”, where “three key bias voltages”, tunable components, are “include[d] as tuning knobs” based on their dominance, “maximal control over performances”, which allows only these tunable components to be changed; see also Kupp, Pg. 7, Col. 2, Para. 3, “On every device in our dataset, we collected four performances: S11, Noise Figure (NF), Gain, and S22. We also collected a power measurement and the four low-cost amplitude sensor (peak detector) alternate test measurement”; and, in view of Carter, the tunning is effectuated with the generated plurality of change control bits, see Carter, Pg. 12, Col. 1-2, Ln. 61-68, “In general, a given set of control signals in the form of control bits is transmitted from the control logic to a configurable logic element. The actual set of control bits provided to the configurable logic element on the integrated circuit depends on the function carried out by the configurable logic element on the chip”);
storing the plurality of change control bits in a change control register (Carter, Pg. 15, Col. 1, Ln. 22-34, “This input signal (shown in Figure 6D) contains bitstream to be stored in the shift register as configuration control bits to configure the configurable logic element to perform a desired logic function or to configure (program) an access junction or a general interconnect junction between general interconnect leads in a manner to be described shortly. Thus the sequence of pulses applied to input lead 58 represents those pulses which when stored in the storage cells of the shift register will activate the configuration control bits in the proper manner to achieve the desired functional and/or interconnection result”, where the “shift register” is within the broadest reasonable definition of a change control register because it is a “register” that stores the changing “control bits”),
wherein each change control bit being connected to one of the one or more tunable dominant components of the analog circuit (Carter, Pg. 12, Col. 1, Ln. 29-34, “By configurable logic element is meant a combination of devices which are capable of being electrically interconnected by switches operated in response to control bits stored on the chip (or transmitted to the chip) to perform any one of a 95 plurality of logical functions”, where the change control bits are connected to functional components, which, in view of Andraud, are the tunable components of the analog circuit, see Andraud, Andraud, Pg. 131, Col. 2, Para. 3, “a core self-healing algorithm, which essentially decides each tuning knob setting to apply in response to measured conditions”; see also Kupp, Pg. 7, Col. 1, Para. 1, “In our device design, we selected three key bias voltages to include as tuning knobs, as these provided maximal control over performances”, where “three key bias voltages”, tunable components, are “include[d] as tuning knobs” based on their dominance, “maximal control over performances”, which allows only these tunable components to be changed);
applying the plurality of change control bits in parallel through one or more digital switches (Carter, Pg. 16, Col. 2, Ln. 82-86, “each of the switches 102 through 107 may be configured to provide a selected 1 of its two input signals as its output signal. Thus, for example, for one selection of configuration control bits, switch 107 provides signal D”, where the “control bits” are applied through the “switches” that provide “output signal[s]” and where the “switches” are within the broadest reasonable interpretation of digital because they are operated in response to “control bits” and implement digital logic, see Carter, Pg. 13, Col. 2, Ln. 17-39, Fig. 1, and where the plurality of change control bits, “control bits”, can be implemented in “parallel”, see Carter, Pg. 14, Col. 2, Ln. 124-126, “The configuration control bits can be input into the configurable logic array either in series or in parallel depending upon design considerations”); and
retuning the analog circuit to attain the predefined set of electrical characteristics by changing the electrical characteristics of the one or more tunable dominant components (Andraud, Pg. 131, Col. 2, Para. 3, “a core self-healing algorithm, which essentially decides each tuning knob setting to apply in response to measured conditions”; Andraud, Pg. 132, Fig. 3, where for both “Off-chip” and “On-chip”, a “MODEL” is used to “Tune knobs”, which adjusts the associated tunable components in conformity with the “setting” in order to retune the analog circuit, see Andraud, Pg. 131, Col. 1, Abstract, “The numerous variations that affect analog and RF circuits are becoming a limiting factor in the design of these circuits in deeply scaled CMOS technologies. An emerging idea to counteract these effects is to let the circuit compensate for these variations itself, referred to as self-healing”; see also Andraud, Pg. 133, Col. 1, Para. 3, “An on-chip optimizer is then used to find the optimal tuning settings. Results show that power can be significantly reduced, from 2.1 mW to 0.6 mW, with the same performance”, where characteristics of the tunable components and collective whole of the circuit must be electrical characteristics for “power . . . [to] be significantly reduced”, Andraud, Pg. 131, Col. 2, Para. 3, “tuning knobs to adjust circuit’s performances”, where analog circuit performance is electrical; see also Andraud, Pg. 132, Col. 1, Para. 3, “Off-chip . . . using a Look-Up Table (LUT) . . .The algorithm . . . choos[es] the corresponding tuning knob setting regarding these conditions . . . On-chip . . . without prior model being built . . . Finding the best tuning setting . . . can be done for example using an exhaustive search . . . of possible tuning combinations . . . [or] an embedded optimizer, driven by general optimization constraints and a fitness functions to be measured”, where the “model” uses a predefined set of characteristics from a “look-Up Table” in “Off-chip” or predefined in either a “searchable” list or “optimizer” with predefined mathematical logic in “On-chip”; see also Kupp, Pg. 7, Col. 1, Para. 1, “In our device design, we selected three key bias voltages to include as tuning knobs, as these provided maximal control over performances”, where “three key bias voltages”, tunable components, are “include[d] as tuning knobs” based on their dominance, “maximal control over performances”, which allows only these tunable components to be changed; see also Kupp, Pg. 7, Col. 2, Para. 3, “On every device in our dataset, we collected four performances: S11, Noise Figure (NF), Gain, and S22. We also collected a power measurement and the four low-cost amplitude sensor (peak detector) alternate test measurement”)
upon activation of the one or more digital switches (Carter, Pg. 16-17, Col. 2-1, Ln. 82-4, “each of the switches 102 through 107 may be configured to provide a selected 1 of its two input signals as its output signal. Thus, for example, for one selection of configuration control bits, switch 107 provides signal D . . . For another selection of configuration control bits, switch 107 provides feedback signal Q from storage circuit 120 and switches 101 through 103 and 104 through 107 and 113 and 114 are configured as before . . . In general, for any first selection of three of the four variables A, B, C and D/Q, and for any second selection of three of the four variables A, B, C and D/Q . . . implements one of the . . . logic functions”, where, as discussed above, the “switches” are the one or more digital switches, which lead to performance of an action, such as “implement[ing] one of the . . . logic functions”, upon activation, “provid[ing a] signal”).
The reasons of obviousness have been noted in the rejection of Claim 1 and remain applicable here.
Regarding Claim 12, the additional elements of the dependent claim are substantially the same as the limitations of Claim 4, therefore it is rejected under the same rationale.
Regarding Claim 13, the additional elements of the dependent claim are substantially the same as the limitations of Claim 5, therefore it is rejected under the same rationale.
Regarding Claim 14, the additional elements of the dependent claim are substantially the same as the limitations of Claim 6, therefore it is rejected under the same rationale.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Andraud in view of Kupp, Carter, and Lourenço et al. (hereinafter Lourenço) (“Using Polynomial Regression and Artificial Neural Networks for Reusable Analog IC Sizing”).
Regarding Claim 3, Andraud in view of Kupp and Carter teach the Integrated Circuit of Claim 1, wherein the tuning model (Andraud, Pg. 131, Fig. 1, “BUILD MODEL Conditions Best tuning”) . . . .
Andraud in view of Kupp and Carter do not explicitly disclose . . . comprises at least one of a polynomial regression model, or an ensembled-regression model (where the tuning model is not specified to be either of these model types).
However, Lourenço teaches [a machine learning technique for analog IC] (Pg. 13, Col. 1, Para. 3-4, “These methods for automatic analog/RF IC sizing . . . using machine learning techniques”)
. . . [where the model] comprises at least one of a polynomial regression model, or an ensembled-regression model (Pg. 13, Abstract, “a multivariate polynomial regression estimates the performance tradeoffs”).
Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to combine the use of a machine learning model for use in analog IC tuning of Andraud in view of Kupp and Carter with the use of a polynomial regression machine learning model for use with analog ICs of Lourenço in order to achieve better model performance with fewer circuit simulations (Lourenço, Pg. 13, Abstract, “The model was able to predict wider and, in some cases, better, performance tradeoff, when compared to independent optimization runs for the same context, despite requiring 400 times fewer circuit simulations”).
Claims 8 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Andraud in view of Kupp, Carter, and Guerra-Gómez et al. (hereinafter Guerra-Gómez) (“Richardson extrapolation-based sensitivity analysis in the multi-objective optimization of analog circuits”).
Regarding Claim 8, Andraud in view of Kupp and Carter teach the Integrated Circuit of Claim 5, wherein each tunable dominant component of the one or more tunable dominant components (Andraud, Pg. 131, Col. 2, Para. 3, “the circuit to heal is equipped with . . . tuning knobs to adjust circuit’s performances . . . each tuning knob setting . . . [is] appl[ied] in response to measured conditions”, where each “knob” of the plurality of “tuning knobs” must be inherently associated with tunable components to function, which as discussed above in regard to the rejection of claim 1, Kupp, Pg. 7, Fig. 7; Kupp, Pg. 7, Col. 1, Para. 1, “In our device design, we selected three key bias voltages to include as tuning knobs, as these provided maximal control over performances”, where “three key bias voltages”, tunable components, are “include[d] as tuning knobs” based on their dominance, “maximal control over performances”, which allows only these tunable components to be changed, and where adjusting the “knob setting” is “applied” to “adjust circuit’s performances”)
is responsive to at least one single binary control in the plurality of change control bits (where, in view of Carter, each aforementioned “knob setting” is responsive to “switches operated in response to control bits”, see Carter, Pg. 12, Col. 1, Ln. 18-32, “a structure is described which allows changing the configuration of a finished integrated circuit from time to time . . . This is accomplished by providing a number of "configurable logical elements” . . . which are capable of being electrically interconnected by switches operated in response to control bits”, which use at least one single binary control, see generally Carter, Pg. 16, Col. 1, Ln. 10-12, “The combinational logic 100 receives the N binary input signals to the configurable logic element”),
where the one or more tunable dominant components are identified in circuit design simulations (Andraud, Pg. 134, Col. 1, Para. 3, “Machine-learning techniques can enable a very compact model representation of the mapping between sensors and tuning knobs”, where the “model” must identify tunable dominant components to map “between sensors and tuning knobs”; Andraud, Pg. 133, Col. 2, Para. 2, “On-chip characterized self-adaptation: . . . An emerging solution recently proposed is the use of self-learning . . . the circuit builds its own training data by experimenting when the system is not used, and learns itself the best adaptation settings regarding the experienced conditions. All types of variations are implicitly considered by this technique and the learning can be updated during the whole circuit lifetime”, where “experimenting when the system is not used” to “learn . . . settings” for the “circuit” are circuit design simulations)
. . . in re-tuning of the analog circuit (Andraud, Pg. 131, Col. 2, Para. 3, “the circuit to heal is equipped with . . . tuning knobs to adjust circuit’s performances . . . each tuning knob setting . . . [is] appl[ied] in response to measured conditions”, where the “adjust[ing]” is re-tuning).
The reasons of obviousness have been noted in the rejection of Claim 1 and remain applicable here.
Andraud in view of Kupp and Carter do not explicitly disclose . . . to be more influential than others . . . .
However, Guerra-Gómez teaches . . . to be more influential than others (Pg. 168, Sect. “3. Multi-parameter sensitivity analysis”, Para. 1, “The relative or normalized sensitivity (S) can be defined as the cause and effect relationship between the circuit elements variations, and the resulting changes in the performances response”, where identifying “relative or normalized sensitivity (S)” of “circuit elements” identifies degree of influence compared to others in “performance response”) . . . .
Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to combine the identifying of tunable dominant components, controlled by binary control bits, based on circuit design simulations for circuit retuning of Andraud in view of Kupp and Carter with the identifying of circuit components that are more influential than others of Guerra-Gómez in order to make determinations about circuit design re-tuning based on relative influence (Guerra-Gómez, Pg. 168, Sect. “3. Multi-parameter sensitivity analysis”, Para. 1, “in the design of analog ICs the lowest sensitivity is very desired”, where “sensitivity” is an important factor in circuit design).
Regarding Claim 16, the additional elements of the dependent claim are substantially the same as the limitations of Claim 8, therefore it is rejected under the same rationale.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Andraud in view of Kupp, Carter, and Chen et al. (hereinafter Chen) (“Fully On-Chip Temperature, Process, and Voltage Sensors”).
Regarding Claim 9, Andraud in view of Kupp and Carter teach the Integrated Circuit of Claim 1, wherein the plurality of PVT sensors comprises (Andraud, Pg. 131, Col. 2, Para. 3, “the circuit to heal is equipped with . . . sensors to monitor all types of considered variations”):
. . . [sensors] collocated with the tuning memory, the Al engine and the analog circuit configured to provide a real-time measurement of device process outcomes (P) (Andraud, Pg. 131, Fig. 1, where once “Load settings” occurs, the tuning memory “BUILD MODEL Best tuning Conditions”, AI engine “SELF-HEALING ALGORITHM”, and the analog circuit “CIRCUIT TO HEAL” are all collocated “ON-CHIP” with the “SENSORS”; where the “SENSORS” provide “STATIC” measurements of “manufacturing variations or defects”, Andraud, Pg. 131, Col. 1, Para. 2, “Static variations only affect the circuit once and remain constant. This is e.g. experienced due to manufacturing variations or defects”, which must be in real-time to be combined with “dynamic variations” for “compensating”, see Andraud, Pg. 132, Col. 1, Para. 2, “Self-adaptation, capable of compensating for static, quasi-static and dynamic variations”; alternatively, the “SENSORS” provide real-time “DYNAMIC” measurements of “operating conditions”, which is also within the broadest reasonable interpretation of process, see Andraud, Pg. 131, Col. 1, Para. 2, “Dynamic variations affect the circuit with rapidly-varying impact, such as e.g. variations due to . . . operating conditions”);
. . . [sensors] collocated with the tuning memory, the Al engine and the analog circuit configured to provide a real-time measurement of operating voltages (V) (Andraud, Pg. 131, Fig. 1, where once “Load settings” occurs, the tuning memory “BUILD MODEL Best tuning Conditions”, AI engine “SELF-HEALING ALGORITHM”, and the analog circuit “CIRCUIT TO HEAL” are all collocated “ON-CHIP” with the “SENSORS”; where the “SENSORS” provide real-time “DYNAMIC” measurements of “voltage”, see Andraud, Pg. 131, Col. 1, Para. 2, “Dynamic variations affect the circuit with rapidly-varying impact, such as e.g. variations due to . . . voltage variations”);
and . . . [sensors] collocated with the tuning memory, the Al engine and the analog circuit configured to provide a real-time measurement of operating temperatures (T) (Andraud, Pg. 131, Fig. 1, where once “Load settings” occurs, the tuning memory “BUILD MODEL Best tuning Conditions”, AI engine “SELF-HEALING ALGORITHM”, and the analog circuit “CIRCUIT TO HEAL” are all collocated “ON-CHIP” with the “SENSORS”; where the “SENSORS” provide real-time “DYNAMIC” measurements of “temperature”, see Pg. 131, Col. 1, Para. 2, “Dynamic variations affect the circuit with rapidly-varying impact, such as e.g. variations due to temperature changes”).
Andraud in view of Kupp and Carter do not explicitly disclose . . . a first sensor . . . a second sensor . . . a third sensor (where the plurality of sensors are discussed as a whole, without mention of specific sensors for each PVT input type).
However, Chen teaches . . . a first sensor . . . a second sensor . . . a third sensor (Pg. 897, Col. 2, Para. 3, “The PVT sensor consists of four major blocks; they are temperature sensor, voltage sensor, voltage reference, and process sensor”).
Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to combine the use of a plurality of sensors, collocated on-chip with the embedded memory, AI engine, and analog circuit, to provide real-time PVT measurements of Andraud in view of Kupp and Carter with the use of a first sensor for process measurements, a second sensor for voltage measurements, and a third sensor for temperature measurements of Chen in order to utilize individualize sensors specifically designed for each measurement and the measurement environment (for example, see Chen, Pg. 898, Col. 1, Para. 3, “The process sensor is proposed with ZTC characteristic in Fig. 2. In UMC 65nm bulk CMOS technology, the ZTC points of NMOS and PMOS are at about 0.4V and 0.6V respectively” and Chen, Pg. 899, Col. 1, Para. 1-2, “a novel ultra-low voltage VTC (ULV2 TC) circuit is proposed to improve accuracy. The proposed ULV2 TC with 0.5V voltage reference is presented in this paper, shows in Fig. 4. It converts input voltage to 5-bit digital code V[4:0]”), which will allow for operation over wide ranges of inputs, with reduced energy consumption, and increased measurement accuracy (Chen, Pg. 897, Abstract, “The proposed wide voltage range low power PVT sensor . . . is capable of operating over a wide voltage range within 0.3V~1V. The power consumption is no more than 3.7μW at 0.3V supply voltage and a high sample rate of 10k samples/sec. The temperature error is merely -0.8~0.8ºC”).
Claims 17 is rejected under 35 U.S.C. 103 as being unpatentable over Andraud in view of Kupp, Carter, Guerra-Gómez, and Chen.
Regarding Claim 17, the additional elements of the dependent claim are substantially the same as the limitations of Claim 9, therefore it is rejected under the same rationale.
Response to Arguments
Applicant's arguments filed on November 6th, 2025 have been fully considered. Each argument is
addressed in detail below.
I. Applicant indicates the objections to the drawings should be withdrawn (Applicant’s Remarks,
11/06/2025, Pg. 12, Section “II. Drawings”).
Applicant’s amendments have overcome each and every objection to the drawings previously set forth in the August 27, 2025 Office Action. As a result, these objections to the drawings have been withdrawn.
II. Applicant indicates the objections to the specification should be withdrawn (Applicant’s Remarks, 11/06/2025, Pg. 12, Section “III. Specification”).
Applicant’s amendments have overcome each and every objection to the specification previously set forth in the August 27, 2025 Office Action. As a result, these objections to the specification have been withdrawn.
III. Applicant argues the decision to interpret the claims as invoking 35 U.S.C. 112(f) should be withdrawn (Applicant’s Remarks, 11/06/2025, Pg. 12-13, Section “III. Claim rejections – 35 U.S.C. 112(f)”).
Specifically, Applicant argues the claims define a hardware-level implementation within an integrated circuit, where an AI engine interacts with an analog circuit, PVT sensors, and a tuning memory embedded with a machine learning model (Pg. 12-13). As a result, Applicant asserts 35 U.S.C. 112(f) should not be invoked because one of ordinary skill in the art would understand the term AI engine to refer to a dedicated hardware or firmware module (Pg. 13). Additionally, Applicant asserts they do not intend to invoke 35 U.S.C. 112(f) and argue the specification includes an explicit description of the structural context and computational function of the AI engine (Pg. 12-13). Specifically, Applicant asserts the specification explicitly defines the AI engine as a CPU-based hardware module with an executable program (Pg. 13).
According to MPEP 2181, “Application of 35 U.S.C. 112(f) is driven by the claim language, not by applicant’s intent or mere statements to the contrary included in the specification or made during prosecution . . . With respect to the third prong of this analysis, the term "means" or "step" or the generic placeholder recited in the claim must not be modified by sufficiently definite structure, material, or acts for achieving the specified function . . . To determine whether a word, term, or phrase coupled with a function denotes structure, examiners may check whether: (1) the specification provides a description sufficient to inform one of ordinary skill in the art that the term denotes structure; (2) general and subject matter specific dictionaries provide evidence that the term has achieved recognition as a noun denoting structure; and/or (3) the prior art provides evidence that the term is an art-recognized structure to perform the claimed function Ex parte Rodriguez, 92 USPQ2d 1395, 1404 (Bd. Pat. App. & Int. 2009) (precedential)”.
Here, the claim language defining a hardware-level implementation within an integrated circuit, where an AI engine interacts with an analog circuit, PVT sensors, and a tuning memory embedded with a machine learning model is insufficient to modify the term AI engine by sufficiently definite structure, material, or acts for achieving the specified function. Additionally, Applicant has not provided dictionary evidence that the term has achieved recognition as a noun denoting structure or prior art evidence that the term is an art-recognized structure to perform the claimed function. furthermore, the stated preference in the specification for an AI engine with a CPU and executable program, does not amount to an explicit definition of the AI engine as a CPU-based hardware module with an executable program. As a result, the specification is not sufficient to inform one or ordinary skill in the art that the term, itself, denotes structure.
Notably, while “AI engine” is being interpreted under 35 U.S.C. 112(f), it is not rejected under 35 U.S.C. 112(b) for failure of the written description to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. As a result, the analysis is driven by the claim language. Therefore, Applicant’s stated intentions not to invoke 35 U.S.C. 112(f) are not relevant to the analysis. Additionally, apart from the narrow context addressed above, Applicant’s specification is superseded by the claim language in this analysis.
As a result, the arguments are not persuasive.
IV. Applicant argues the objections to the claims should be withdrawn (Applicant’s Remarks, 11/06/2025, Pg. 13-14, Section “IV. Claim objections”).
Specifically, Applicant argues the objections to claims 6 and 14, in regard to the use of the term “de-tuning” (Claim 6, Pg. 47, Ln. 21; Claim 14, Pg. 50, Ln. 9), should be withdrawn because the use of the term “de-tuning” was intentional and legally correct. Applicant’s arguments in regard to these objections are persuasive. As a result, these objections have been withdrawn.
Additionally, Applicant indicates the remaining objections to the claims have been overcome by Applicant’s amendments. Applicant’s amendments have overcome the remaining objections to the claims, as previously set forth in the August 27, 2025 Office Action. As a result, these objections to the claims have been withdrawn.
However, as discussed in detail above, Applicant’s amendments create additional minor informalities which necessitate new grounds for objection.
V. Applicant argues the rejections to the claims, under 35 U.S.C. 112(b), should be withdrawn (Applicant’s Remarks, 11/06/2025, Pg. 14, Section “V. Claim Rejections – 35 U.S.C. 112(b)”).
Applicant’s amendments have overcome each and every rejection to the claims, under 35 U.S.C. 112(b), as previously set forth in the August 27, 2025 Office Action. As a result, these rejections to the claims, under 35 U.S.C. 112(b), have been withdrawn.
However, as discussed in detail above, Applicant’s amendments create additional indefiniteness which necessitate new grounds for rejection under 35 U.S.C. 112(b).
VI. Applicant argues the rejections to the claims on the grounds of nonstatutory double patenting should be withdrawn (Applicant’s Remarks, 11/06/2025, Pg. 14-18, Section “DOUBLE PATENTING”).
Specifically, Applicant argues the rejections of the claims 1-2, 4-6, and 10-14 on the grounds of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. US 11,416,664 B2 in view of Bhattacharya should be withdrawn because 1) the claimed subject matter of the instant application is patentably distinct and 2) a terminal disclaimer is filed to overcome the double patenting rejection.
In response to the filing of the terminal disclaimer, which was subsequently approved, the rejections of claims 1-2, 4-6, and 10-14 on the grounds of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. US 11,416,664 B2 in view of Bhattacharya have been withdrawn. As a result, the arguments regarding whether the claimed subject matter is patentably distinct is rendered moot.
Additionally, Applicant argues the provisional rejections of claims 1-2, 4-6, and 10-14 on the grounds of nonstatutory double patenting as being unpatentable over claim 8 of copending Application No. 18/202819 (reference application) in view of Bhattacharya should be withdrawn because an amendment to cancel claim 8 of copending Application No. 18/202819 has been filed.
In response to the filing of an amendment to cancel claim 8 of copending Application No. 18/202819, which was subsequently entered, the provisional rejections of claims 1-2, 4-6, and 10-14 on the grounds of nonstatutory double patenting as being unpatentable over claim 8 of copending Application No. 18/202819 (reference application) in view of Bhattacharya have been withdrawn.
VII. Applicant argues the rejections to the claims, under 35 U.S.C. 103, should be withdrawn (Applicant’s Remarks, 11/06/2025, Pg. 18-42, Section “Claim Rejections – 35 U.S.C. 103”).
In response to Applicant’s amendments, the previously communicated rejections of the claims, under 35 U.S.C. § 103, have been withdrawn. However, Applicant’s arguments are not persuasive in light of the new rejections, under 35 U.S.C. § 103, discussed in detail above. The new grounds of rejection rely on a new combination of prior art in order to teach the new combination of elements in the amended independent claims, which were not presented in this arrangement in any of the previously presented claims
As a result, Applicant’s arguments are rendered moot. However, for clarity of the record and to expedite prosecution, each of Applicant’s arguments are addressed below.
Applicant arguments alleging failures of the prior art of record, as cited in in the August 27, 2025 Office Action, to teach amended claim limitations, which this Office Action relies upon new prior art to teach.
As discussed in detail above, this Office Action relies upon Kupp to teach the amended claim elements of “tunable dominant components” and “deviations . . . using the deviations . . . from the deviations”. As a result, Arguments addressing whether the previous prior art of record, as cited in in the August 27, 2025 Office Action, teach these amended claim elements are rendered moot.
As a result, the arguments are not persuasive.
Applicant arguments alleging failures of the prior art of record to teach limitations not positively recited in the claims.
According to MPEP 2111.01, “II. IT IS IMPROPER TO IMPORT CLAIM LIMITATIONS FROM THE SPECIFICATION Though understanding the claim language may be aided by explanations contained in the written description, it is important not to import into a claim limitations that are not part of the claim” (internal quotation marks omitted) (see also Superguide Corp. v. DirecTV Enterprises, Inc., 358 F.3d 870, 875, 69 USPQ2d 1865, 1868 (Fed. Cir. 2004)).
Here, Applicant argues the prior art of record fails to teach limitations that are not positively recited in the claims. Such as the mitigation of unpredictable PVT variations that detune analog circuits during operation (Pg. 20); the prohibition against and lack of use of dedicated processors or complex on-chip optimizers (Pg. 20-21); the prohibition against off-chip characterization using look-up tables or on-chip characterization using exhaustive searches or embedded optimizers (Pg. 26); use of MOSFETs, resistors, capacitors, or circuit sub-blocks as tunable components (Pg. 26); explicitly defined electrical and functional correlations between tunable components and circuit-level characteristics (Pg. 26); selective adjustment of tunable components (Pg. 27); a specific method for determining values for the tunable components (Pg. 28); and the manner of connection between the control bits and the tunable components, such as the absence of representations of logical states (Pg. 34).
However, these limitations are not read into the claims.
As a result, the arguments are not persuasive.
Applicant arguments alleging failures of Andraud, Carter, Lourenço, Guerra-Gómez, or Chen, to teach limitations, individually, for which a combination of references is relied upon.
According to MPEP 2145, “One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references” (see also In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981)).
Here, Applicant argues that each of Andraud, Carter, Lourenço, Guerra-Gómez, and Chen, in isolation, fail to disclose limitations, individually, of Applicant’s claimed subject matter. Such as the alleged failure of Carter to disclose use of a machine learning model to determine deviations and retune an analog circuit based on actual PVT variations (Pg. 20); the alleged failure of Andraud to teach retuning the analog circuit to a predefined set of electrical characteristics, which, as discussed in detail above, is implicitly required by Andraud, but explicitly recited by the other prior art of record (Pg. 26-27); the alleged failure of Andraud to teach the overall analog circuit behavior, such as change control bits (Pg. 27); the alleged failure of Chen to teach using the AI Engine to determine required adjustments to the tunable components or generate change control bits for changing the electrical characteristics of the tunable components (Pg. 28); the alleged failure of Andraud to teach the entirety of the operations performed by the AI engine (Pg. 32-33); the alleged failure of Carter to teach a machine learning model to determine the required adjustments to the tunable components in order to alter analog electrical characteristics to achieve analog circuit retuning (Pg. 34); the alleged failure of Carter to teach tunable components whose electrical characteristics influence the overall analog circuit under varying PVT conditions of tunable components upon activation of one or more digital switches (Pg. 34); the alleged failure of Andraud to teach the hardware-integrated implementation in its entirety (Pg. 34); the alleged failure of Carter to teach the hardware-integrated implementation in its entirety (Pg. 34); the alleged failure of Carter to teach the connection between a change control register that stores change control bits and one or more tunable components (Pg. 36); the alleged failure of Andraud to teach change control bits, change control registers, or digital switches (Pg. 36); the alleged failure of Carter to teach changing physical characteristics (Pg. 36-37); the alleged failure of Andraud to teach digital switches that could be used by the AI engine to apply the change control bits to the tunable components to change their electrical characteristics (Pg. 37); the alleged failure of Lourenço to teach collocated PVT sensors, an AI engine, or a tuning memory (Pg. 38); and the alleged failure of Guerra-Gómez to teach the retuning of analog circuits or the mechanism for changing the electrical characteristics of tunable components (Pg. 39).
However, the teaching of these limitations, in both the August 27, 2025 Office Action and this Office Action, rely on a combination of references.
As a result, the arguments are not persuasive.
Applicant arguments augments against individual references, where the individual reference is relied upon to entirely teach the limitation at issue.
According to MPEP 2111, “During patent examination, the pending claims must be given their broadest reasonable interpretation consistent with the specification” (internal quotation marks omitted) (see also Phillips v. AWH Corp., 415 F.3d 1303, 1316, 75 USPQ2d 1321, 1329 (Fed. Cir. 2005)).
Additionally, according to MPEP 2111.01, “Under a broadest reasonable interpretation (BRI), words of the claim must be given their plain meaning, unless such meaning is inconsistent with the specification. The plain meaning of a term means the ordinary and customary meaning given to the term by those of ordinary skill in the art at the relevant time. The ordinary and customary meaning of a term may be evidenced by a variety of sources, including the words of the claims themselves, the specification, drawings, and prior art”).
Furthermore, according to 37 C.F.R. 1.111, “The reply by the applicant or patent owner must be reduced to a writing which distinctly and specifically points out the supposed errors in the examiner’s action”.
Here, Applicant argues Andraud fails to teach “a plurality of PVT sensors, each collocated with the analog circuit, a tuning memory, and an artificial intelligence (AI) engine, wherein the plurality of PVT sensors are configured to provide on- the-fly PVT signal inputs” (Claim 1) because it allegedly discloses sensors to monitor all types of considered variations without specifically identifying the sensors as PVT sensors; it allegedly does not specifically identify the sensors as integrated within the IC and collocated with the tuning memory, AI engine, and the analog circuit; finding tuning knobs on the fly are allegedly discussed theoretically and without specific implementation details of how this is achieved; and the self-healing algorithm is allegedly a high level interpretation that essentially decides each tuning knob setting to apply in response to measured conditions, which is incompatible with Applicant’s claimed invention (Pg. 27-29).
However, as discussed in detail above, the recitation of sensors, which monitor process, voltage, and temperature variations is within the broadest reasonable interpretation of PVT sensors. Additionally, Andraud (Pg. 131, Col. 1, Fig. 1) discloses the sensors, AI engine, and analog circuit as on-chip components of the integrated circuit, which is within the broadest reasonable interpretation of collocated. While Applicant asserts that the disclosure of these components on chip is insufficient to teach collocated, Applicant provides no justifications for why this assertion is justified or any supposed errors with the previous Office Action’s characterization of these components. Furthermore, as discussed in detail above, the teaching of “finding tuning values on the fly” is fully consistent with the words of the claim, as given their plain meaning. Finally, Applicant does not specifically point out any supposed errors that would preclude the self-healing algorithm of Andraud, regardless of its level of interpretation, from fully disclosing the limitations of Applicant’s invention that it is relied upon to teach.
As a result, the argument is not persuasive.
Additionally, Applicant argues Andraud fails to teach a machine learning model embedded with the tuning memory for use by the AI engine to determine the required adjustments to alter the electrical characteristics of the tunable components because it allegedly describes the use of optimizers or mathematical algorithms for determining knob settings on a conceptual level without use for on on-the-fly PVT signal inputs (Pg. 31-32).
As discussed in detail above, the disclosure of Andraud, which describes a machine learning model embedded with the best tunning for various conditions that is used by an AI engine to evaluate dynamic PVT conditions to alter the electric characteristics of the tunable components and the analog circuit as a whole is within the broadest reasonable interpretation of teach a machine learning model embedded with the tuning memory for use by the AI engine to determine the required adjustments to alter the electrical characteristics of the tunable components. Additionally, Applicant fails to specifically point out any supposed errors with this analysis or to sufficiently explain why the conceptual level of Andraud precludes this teaching.
As a result, the argument is not persuasive.
Furthermore, Applicant argues Lourenço fails to disclose an ensemble regression model. However, claim 3 recites “at least one of a polynomial regression model, or an ensemble-regression model”. The plain meaning of “at least one of a . . . or” is a requirement of a minimum of one of the two options. Therefore, the disclosure of a polynomial regression model by Lourenço is sufficient.
As a result, the argument is not persuasive.
Applicant arguments alleging failures of the combination of prior art of record, as relied upon in both the August 27, 2025 Office Action and this Office Action.
According to MPEP 2143.01, “If a proposed modification would render the prior art invention being modified unsatisfactory for its intended purpose, there may be no suggestion or motivation to make the proposed modification” . . . [wherein, relevant evidence against this finding is a showing that] Nothing in the prior art teaches that the proposed modification would have resulted in an ‘inoperable’ process”.
Additionally, according to MPEP 2143.01, “If the proposed modification or combination of the prior art would change the principle of operation of the prior art invention being modified, then the teachings of the references are not sufficient to render the claims prima facie obvious” (see also In re Ratti, 270 F.2d 810, 813, 123 USPQ 349, 352 (CCPA 1959) ("suggested combination of references would require a substantial reconstruction and redesign of the elements shown in [the primary reference] as well as a change in the basic principle under which the [primary reference] construction was designed to operate”).
Furthermore, according to 37 C.F.R. 1.111, “The reply by the applicant or patent owner must be reduced to a writing which distinctly and specifically points out the supposed errors in the examiner’s action”.
Here, Applicant argues the modification of the retuning of an analog circuit by changing the electrical characteristics of its tunable components of Andraud with the digital logic circuits with discrete logic gates of Carter would render the prior art unsatisfactory for its intended purpose (Pg. 34-35). Specifically, Applicant argues that Andraud in view of Carter fail to teach the storing of change control bits and using them to change the electrical characteristics of the tunable dominant components because Carter’s control bits are inherently digital and operate only on digital logic elements, whereas Andraud’s tuning Knobs adjust analog circuit behavior (Pg. 35-37). Furthermore, Applicant alleges the principle of operation of Andraud is continuous and analog, whereas Carter pertains to digital logic with configurable logic gates and switch-based digital signal control (Pg. 37). As a result, Applicant argues the modification would require substantial reengineering of Andraud’s analog system, which would render it inoperative for its purpose (Pg. 37). Furthermore, Applicant asserts that Carter’s architecture cannot process on the-fly PVT signals or interact with an AI Engine to retune analog components.
However, the use of digital controls to adjust analog circuits is well-established and known to provide advantageous over alternative control approaches (Wilamowski et al., “Digitally Tuned Analog VLSI Controllers”, Pg. 1185, Col. 1, Abstract, “Digitally controlled analog circuits have the following advantages: lower cost, high speed and small signal latency, parallel processing, direct implementation of continuous time designs, and smaller system noise important for a precision control” and Pg. 1187, Col. 1, Para. 2, “The digitally adjusted analog controller concept”). As a result, nothing in the prior art teaches that the proposed modification would have resulted in the inoperability of the process disclosed by Andraud. Additionally, Applicant does not provide any additional justification for the asserted incapabilities of Carter’s architecture. Furthermore, as currently recited in the claims, Applicant the connection between the change control bits and the tunable dominant components at a high level of generality, which does not preclude a mixed analog/digital connection.
As a result, the argument is not persuasive.
Additionally, Applicant argues combining the teachings of Andraud and Carter would not render the claims prima facia obvious because the combination would change the principle of operation of the prior invention being modified (Pg. 38). Specifically, Applicant argues the proposed modification would require substantial reengineering of process disclosed by Andraud (Pg. 37).
However, as pointed out by the Applicant, Andraud does not disclose a specific method of operation wherein the tuning knobs effectuate the adjustment of tunable components to effectuate the operations of analog circuit self-healing. Additionally, as also discussed in detail above, the use of digital controls to adjust analog circuits is well-established and known to provide advantageous over alternative control approaches (Wilamowski et al., “Digitally Tuned Analog VLSI Controllers”, Pg. 1185, Col. 1, Abstract, “Digitally controlled analog circuits have the following advantages: lower cost, high speed and small signal latency, parallel processing, direct implementation of continuous time designs, and smaller system noise important for a precision control” and Pg. 1187, Col. 1, Para. 2, “The digitally adjusted analog controller concept”). Therefore, the proposed combination does not change the principle of operation of Andraud because Andraud discloses only the result of adjustment of tunable analog components, without providing specific which could conflict with the approach of Carter, and the use digital controls to effectuate the adjustment of tunable analog components was well-established before the effective filing date of the claimed invention.
As a result, the argument is not persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW BRYCE GOLAN whose telephone number is (571)272-5159. The examiner can normally be reached Monday through Friday, 8:00 AM to 5:00 PM ET.
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/MATTHEW BRYCE GOLAN/Examiner, Art Unit 2123
/ALEXEY SHMATOV/Supervisory Patent Examiner, Art Unit 2123