DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending for examination. This Office Action is FINAL.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 7, 16, and 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 7, 16, and 20 recite “and not issue an interrupt to the server before completion of the at least one action” in the second-to-last and/or last line. [0034] of the instant specification describes using a match-action table 232 as an error exception handling to configure packet re-routing. [0040] further describes using processors 404 and/or FPGAs 440 to perform event detection and action, wherein processors 404 include a programmable processing pipeline with one or more match-action units to schedule packets for transmission. [0042] describes coalescing interrupts, in which interrupt coalescing 422 waits for multiple packets to arrive, or for a timeout to expire, before generating an interrupt to host system to process received packet(s). However, it is unclear whether or not the interrupt coalescing 422 waits for the same packets as the rerouted/scheduled packets of the one or more match-action units before generating an interrupt to the host.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, 10-15, 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over He et al. (US 12323482 B2, hereinafter “He”) in view of Rajagopal et al. (US 20150227404 A1, hereinafter “Rajagopal”).
Regarding Claim 1, He discloses an apparatus (Fig. 17) comprising:
a network interface device (Fig. 17: reference character 1700 contains switch 1704 with various ports . Col 26, lines 1-8: the entirety of device 1700 serves as a network interface device as packets are routed to and from ports of switch 1704, in which any of the ports are connected to a network of one or more interconnected devices) comprising:
an interface (Fig. 17: ports 1702-0, 1702-X, 1706-0, and 1706-Y);
a circuitry (Fig. 17: FPGAs 1718); and
a device, communicatively coupled to the interface (Fig. 17: switch 1704 is coupled to ports 1702-0, 1702-X, 1706-0, and 1706-Y), wherein the circuitry is to perform at least one action for at least one error or exception handling event based on a configuration specified by an instruction set consistent with a programmable packet processing language (Col 15, lines 64-67 and Col 16, lines 1-5: The data plane in switch 1202 is used for traffic policy (e.g., routing policies to apply in the event of congestion). Fig. 17 and Col 25, lines 63-67: Various resources in the switch, including packet processing pipelines 1712, can perform traffic policy application. Fig. 18 and Col 27, lines 37-54: pipelines include a match-action unit (MAU) 1824 or 1834 to process packets. The matching action may include sending packets to a particular port. Fig. 17 and Col 26, lines 38-43: Packet processing pipelines 1712 can be configured and programmed by P4. Therefore, the instruction set implemented by packet processing language P4 is configured to execute the packet processing pipeline (i.e., the handling event). The packet processing pipeline may be executed to apply traffic policies in response to network congestion (i.e., the error or exception)) and…, wherein the at least one error or exception handling event is associated with packet processing (see above – MAU processes packets to remediate congestion).
He does not disclose:
…after the error or exception handling, indicate to a server an occurrence of the at least one error or exception handling event…
However, Rajagopal teaches:
…after the error or exception handling, indicate to a server an occurrence of the at least one error or exception handling event… (Fig. 8, steps 825-830 and [0066]: after agent obtains notification that a corrective action has been taken ([0065]: to remedy a fault; corrective action is interpreted as an error handling event), the agent generates and sends a corrective action confirmation to the diagnostics server).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine He and Rajagopal by implementing the confirmation message taught by Rajagopal. One of ordinary skill in the art would be motivated to make this modification in order to provide means for communication to improve fault classification, correction, and analysis (Rajagopal: [0065]).
Regarding Claim 2, He in view of Rajagopal teaches the apparatus of claim 1, as referenced above, wherein the device comprises a programmable packet processing pipeline (He: Fig. 17, packet processing pipelines 1712 is implemented in switch 1704) and the programmable packet processing pipeline comprises the circuitry (He: Fig. 17 and Col 26, lines 38-43: FPGAs 1718 in switch 1704 can be utilized for packet processing. Fig. 18 and Col 26, lines 44-49: depicts an example programmable packet processing pipeline that may be used in a switch. Col 26, lines 56-66: the processing pipeline comprises of ingress and egress pipelines that may share or use separate circuitry. Therefore, the programmable packet processing pipeline is interpreted as the combination of pipelines 1712 and FPGAs 1718).
Regarding Claim 3, He in view of Rajagopal teaches the apparatus of claim 1, as referenced above, wherein the programmable packet processing language comprises one or more of: Programming Protocol-independent Packet Processors (P4), Software for Open Networking in the Cloud (SONiC), C, or Python (He: Col 26, lines 38-43: pipeline 1712 may be programmed in P4, C, or Python).
Regarding Claim 4, He in view of Rajagopal teaches the apparatus of claim 1, wherein the circuitry comprises one or more of: field programmable gate array (FPGA), application specific integrated circuit (ASIC), central processing unit (CPU), processor, or graphics processing unit (GPU) (Fig. 17: FPGA 1718).
Regarding Claim 6, He in view of Rajagopal teaches the apparatus of claim 1, as referenced above, wherein the device comprises one or more of: a network interface controller (NIC), a remote direct memory access (RDMA)-enabled NIC, SmartNIC, router, switch, forwarding element, infrastructure processing unit (IPU), data processing unit (DPU), accelerator, storage device, memory device, graphics processing unit, cryptographic offload circuity, workload queue manager, or audio or sound processing device (Fig. 17: switch 1704 includes memory 1708).
Regarding Claim 10, the apparatus of Claim 1 performs the same steps as the medium of Claim 10, and Claim 10 is rejected using the same art and rationale set forth above in the rejection of Claim 1 by the teachings of He in view of Rajagopal.
He further discloses at least one non-transitory computer-readable medium comprising instructions stored thereon, …executed by one or more processors (Col 33, lines 34-59: non-transitory storage medium to store or maintain instructions stored within the processor)
Regarding Claim 11, He in view of Rajagopal teaches the medium of Claim 10 above. The apparatus of Claim 2 performs the same steps as the medium of Claim 11, and Claim 11 is rejected using the same art and rationale set forth above in the rejection of Claim 2 by the teachings of He in view of Rajagopal.
Regarding Claim 12, He in view of Rajagopal teaches the at least one non-transitory computer-readable medium of claim 11, as referenced above, wherein the programmable packet processing language comprises one or more of: Programming Protocol-independent Packet Processors (P4), Software for Open Networking in the Cloud (SONiC), C, or Python (He: Col 26, lines 38-43: pipeline 1712 may be programmed in P4, C, or Python).
Regarding Claim 13, He in view of Rajagopal teaches the medium of Claim 10 above. The apparatus of Claim 4 performs the same steps as the medium of Claim 13, and Claim 13 is rejected using the same art and rationale set forth above in the rejection of Claim 4 by the teachings of He in view of Rajagopal.
Regarding Claim 14, He in view of Rajagopal teaches the medium of Claim 10 above. The apparatus of Claim 5 performs the same steps as the medium of Claim 14, and Claim 14 is rejected using the same art and rationale set forth above in the rejection of Claim 5 by the teachings of He in view of Rajagopal.
Regarding Claim 15, He in view of Rajagopal teaches the medium of Claim 10 above. The apparatus of Claim 6 performs the same steps as the medium of Claim 15, and Claim 15 is rejected using the same art and rationale set forth above in the rejection of Claim 6 by the teachings of He in view of Rajagopal.
Regarding Claim 17, He discloses a method (Fig. 17) comprising:
developing an instruction set consistent with a programmable packet processing language (Col 26, lines 38-43: pipeline 1712 may be programmed in P4, C, Python, Broadcom NPL, or x86. Col 32, lines 55-67. Col 33, lines 24-32: the implemented logic may be an instruction set), when executed, to cause circuitry to perform at least one action for at least one error or exception handling event (Fig. 17, switch 1704 contains FGPAs 1718. Col 15, lines 64-67 and Col 16, lines 1-5: The data plane in switch 1202 is used for traffic policy (e.g., routing policies to apply in the event of congestion). Fig. 17 and Col 25, lines 63-67: Various resources in the switch, including packet processing pipelines 1712, can perform traffic policy application. Fig. 18 and Col 27, lines 37-54: pipelines include a match-action unit (MAU) 1824 or 1834 to process. The matching action may include sending packets to a particular port. Fig. 17 and Col 26, lines 38-43: Packet processing pipelines 1712 can be configured and programmed by P4. Therefore, the instruction set implemented by packet processing language P4 is configured to execute the packet processing pipeline (i.e., the handling event). The packet processing pipeline be executed to apply traffic policies in response to network congestion) and…, wherein the at least one error or exception handling event is associated with packet processing (see above – MAU processes packets to remediate congestion).
He does not disclose:
…after the error or exception handling, indicating to a server an occurrence of the at least one error or exception handling event based on a configuration specified by the instruction set…
However, Rajagopal teaches:
…after the error or exception handling, indicating to a server an occurrence of the at least one error or exception handling event based on a configuration specified by the instruction set… (Fig. 8, steps 825-830 and [0066]: after agent obtains notification that a corrective action has been taken ([0065]: to remedy a fault; corrective action is interpreted as an error handling event), the agent generates and sends a corrective action confirmation to the diagnostics server. [0078]: the steps described are performed by instructions executed by one or more processors).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine He and Rajagopal by implementing the confirmation message taught by Rajagopal. One of ordinary skill in the art would be motivated to make this modification in order to provide means for communication to improve fault classification, correction, and analysis (Rajagopal: [0065]).
Regarding Claim 18, He in view of Rajagopal teaches the method of claim 17, as referenced above, wherein the circuitry comprises a programmable packet processing pipeline (He: Fig. 17: pipeline 1712 is implemented in switch 1794. Col 26, line 38-43: FPGAs 1718 can be utilized packet processing).
Regarding Claim 19, He in view of Rajagopal teaches the method of claim 18, as referenced above, wherein the programmable packet processing language comprises one or more of: Programming Protocol-independent Packet Processors (P4), C, or Python (He: Col 26, lines 38-43: pipeline 1712 may be programmed in P4, C, or Python).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Hein view of Rajagopal, in further view of Mahajan et al. (US 20150358200 A1, hereinafter “Mahajan”).
Regarding Claim 5, He in view of Rajagopal teaches the apparatus of claim 1, as referenced above, wherein based on detection of the at least one error or exception handling event, the circuitry is to perform at least one action associated with the at least one error or exception handling event (Col 15, lines 64-67 and Col 16, lines 1-5: Data plane in switch 1202 used for traffic policy (e.g., routing policies to apply in the event of congestion), therefore congestion is detected prior to applying routing policies. Fig. 17 and Col 25, lines 63-67: Various resources in the switch, including packet processing pipelines 1712, can perform traffic policy application. Fig. 18 and Col 27, lines 37-54: pipelines include a match-action unit (MAU) 1824 or 1834 to process packets. The matching action may include sending the packet to a particular port)
He in view of Rajagopal does not teach:
…and wherein the error or exception handling event comprises: identification of a particular destination Internet Protocol (IP) address in a packet, particular packet loss rate being met, traffic speed being met, packet count being met, a particular byte count being met, a particular throughput level being met, or a particular channel utilization being met.
However, Mahajan teaches:
…and wherein the error or exception handling event comprises: identification of a particular destination Internet Protocol (IP) address in a packet, particular packet loss rate being met, traffic speed being met, packet count being met, a particular byte count being met, a particular throughput level being met, or a particular channel utilization being met ([0015]: fault handling service 102 spreads traffic in the network such that no congestion occurs e.g., a link does not exceed a bandwidth capacity. Link capacity encompasses meeting a particular throughput level – i.e., under bandwidth capacity).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine He, Rajagopal, and Mahajan by implementing the traffic routing in terms of bandwidth capacity as taught by Mahajan. One of ordinary skill in the art would be motivated to make this modification in order to ensure that no congestion occurs (Mahajan: [0013], [0015]).
Claims 7, 16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over He in view of Rajagopal, in further view of XU et al. (US 20220006548 A1, hereinafter “XU”).
Regarding Claim 7, He in view of Rajagopal teaches the apparatus of claim 1, as referenced above, wherein the circuitry is to indicate to the server occurrence of the at least one error or exception handling event after performance of the at least one action (Rajagopal: Fig. 1A-1C and [0021]: “Agent” refers to agent device 130, which contains circuitry. Fig. 8, steps 825-830 and [0066]: after the agent obtains a notification that the corrective action is completed, the agent sends a confirmation to the diagnostics server)…
He in view of Rajagopal does not teach:
…and not issue an interrupt to the server before completion of the at least one action
However, XU teaches:
and not issue an interrupt to the server before completion of the at least one action (Abstract: after correcting a transmission error in a network timing process, the physical layer of a server receives a data packet. The physical layer then sends the data to the application layer of the server using interrupt mode. Therefore, the packet arrives in interrupt mode (i.e., sends an interrupt) to the server after the transmission error correction action is completed)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine He, Rajagopal, and XU by implementing the interrupt mode taught by XU. One of ordinary skill in the art would be motivated to make this modification in order to control network timing precision (XU: [0006] and [0012]).
Regarding Claim 16, He in view of Rajagopal teaches the medium of Claim 10 above. The apparatus of Claim 7 performs the same steps as the medium of Claim 16, and Claim 16 is rejected using the same art and rationale set forth above in the rejection of Claim 7 by the teachings of He in view of Rajagopal, in further view of XU.
Regarding Claim 20, He in view of Rajagopal teaches the method of claim 17, as referenced above, wherein execution of the instruction set causes the circuitry to perform at least one action associated with the at least one error or exception handling event (Col 15, lines 64-67 and Col 16, lines 1-5: Data plane in switch 1202 used for traffic policy (e.g., routing policies to apply in the event of congestion), therefore congestion is detected prior to applying routing policies. Fig. 17 and Col 25, lines 63-67: Various resources in the switch, including packet processing pipelines 1712, can perform traffic policy application. Fig. 18 and Col 27, lines 37-54: pipelines include a match-action unit (MAU) 1824 or 1834 to process packets. The matching action may include sending the packet to a particular port)…
He in view of Rajagopal does not teach:
…and not issue an interrupt to a server before completion of the at least one action.
However, XU teaches:
…and not issue an interrupt to a server before completion of the at least one action (Abstract: after correcting a transmission error in a network timing process, the physical layer of a server receives a data packet. The physical layer then sends the data to the application layer of the server using interrupt mode. Therefore, the packet arrives in interrupt mode (i.e., sends an interrupt) to the server after the transmission error correction action is completed).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine He, Rajagopal, and XU by implementing the interrupt mode taught by XU. One of ordinary skill in the art would be motivated to make this modification in order to control network timing precision (XU: [0006] and [0012]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over He in view of Rajagopal, in further view of MESNIER et al. (WO 2020186081 A1, hereinafter MESNIER)*.
*Note: a copy of MESNIER may be found in the file wrapper under doc code “FOR” with receipt date “07/11/2025”
Regarding Claim 8, He in view of Rajagopal teaches the apparatus of claim 1, as referenced above.
He in view of Rajagopal does not teach:
comprising the server communicatively coupled to the interface, wherein the server is to offload event detection and action to the circuitry.
However, MESNIER teaches:
comprising the server communicatively coupled to the interface (Fig. 1: host 102 coupled to client offload logic 114 and client offload library 115), wherein the server is to offload event detection and action to the circuitry (Fig. 1 and [0067]: computing system 100 may include a host 102 (containing processor 106) and block storage device 104 (e.g., SSD, block-based storage server). [0172]: Computations are moved from the host server to the target storage server. Fig. 48 and [0381]-[0383]: Bitrot detection and checksum calculation are offloaded to SSDs instead of hosts/CPUs).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine He and MESNIER by offloading the error detection and calculating taught by MESNIER as an additional feature to the diagnostics server taught by Rajagopal. One of ordinary skill in the art would be motivated to make this modification in order to free up CPU and I/O bandwidth for higher priority, latency sensitive operations (MESNIER: [0383]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over He in view of Rajagopal, in further view of MESNIER, in further view of Reddy et al. (US 20200341904 A1, hereinafter “Reddy”).
Regarding Claim 9, He in view of Rajagopal, in further view of MESINER teaches the apparatus of claim 8, as referenced above.
He in view of Rajagopal, in further view of MESINER does not teach:
comprising a data center comprising the server and a second server, wherein the circuitry is to provide telemetry data concerning operation of the device to the server and the server is to provide the telemetry data to the second server and where the second server is to execute an orchestrator to allocate hardware resources to processes based on the telemetry data.
However, Reddy teaches:
comprising a data center comprising the server and a second server (Fig. 1 and [0028]: data center 100 may be allocated to a managed node containing resources from various sleds. The aggregated resources form a composite node (“managed node”), stated to act as a server. Fig. 15 and [0078]: orchestrator server 1520 is a second server alongside managed node 1570), wherein the circuitry is to provide telemetry data concerning operation of the device to the server ([0078]: telemetry data received by orchestrator server 1520 indicates performance of each slide 400 of managed node 1570. [0028]: resources (sleds) may belong to different racks or pods. Therefore, telemetry data is sent to and aggregated at managed node 1570 (see Fig. 15)) and the server is to provide the telemetry data to the second server and where the second server is to execute an orchestrator to allocate hardware resources to processes based on the telemetry data ([0078]: orchestrator server 1520 may receive telemetry data of managed node 1570 to determine whether quality of service (QoS) targets are met. Orchestrator server 1520 may additionally determine whether one or more physical resources may be dynamically allocated to assist in workload execution and maintain QoS satisfaction).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine He, Rajagopal, MESINIER, and Reddy by implementing the orchestrator server and resource allocation taught by Reddy. One of ordinary skill in the art would be motivated to make this modification in order to satisfy QoS targets (Reddy: [0078]).
Response to Arguments
Applicant's arguments filed 10/14/2025 regarding 35 U.S.C. 102 and 103 have been fully considered but are moot.
Applicant’s arguments with respect to the Specification have been fully considered and persuasive. The objections of the Specification have been withdrawn.
Applicant’s arguments with respect to the Fig. 6 have been fully considered and persuasive. The objection of Fig. 6 has been withdrawn.
Applicant’s arguments with respect to the claim objections have been fully considered and persuasive. The objections of the Claims 3, 9, 11-16 and 19 have been withdrawn.
Applicant’s arguments with respect to the 35 U.S.C. 112(b) have been fully considered and persuasive. The 112(b) rejections of the Claims 3, 12, and 19 have been withdrawn.
Applicant’s arguments with respect to claim(s) 1-6, 10-15 and 17-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant argues:
“He does not disclose claim 1's "perform at least one action for at least one error or exception handling event based on a configuration specified by an instruction set consistent with a programmable packet processing language and after the error or exception handling, indicate to a server an occurrence of the at least one error or exception handling event, wherein the at least one error or exception handling event is associated with packet processing."
Examiner agrees with the applicant and withdraws the previous 35 U.S.C. 102 rejection of Claim 1. Instead, Claim 1 is rejected under 35 U.S.C. 103 in light of He in view of Rajagopal.
He discloses using a programmable packet processing pipeline to perform traffic policy application (Col 25, lines 63-66), which involves processing packets via sending the packets to a particular port (Col 27, lines 37-54). Traffic policy may be applied in the event of congestion (Col 16, lines 2-3), in which the congestion is interpreted as a type of error. This interpretation is consistent with [0034] of the instant specification, which recognizes congestion as a trigger for error or exception handling.
Although He does not teach “…indicate to a server an occurrence of the at least one error or exception handling event…,” Rajagopal cures the deficiencies of He by teaching a device that sends a confirmation of the completed corrective action corresponding to a fault to a diagnostics server ([0066]). Therefore, Claim 1 remains rejected in light of He in view of Rajagopal. Claims 10 and 17 are also rejected for similar reasons.
Regarding the 35 U.S.C. 103 rejections of Claims 7/16 and 8/9, applicant argues:
“Applicants do not concede that teachings of He and Rajagopal are properly combinable.”
“Applicants do not concede that teachings of He and Mesnier are properly combinable.”
Examiner respectfully disagrees.
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, Rajagopal provide means for communication to improve fault classification, correction, and analysis (Rajagopal: [0065]), Likewise, Mesnier allows the host (containing a CPU) to free up CPU and I/O bandwidth for higher priority, latency sensitive operations (MESNIER: [0383]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CATHERINE MARIE NGUYEN whose telephone number is (571)272-6160. The examiner can normally be reached M-F 7am-4pm.
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/C.M.N./Examiner, Art Unit 2114
/ASHISH THOMAS/Supervisory Patent Examiner, Art Unit 2114