Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner’s Note
The Examiner encourages Applicant to schedule an interview to discuss issues related to, for example, the rejections noted below under 35 U.S.C § 112 and § 103, for moving forward allowance.
Providing supporting paragraph(s) for each limitation of amended/new claim(s) in Remarks is strongly requested for clear and definite claim interpretations by Examiner.
Priority
Acknowledgment is made of applicant's claim for the present application filed on 05/31/2022.
Claim Objections
Claim(s) 14-17 is/are objected to because of the following informalities.
Claim(s) 14 is/are objected to because of the following informalities: it appears that “the second plurality of qubits” (line 2) needs to read “second plurality of physical qubits” or something else. Appropriate correction is required.
Claim(s) 14 each recite(s) limitations that raise issues of indefiniteness as set forth above, and their dependent claims are objected to at least based on their direct and/or indirect dependency from the claim listed above. Appropriate explanation and/or amendment is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “local” (claim 1, line 6) is a relative term which renders the claim indefinite. The term “local” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. In addition, claim(s) 3-4, 13 (two times) is/are rejected for the same reason.
Claim(s) 6 recite(s) the limitation “the synchronization qubits of the first QPU” (line 4). There is insufficient antecedent basis for this limitation in the claim. It is not clear if it indicates “synchronization qubits” for the second QPU (claim 6, line 3) or it means “synchronization qubits” for the first QPU, or something else. It appears it may need to read “synchronization qubits”, or something else. For the purposes of examination, “synchronization qubits” is used.
The term “global” (claim 7, line 2) is a relative term which renders the claim indefinite. The term “global” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. In addition, claim(s) 7 (three times more), 15 (four times) is/are rejected for the same reason.
Claim(s) 1, 3-4, 6, 7, 13, 15 each recite(s) limitations that raise issues of indefiniteness as set forth above, and their dependent claims are rejected at least based on their direct and/or indirect dependency from the claim listed above. Appropriate explanation and/or amendment is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4-5, 9-13, 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Andrés-Martínez et al. (Automated distribution of quantum circuits via hypergraph partitioning) in view of Monras et al. (Quantum Information Processing with Quantum Zeno Many-Body Dynamics)
Regarding claim 1
Andrés-Martínez teaches
An apparatus comprising:
a first quantum processing unit (QPU) configured to perform one or more quantum walks,
(Andrés-Martínez [fig(s) 2] “Implementation, as in [30], of a group of nonlocal CZ gates that share a common qubit. Circuit a) is the original circuit, b) is the distributed version. The dashed line indicates how the circuit is separated into two QPUs. The bent wire on the left of b) represents an ebit. The measurement outcomes are communicated through a classical network.” [sec(s) II] “This section describes the essential characteristics of any distributed architecture and identifies communication across QPUs as the main bottleneck. We then detail the problem at hand and discuss related work from the literature. Finally, we describe the standard way nonlocal multi-qubit gates are executed across QPUs, which will be required when building distributed circuits. … We use an approach pioneered by Gottesman and Chuang [31] to implement multi-qubit gates across distant qubits using entangled mutipartite states and measurements.” [sec(s) IV] “Our algorithm was evaluated on five quantum circuits provided by Quipper’s library [39]. These circuits implement algorithms that have been discussed in the literature as examples where quantum computers achieve computational speedup. Their default configuration was used unless stated otherwise: • Boolean formula (BF) [41]: the circuit fragment implementing the quantum walk, the core of the algorithm; • Binary welded tree (BWT) [42]: tree height set to 200 (from 5 by default);”;)
(Note: Hereinafter, if a limitation has bold brackets (i.e. [·]) around claim languages, the bracketed claim languages indicate that they have not been taught yet by the current prior art reference but they will be taught by another prior art reference afterwards.)
wherein the first QPU comprises a first plurality of physical qubits [propagating] across a first plurality of nodes, and
(Andrés-Martínez [fig(s) 2] “Implementation, as in [30], of a group of nonlocal CZ gates that share a common qubit. Circuit a) is the original circuit, b) is the distributed version. The dashed line indicates how the circuit is separated into two QPUs. The bent wire on the left of b) represents an ebit. The measurement outcomes are communicated through a classical network.” [sec(s) II] “This section describes the essential characteristics of any distributed architecture and identifies communication across QPUs as the main bottleneck. We then detail the problem at hand and discuss related work from the literature. Finally, we describe the standard way nonlocal multi-qubit gates are executed across QPUs, which will be required when building distributed circuits. … We use an approach pioneered by Gottesman and Chuang [31] to implement multi-qubit gates across distant qubits using entangled mutipartite states and measurements. In particular, we will use the scheme proposed in [30] which, using a single ebit, implements any number of contiguous nonlocal CZ gates that act on a common qubit, as shown in Figure 2. To do so, a so-called cat-entangler first shares the state of the common qubit with the remote QPU, which requires the use of an ebit; then, the CZ gates are locally performed on the remote QPU and finally the cat-disentangler destructively measures the remaining ebit half to remove any residual entanglement.”;)
wherein at least a portion of the first plurality of nodes are local nodes configured to perform the one or more quantum walks on the first QPU.
(Andrés-Martínez [fig(s) 2] “Implementation, as in [30], of a group of nonlocal CZ gates that share a common qubit. Circuit a) is the original circuit, b) is the distributed version. The dashed line indicates how the circuit is separated into two QPUs. The bent wire on the left of b) represents an ebit. The measurement outcomes are communicated through a classical network.” [sec(s) II] “This section describes the essential characteristics of any distributed architecture and identifies communication across QPUs as the main bottleneck. We then detail the problem at hand and discuss related work from the literature. Finally, we describe the standard way nonlocal multi-qubit gates are executed across QPUs, which will be required when building distributed circuits. … We use an approach pioneered by Gottesman and Chuang [31] to implement multi-qubit gates across distant qubits using entangled mutipartite states and measurements.” [sec(s) IV] “Our algorithm was evaluated on five quantum circuits provided by Quipper’s library [39]. These circuits implement algorithms that have been discussed in the literature as examples where quantum computers achieve computational speedup. Their default configuration was used unless stated otherwise: • Boolean formula (BF) [41]: the circuit fragment implementing the quantum walk, the core of the algorithm; • Binary welded tree (BWT) [42]: tree height set to 200 (from 5 by default);”; e.g., nodes for one of the “two QPUs” along with fig 2 read(s) on “local nodes”.)
However, Andrés-Martínez does not appear to explicitly teach:
wherein the first QPU comprises a first plurality of physical qubits [propagating] across a first plurality of nodes, and
(Note: Hereinafter, if a limitation has one or more bold underlines, the one or more underlined claim languages indicate that they are taught by the current prior art reference, while the one or more non-underlined claim languages indicate that they have been taught already by one or more previous art references.)
Monras teaches
wherein the first QPU comprises a first plurality of physical qubits propagating across a first plurality of nodes, and
(Monras [fig(s) 7] “LET one qubit propagate freely between site 2” [sec(s) III] “The natural evolution under the Hamiltonian HC corresponds to a delocalization of the qubit, by a continuous time quantum walk [12, 13] with Dirichlet boundary conditions <0|ρ|0> = <n + 1|ρ|n + 1> = 0, while preserving its internal state. The position of the qubit can be localized on-demand by simply measuring Lˆ. Moreover, if Lˆ is performed continuously, the time evolution is frozen and delocalization is prevented [see Fig 1b].” [sec(s) IV] “In this scheme, the qubit evolves as a continuous time quantum walk driven by the QZE, namely, by measuring the appropriate sites the space where the walk takes place can be dynamically changed. … For large ∆t the qubit will propagate freely along the chain. For small ∆t the QZE will be invoked, thus hindering the qubit from propagating. At some optimal ∆t the anti-Zeno effect will push the qubit forward [See Fig. 3a], providing a speedup of about 12% with respect to the free propagation speed. A constant qubit-rate for schemes 2 & 3 could also be achieved by allowing to move the right boundary of each block, as in scheme 1. These three schemes exploit the fact that the block boundaries act as potential barriers and the qubit propagates as a free particle in the lattice.”;)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Andrés-Martínez with the qubit propagation of Monras.
One of ordinary skill in the art would have been motived to combine in order to simplify the control requirements for physical implementation by avoiding the need for complex and time-dependent interactions. The control is managed by simple, frequent local measurements.
(Monras [sec(s) I] “However, this implementation often requires a great amount of control of the dynamics. Such a control could be achieved, of course, if one would have the possibility to modify the interactions on demand. In this case, the engineering protocol would consist in a sequence of interaction tunings yielding a complex time dependent Hamiltonian. In this article, we show that this kind of control can also be achieved using an always-on many-body Hamiltonian. More specifically, we are interested in devising a scheme to move qubits and perform universal two-qubit gates within a many-body system in which the Hamiltonian is constant [26]. Indeed, we shall argue that this can be achieved even within a one-dimensional many-body system (spin chain hereafter). The key ingredient in order to control the dynamics will be the quantum Zeno effect [5, 6]. The quantum Zeno effect prevents some particular subspaces from being populated and thus, renders an effective dynamics which in turn can take the role of the switching on and off of some interactions in the ideal case above mentioned.”)
Regarding claim 4
The combination of Andrés-Martínez, Monras teaches claim 1.
Andrés-Martínez further teaches
a second QPU in communication with the first QPU via a quantum channel and configured to perform the one or more quantum walks,
(Andrés-Martínez [fig(s) 2] “Implementation, as in [30], of a group of nonlocal CZ gates that share a common qubit. Circuit a) is the original circuit, b) is the distributed version. The dashed line indicates how the circuit is separated into two QPUs. The bent wire on the left of b) represents an ebit. The measurement outcomes are communicated through a classical network.” [sec(s) II] “This section describes the essential characteristics of any distributed architecture and identifies communication across QPUs as the main bottleneck. We then detail the problem at hand and discuss related work from the literature. Finally, we describe the standard way nonlocal multi-qubit gates are executed across QPUs, which will be required when building distributed circuits. … We use an approach pioneered by Gottesman and Chuang [31] to implement multi-qubit gates across distant qubits using entangled mutipartite states and measurements. In particular, we will use the scheme proposed in [30] which, using a single ebit, implements any number of contiguous nonlocal CZ gates that act on a common qubit, as shown in Figure 2. To do so, a so-called cat-entangler first shares the state of the common qubit with the remote QPU, which requires the use of an ebit; then, the CZ gates are locally performed on the remote QPU and finally the cat-disentangler destructively measures the remaining ebit half to remove any residual entanglement.” [sec(s) IV] “Our algorithm was evaluated on five quantum circuits provided by Quipper’s library [39]. These circuits implement algorithms that have been discussed in the literature as examples where quantum computers achieve computational speedup. Their default configuration was used unless stated otherwise: • Boolean formula (BF) [41]: the circuit fragment implementing the quantum walk, the core of the algorithm; • Binary welded tree (BWT) [42]: tree height set to 200 (from 5 by default);”;)
wherein the second QPU comprises a second plurality of physical qubits [propagating] across a second plurality of nodes, and
(Andrés-Martínez [fig(s) 2] “Implementation, as in [30], of a group of nonlocal CZ gates that share a common qubit. Circuit a) is the original circuit, b) is the distributed version. The dashed line indicates how the circuit is separated into two QPUs. The bent wire on the left of b) represents an ebit. The measurement outcomes are communicated through a classical network.” [sec(s) II] “This section describes the essential characteristics of any distributed architecture and identifies communication across QPUs as the main bottleneck. We then detail the problem at hand and discuss related work from the literature. Finally, we describe the standard way nonlocal multi-qubit gates are executed across QPUs, which will be required when building distributed circuits. … We use an approach pioneered by Gottesman and Chuang [31] to implement multi-qubit gates across distant qubits using entangled mutipartite states and measurements. In particular, we will use the scheme proposed in [30] which, using a single ebit, implements any number of contiguous nonlocal CZ gates that act on a common qubit, as shown in Figure 2. To do so, a so-called cat-entangler first shares the state of the common qubit with the remote QPU, which requires the use of an ebit; then, the CZ gates are locally performed on the remote QPU and finally the cat-disentangler destructively measures the remaining ebit half to remove any residual entanglement.”;)
wherein at least a portion of the second plurality of nodes are local nodes configured to perform the one or more quantum walks on the second QPU.
(Andrés-Martínez [fig(s) 2] “Implementation, as in [30], of a group of nonlocal CZ gates that share a common qubit. Circuit a) is the original circuit, b) is the distributed version. The dashed line indicates how the circuit is separated into two QPUs. The bent wire on the left of b) represents an ebit. The measurement outcomes are communicated through a classical network.” [sec(s) II] “This section describes the essential characteristics of any distributed architecture and identifies communication across QPUs as the main bottleneck. We then detail the problem at hand and discuss related work from the literature. Finally, we describe the standard way nonlocal multi-qubit gates are executed across QPUs, which will be required when building distributed circuits. … We use an approach pioneered by Gottesman and Chuang [31] to implement multi-qubit gates across distant qubits using entangled mutipartite states and measurements.” [sec(s) IV] “Our algorithm was evaluated on five quantum circuits provided by Quipper’s library [39]. These circuits implement algorithms that have been discussed in the literature as examples where quantum computers achieve computational speedup. Their default configuration was used unless stated otherwise: • Boolean formula (BF) [41]: the circuit fragment implementing the quantum walk, the core of the algorithm; • Binary welded tree (BWT) [42]: tree height set to 200 (from 5 by default);”; e.g., nodes for the other one of the “two QPUs” along with fig 2 read(s) on “local nodes”.)
Monras further teaches
wherein the second QPU comprises a second plurality of physical qubits propagating across a second plurality of nodes, and
(Monras [fig(s) 7] “LET one qubit propagate freely between site 2” [sec(s) III] “The natural evolution under the Hamiltonian HC corresponds to a delocalization of the qubit, by a continuous time quantum walk [12, 13] with Dirichlet boundary conditions <0|ρ|0> = <n + 1|ρ|n + 1> = 0, while preserving its internal state. The position of the qubit can be localized on-demand by simply measuring Lˆ. Moreover, if Lˆ is performed continuously, the time evolution is frozen and delocalization is prevented [see Fig 1b].” [sec(s) IV] “In this scheme, the qubit evolves as a continuous time quantum walk driven by the QZE, namely, by measuring the appropriate sites the space where the walk takes place can be dynamically changed. … For large ∆t the qubit will propagate freely along the chain. For small ∆t the QZE will be invoked, thus hindering the qubit from propagating. At some optimal ∆t the anti-Zeno effect will push the qubit forward [See Fig. 3a], providing a speedup of about 12% with respect to the free propagation speed. A constant qubit-rate for schemes 2 & 3 could also be achieved by allowing to move the right boundary of each block, as in scheme 1. These three schemes exploit the fact that the block boundaries act as potential barriers and the qubit propagates as a free particle in the lattice.”;)
The combination of Andrés-Martínez, Monras is combinable with Monras for the same rationale as set forth above with respect to claim 1.
Regarding claim 5
The combination of Andrés-Martínez, Monras teaches claim 4.
Andrés-Martínez further teaches
wherein the first QPU and the second QPU operate in parallel to perform the one or more quantum walks.
(Andrés-Martínez [fig(s) 2] “Implementation, as in [30], of a group of nonlocal CZ gates that share a common qubit. Circuit a) is the original circuit, b) is the distributed version. The dashed line indicates how the circuit is separated into two QPUs. The bent wire on the left of b) represents an ebit. The measurement outcomes are communicated through a classical network.” [sec(s) II] “This section describes the essential characteristics of any distributed architecture and identifies communication across QPUs as the main bottleneck. We then detail the problem at hand and discuss related work from the literature. Finally, we describe the standard way nonlocal multi-qubit gates are executed across QPUs, which will be required when building distributed circuits. … We use an approach pioneered by Gottesman and Chuang [31] to implement multi-qubit gates across distant qubits using entangled mutipartite states and measurements. In particular, we will use the scheme proposed in [30] which, using a single ebit, implements any number of contiguous nonlocal CZ gates that act on a common qubit, as shown in Figure 2. To do so, a so-called cat-entangler first shares the state of the common qubit with the remote QPU, which requires the use of an ebit; then, the CZ gates are locally performed on the remote QPU and finally the cat-disentangler destructively measures the remaining ebit half to remove any residual entanglement.” [sec(s) IV] “Our algorithm was evaluated on five quantum circuits provided by Quipper’s library [39]. These circuits implement algorithms that have been discussed in the literature as examples where quantum computers achieve computational speedup. Their default configuration was used unless stated otherwise: • Boolean formula (BF) [41]: the circuit fragment implementing the quantum walk, the core of the algorithm; • Binary welded tree (BWT) [42]: tree height set to 200 (from 5 by default);”;)
Regarding claim 9
The combination of Andrés-Martínez, Monras teaches claim 1.
Monras further teaches
wherein the one or more quantum walks are discrete-time quantum walks or continuous-time quantum walks.
(Monras [sec(s) IV] “In this scheme, the qubit evolves as a continuous time quantum walk driven by the QZE, namely, by measuring the appropriate sites the space where the walk takes place can be dynamically changed. Before entering the discussion in more detail, we want to point out that spin1 chains have previously been studied in the context of state transfer [16, 17, 18, 19, 20]. Although the measurement in Eq. (5) was used in the double rail encoding to check the arrival of the qubit without destroying its state [17], the possibility of enhancing the performance by the QZE was not considered. … Scheme 2, imaging: the qubit is initially near the left-end of a block and is left to evolve freely. After a long time ∆T a measurement Lˆ is performed and the left boundary of the block is shifted next to the qubit. The procedure is repeated until the block has the desired size and position. The transfer speed with this procedure, assuming that the transfer distance is large (n ≫ 1), and thus the block is always much larger that the width of the wave packet, corresponds to the free propagation speed of a continuous-time quantum walk with one boundary.”;)
The combination of Andrés-Martínez, Monras is combinable with Monras for the same rationale as set forth above with respect to claim 1.
Regarding claim 10
The combination of Andrés-Martínez, Monras teaches claim 1.
Andrés-Martínez teaches
wherein the one or more quantum walks are conducted across the first plurality of nodes of at least the first QPU so as to form a graphical structure.
(Andrés-Martínez [fig(s) 2-3, 5] [sec(s) II] “This section describes the essential characteristics of any distributed architecture and identifies communication across QPUs as the main bottleneck. We then detail the problem at hand and discuss related work from the literature. Finally, we describe the standard way nonlocal multi-qubit gates are executed across QPUs, which will be required when building distributed circuits. … We use an approach pioneered by Gottesman and Chuang [31] to implement multi-qubit gates across distant qubits using entangled mutipartite states and measurements. In particular, we will use the scheme proposed in [30] which, using a single ebit, implements any number of contiguous nonlocal CZ gates that act on a common qubit, as shown in Figure 2. To do so, a so-called cat-entangler first shares the state of the common qubit with the remote QPU, which requires the use of an ebit; then, the CZ gates are locally performed on the remote QPU and finally the cat-disentangler destructively measures the remaining ebit half to remove any residual entanglement.” [sec(s) IV] “Our algorithm was evaluated on five quantum circuits provided by Quipper’s library [39]. These circuits implement algorithms that have been discussed in the literature as examples where quantum computers achieve computational speedup. Their default configuration was used unless stated otherwise: • Boolean formula (BF) [41]: the circuit fragment implementing the quantum walk, the core of the algorithm; • Binary welded tree (BWT) [42]: tree height set to 200 (from 5 by default);”; e.g., figs 2-3 and/or fig 5 and/or fig 10 read(s) on “graphical structure”.)
Regarding claim 11
The combination of Andrés-Martínez, Monras teaches claim 10.
Andrés-Martínez further teaches
wherein performance of the one or more quantum walks on the first QPU comprises [propagation] of at least a portion of the first plurality of physical qubits across the first plurality of nodes responsive to one or more inputs from evolution operators.
(Andrés-Martínez [fig(s) 2] “The measurement outcomes are communicated through a classical network.” [fig(s) 3] [sec(s) II.A] “A classical communication network that the QPUs may send classical messages through when measuring their qubits and receive message over when applying corrections. … Moreover, while they assume the cost of classical communication to be negligible, the authors estimate that the generation of ebits will be roughly 300 times more costly than the application of a two-qubit gate locally within a QPU.” [sec(s) II] “This section describes the essential characteristics of any distributed architecture and identifies communication across QPUs as the main bottleneck. We then detail the problem at hand and discuss related work from the literature. Finally, we describe the standard way nonlocal multi-qubit gates are executed across QPUs, which will be required when building distributed circuits.” [sec(s) IV] “Their default configuration was used unless stated otherwise: • Boolean formula (BF) [41]: the circuit fragment implementing the quantum walk, the core of the algorithm; • Binary welded tree (BWT) [42]: tree height set to 200 (from 5 by default); … The times shown in the table indicate how long it took to obtain the distributed circuit using our implementation (available at [40]), running it on a standard desktop computer.” [sec(s) V] “that problem is intractable on a classical computer (namely, it is NP-hard [45]). Instead, we work with close to optimal solutions that can be found efficiently by classical computers. The results discussed in Section IV were obtained using such suboptimal partitions.”;)
Monras further teaches
wherein performance of the one or more quantum walks on the first QPU comprises propagation of at least a portion of the first plurality of physical qubits across the first plurality of nodes responsive to one or more inputs from evolution operators.
(Monras [fig(s) 7] “LET one qubit propagate freely between site 2” [sec(s) III] “The natural evolution under the Hamiltonian HC corresponds to a delocalization of the qubit, by a continuous time quantum walk [12, 13] with Dirichlet boundary conditions <0|ρ|0> = <n + 1|ρ|n + 1> = 0, while preserving its internal state. The position of the qubit can be localized on-demand by simply measuring Lˆ. Moreover, if Lˆ is performed continuously, the time evolution is frozen and delocalization is prevented [see Fig 1b].” [sec(s) IV] “In this scheme, the qubit evolves as a continuous time quantum walk driven by the QZE, namely, by measuring the appropriate sites the space where the walk takes place can be dynamically changed. … Scheme 3, “compressing” [see Fig 1d]: assume the qubit is encoded in site 1 (left) which needs to be transferred to site n (right). … For large ∆t the qubit will propagate freely along the chain. For small ∆t the QZE will be invoked, thus hindering the qubit from propagating. At some optimal ∆t the anti-Zeno effect will push the qubit forward [See Fig. 3a], providing a speedup of about 12% with respect to the free propagation speed. A constant qubit-rate for schemes 2 & 3 could also be achieved by allowing to move the right boundary of each block, as in scheme 1. These three schemes exploit the fact that the block boundaries act as potential barriers and the qubit propagates as a free particle in the lattice. Combinations of these schemes can provide a variety of performance vs. control tradeoffs and thus can be adapted to meet different demands depending on the particular requirements and limitations of a given physical implementation. It is worth noticing that schemes 2 & 3, which use large blocks perform significantly faster than scheme 1. The reason for this is that in scheme 1, the qubit is prevented from advancing too fast since it is constrained to a size-2 block.”;)
The combination of Andrés-Martínez, Monras is combinable with Monras for the same rationale as set forth above with respect to claim 1.
Regarding claim 12
The combination of Andrés-Martínez, Monras teaches claim 4.
Andrés-Martínez further teaches
further comprising a computer processing device in communication with the first QPU and the second QPU, wherein the computer processing device is configured to receive data generated by the one or more quantum walks performed by the first QPU and the second QPU.
(Andrés-Martínez [fig(s) 2] “The measurement outcomes are communicated through a classical network.” [fig(s) 3] [sec(s) II.A] “A classical communication network that the QPUs may send classical messages through when measuring their qubits and receive message over when applying corrections. … Moreover, while they assume the cost of classical communication to be negligible, the authors estimate that the generation of ebits will be roughly 300 times more costly than the application of a two-qubit gate locally within a QPU.” [sec(s) II] “This section describes the essential characteristics of any distributed architecture and identifies communication across QPUs as the main bottleneck. We then detail the problem at hand and discuss related work from the literature. Finally, we describe the standard way nonlocal multi-qubit gates are executed across QPUs, which will be required when building distributed circuits.” [sec(s) IV] “Their default configuration was used unless stated otherwise: • Boolean formula (BF) [41]: the circuit fragment implementing the quantum walk, the core of the algorithm; • Binary welded tree (BWT) [42]: tree height set to 200 (from 5 by default); … The times shown in the table indicate how long it took to obtain the distributed circuit using our implementation (available at [40]), running it on a standard desktop computer.” [sec(s) V] “that problem is intractable on a classical computer (namely, it is NP-hard [45]). Instead, we work with close to optimal solutions that can be found efficiently by classical computers. The results discussed in Section IV were obtained using such suboptimal partitions.”; e.g., “measurement outcomes are communicated through a classical network” along with “two QPUs”, “classical messages” and “classical computer” read(s) on “a computer processing device in communication with the first QPU and the second QPU”.)
Regarding claim 13
The claim is a method claim corresponding to a combination of the apparatus claims 1 and 4, and is directed to largely the same subject matter. Thus, it is rejected for the same reasons as given in the rejections of the combination of the apparatus claims.
Regarding claim 18
The claim is a method claim corresponding to the apparatus claim 9, and is directed to largely the same subject matter. Thus, it is rejected for the same reasons as given in the rejections of the apparatus claim.
Regarding claim 19
The combination of Andrés-Martínez, Monras teaches claim 13.
Andrés-Martínez further teaches
wherein the one or more quantum walks are conducted across the first plurality of nodes of the first QPU and the second plurality of nodes of the second QPU so as to form respective first and second graphical structures.
(Andrés-Martínez [fig(s) 2-3, 5] [sec(s) II] “This section describes the essential characteristics of any distributed architecture and identifies communication across QPUs as the main bottleneck. We then detail the problem at hand and discuss related work from the literature. Finally, we describe the standard way nonlocal multi-qubit gates are executed across QPUs, which will be required when building distributed circuits. … We use an approach pioneered by Gottesman and Chuang [31] to implement multi-qubit gates across distant qubits using entangled mutipartite states and measurements. In particular, we will use the scheme proposed in [30] which, using a single ebit, implements any number of contiguous nonlocal CZ gates that act on a common qubit, as shown in Figure 2. To do so, a so-called cat-entangler first shares the state of the common qubit with the remote QPU, which requires the use of an ebit; then, the CZ gates are locally performed on the remote QPU and finally the cat-disentangler destructively measures the remaining ebit half to remove any residual entanglement.” [sec(s) IV] “Our algorithm was evaluated on five quantum circuits provided by Quipper’s library [39]. These circuits implement algorithms that have been discussed in the literature as examples where quantum computers achieve computational speedup. Their default configuration was used unless stated otherwise: • Boolean formula (BF) [41]: the circuit fragment implementing the quantum walk, the core of the algorithm; • Binary welded tree (BWT) [42]: tree height set to 200 (from 5 by default);”; e.g., figs 2-3 and/or fig 5 and/or fig 10 read(s) on “graphical structures”.)
Regarding claim 20
The combination of Andrés-Martínez, Monras teaches claim 19.
Andrés-Martínez further teaches
performance of the one or more quantum walks on the first QPU comprises [propagation] of at least a portion of the first plurality of physical qubits across the first plurality of nodes of the first [graphical] structure responsive to one or more inputs from evolution operators; and
(Andrés-Martínez [fig(s) 2] “The measurement outcomes are communicated through a classical network.” [fig(s) 3] [sec(s) II.A] “A classical communication network that the QPUs may send classical messages through when measuring their qubits and receive message over when applying corrections. … Moreover, while they assume the cost of classical communication to be negligible, the authors estimate that the generation of ebits will be roughly 300 times more costly than the application of a two-qubit gate locally within a QPU.” [sec(s) II] “This section describes the essential characteristics of any distributed architecture and identifies communication across QPUs as the main bottleneck. We then detail the problem at hand and discuss related work from the literature. Finally, we describe the standard way nonlocal multi-qubit gates are executed across QPUs, which will be required when building distributed circuits.” [sec(s) IV] “Their default configuration was used unless stated otherwise: • Boolean formula (BF) [41]: the circuit fragment implementing the quantum walk, the core of the algorithm; • Binary welded tree (BWT) [42]: tree height set to 200 (from 5 by default); … The times shown in the table indicate how long it took to obtain the distributed circuit using our implementation (available at [40]), running it on a standard desktop computer.” [sec(s) V] “that problem is intractable on a classical computer (namely, it is NP-hard [45]). Instead, we work with close to optimal solutions that can be found efficiently by classical computers. The results discussed in Section IV were obtained using such suboptimal partitions.”;)
performance of the one or more quantum walks on the second QPU comprises [propagation] of at least a portion of the second plurality of physical qubits across the second plurality of nodes of the second [graphical] structure responsive to one or more inputs from the evolution operators
(Andrés-Martínez [fig(s) 2] “The measurement outcomes are communicated through a classical network.” [fig(s) 3] [sec(s) II.A] “A classical communication network that the QPUs may send classical messages through when measuring their qubits and receive message over when applying corrections. … Moreover, while they assume the cost of classical communication to be negligible, the authors estimate that the generation of ebits will be roughly 300 times more costly than the application of a two-qubit gate locally within a QPU.” [sec(s) II] “This section describes the essential characteristics of any distributed architecture and identifies communication across QPUs as the main bottleneck. We then detail the problem at hand and discuss related work from the literature. Finally, we describe the standard way nonlocal multi-qubit gates are executed across QPUs, which will be required when building distributed circuits.” [sec(s) IV] “Their default configuration was used unless stated otherwise: • Boolean formula (BF) [41]: the circuit fragment implementing the quantum walk, the core of the algorithm; • Binary welded tree (BWT) [42]: tree height set to 200 (from 5 by default); … The times shown in the table indicate how long it took to obtain the distributed circuit using our implementation (available at [40]), running it on a standard desktop computer.” [sec(s) V] “that problem is intractable on a classical computer (namely, it is NP-hard [45]). Instead, we work with close to optimal solutions that can be found efficiently by classical computers. The results discussed in Section IV were obtained using such suboptimal partitions.”;)
Monras further teaches
performance of the one or more quantum walks on the first QPU comprises propagation of at least a portion of the first plurality of physical qubits across the first plurality of nodes of the first graphical structure responsive to one or more inputs from evolution operators; and
(Monras [fig(s) 1-2, 4] [fig(s) 7] “LET one qubit propagate freely between site 2” [sec(s) III] “The natural evolution under the Hamiltonian HC corresponds to a delocalization of the qubit, by a continuous time quantum walk [12, 13] with Dirichlet boundary conditions <0|ρ|0> = <n + 1|ρ|n + 1> = 0, while preserving its internal state. The position of the qubit can be localized on-demand by simply measuring Lˆ. Moreover, if Lˆ is performed continuously, the time evolution is frozen and delocalization is prevented [see Fig 1b].” [sec(s) IV] “In this scheme, the qubit evolves as a continuous time quantum walk driven by the QZE, namely, by measuring the appropriate sites the space where the walk takes place can be dynamically changed. … Scheme 3, “compressing” [see Fig 1d]: assume the qubit is encoded in site 1 (left) which needs to be transferred to site n (right). … For large ∆t the qubit will propagate freely along the chain. For small ∆t the QZE will be invoked, thus hindering the qubit from propagating. At some optimal ∆t the anti-Zeno effect will push the qubit forward [See Fig. 3a], providing a speedup of about 12% with respect to the free propagation speed. A constant qubit-rate for schemes 2 & 3 could also be achieved by allowing to move the right boundary of each block, as in scheme 1. These three schemes exploit the fact that the block boundaries act as potential barriers and the qubit propagates as a free particle in the lattice. Combinations of these schemes can provide a variety of performance vs. control tradeoffs and thus can be adapted to meet different demands depending on the particular requirements and limitations of a given physical implementation. It is worth noticing that schemes 2 & 3, which use large blocks perform significantly faster than scheme 1. The reason for this is that in scheme 1, the qubit is prevented from advancing too fast since it is constrained to a size-2 block.”;)
performance of the one or more quantum walks on the second QPU comprises propagation of at least a portion of the second plurality of physical qubits across the second plurality of nodes of the second graphical structure responsive to one or more inputs from the evolution operators.
(Monras [fig(s) 1-2, 4] [fig(s) 7] “LET one qubit propagate freely between site 2” [sec(s) III] “The natural evolution under the Hamiltonian HC corresponds to a delocalization of the qubit, by a continuous time quantum walk [12, 13] with Dirichlet boundary conditions <0|ρ|0> = <n + 1|ρ|n + 1> = 0, while preserving its internal state. The position of the qubit can be localized on-demand by simply measuring Lˆ. Moreover, if Lˆ is performed continuously, the time evolution is frozen and delocalization is prevented [see Fig 1b].” [sec(s) IV] “In this scheme, the qubit evolves as a continuous time quantum walk driven by the QZE, namely, by measuring the appropriate sites the space where the walk takes place can be dynamically changed. … Scheme 3, “compressing” [see Fig 1d]: assume the qubit is encoded in site 1 (left) which needs to be transferred to site n (right). … For large ∆t the qubit will propagate freely along the chain. For small ∆t the QZE will be invoked, thus hindering the qubit from propagating. At some optimal ∆t the anti-Zeno effect will push the qubit forward [See Fig. 3a], providing a speedup of about 12% with respect to the free propagation speed. A constant qubit-rate for schemes 2 & 3 could also be achieved by allowing to move the right boundary of each block, as in scheme 1. These three schemes exploit the fact that the block boundaries act as potential barriers and the qubit propagates as a free particle in the lattice. Combinations of these schemes can provide a variety of performance vs. control tradeoffs and thus can be adapted to meet different demands depending on the particular requirements and limitations of a given physical implementation. It is worth noticing that schemes 2 & 3, which use large blocks perform significantly faster than scheme 1. The reason for this is that in scheme 1, the qubit is prevented from advancing too fast since it is constrained to a size-2 block.”;)
The combination of Andrés-Martínez, Monras is combinable with Monras for the same rationale as set forth above with respect to claim 1.
Claim(s) 2-3, 6-8, 14-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Andrés-Martínez et al. (Automated distribution of quantum circuits via hypergraph partitioning) in view of Monras et al. (Quantum Information Processing with Quantum Zeno Many-Body Dynamics) in view of Tamascelli et al. (INTERACTING QUANTUM WALKS)
Regarding claim 2
The combination of Andrés-Martínez, Monras teaches claim 1.
However, the combination of Andrés-Martínez, Monras does not appear to explicitly teach:
wherein at least a portion of the first plurality of physical qubits are synchronization qubits configured to determine if the one or more quantum walks performed by the first QPU are in sync.
Tamascelli teaches
wherein at least a portion of the first plurality of physical qubits are synchronization qubits configured to determine if the one or more quantum walks performed by the first QPU are in sync.
(Tamascelli [sec(s) 3.4] “When defining the CµNOT circuit (section 2.3) we made massive use of delay lines, that is edges of the clocking device “during which” the state of the register does not change. As we said in there, this allows for every computational path to be of the same length 1; in turn, this makes it possible the interference between different computational paths corresponding to different conditions of the controlling qubits to happen. As an example of the role of synchronization in our interacting quantum walks, let us consider the following Hamiltonians.” [sec(s) 3.2] “this is an example of a conditional jump in the quantum walk performed by the cursor: it acts non trivially only in the eigenspace belonging to the eigenvalue +1 of ρ3, enabling the transition |Q = s> → |Q = s + 1>.” [sec(s) 3.3] “As a final remark of this section, we observe that, acting in effect as a Stern-Gerlach apparatus providing space separation between two different spin states, the term
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(3.20) can be used also to model the preparation (“putting the data in”) of a register qubit in a given spin state.” [sec(s) 2.1] “The oracle A performs a quantum reversible computation of the indicator function of a by flipping the component 3 of the output qubit σ(ν) iff the word a is written on the register in terms of the σ(1), σ(2), . . . , σ(µ) components of the input qubits.” [sec(s) 2.2] “For every non negative integer K, we wish to show a quantum clocking mechanism able to apply 2K times the transformation BA to the register qubits σ(1), σ(2). . . , σ(ν), by repeatedly using the same “piece of hardware” that applies BA just once. We will show that this clocking mechanism will involve s(K) = 4K + 3 (2.21) cursor qubits τ(1), τ(2). . . , τ(s(K))”;)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Andrés-Martínez, Monras with the synchronized quantum walks of Tamascelli.
One of ordinary skill in the art would have been motived to combine in order to provide exponentially shorter propagation between a particular pair of nodes than the analogous propagation time needed by a classical walker, and reduce the complexity of the physical implementation for an algorithm on a Feynman computer.
(Tamascelli [sec(s) 1.2] “It is thus natural to ask whether quantum walks might be useful for quantum computation. In [21], for example, it is shown that there are graphs for which the time for a quantum walker to propagate between a particular pair of nodes is exponentially shorter than the analogous propagation time needed by a classical walker.” [sec(s) 2.3] “The iteration of quantum subroutines mechanism provides thus a way to reduce the space complexity of an algorithm; this, in turn, reduces the complexity of the physical implementation of the Grover algorithm on a Feynman computer. In the next section we address the problem of further simplify the implementation of quantum functional blocks.”)
Regarding claim 3
The combination of Andrés-Martínez, Monras, Tamascelli teaches claim 2.
Tamascelli further teaches
wherein the synchronization qubits are independent of the physical qubits propagating across the local nodes performing the one more quantum walks.
(Tamascelli [sec(s) 1.2] “In [21], for example, it is shown that there are graphs for which the time for a quantum walker to propagate between a particular pair of nodes is exponentially shorter than the analogous propagation time needed by a classical walker.” [sec(s) 3.4] “When defining the CµNOT circuit (section 2.3) we made massive use of delay lines, that is edges of the clocking device “during which” the state of the register does not change. As we said in there, this allows for every computational path to be of the same length 1; in turn, this makes it possible the interference between different computational paths corresponding to different conditions of the controlling qubits to happen. As an example of the role of synchronization in our interacting quantum walks, let us consider the following Hamiltonians.” [sec(s) 3.2] “this is an example of a conditional jump in the quantum walk performed by the cursor: it acts non trivially only in the eigenspace belonging to the eigenvalue +1 of ρ3, enabling the transition |Q = s> → |Q = s + 1>.” [sec(s) 3.3] “As a final remark of this section, we observe that, acting in effect as a Stern-Gerlach apparatus providing space separation between two different spin states, the term
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(3.20) can be used also to model the preparation (“putting the data in”) of a register qubit in a given spin state.” [sec(s) 2.1] “The oracle A performs a quantum reversible computation of the indicator function of a by flipping the component 3 of the output qubit σ(ν) iff the word a is written on the register in terms of the σ(1), σ(2), . . . , σ(µ) components of the input qubits.” [sec(s) 2.2] “For every non negative integer K, we wish to show a quantum clocking mechanism able to apply 2K times the transformation BA to the register qubits σ(1), σ(2). . . , σ(ν), by repeatedly using the same “piece of hardware” that applies BA just once. We will show that this clocking mechanism will involve s(K) = 4K + 3 (2.21) cursor qubits τ(1), τ(2). . . , τ(s(K))”;)
The combination of Andrés-Martínez, Monras, Tamascelli is combinable with Tamascelli for the same rationale as set forth above with respect to claim 2.
Regarding claim 6
The combination of Andrés-Martínez, Monras teaches claim 4.
However, the combination of Andrés-Martínez, Monras does not appear to explicitly teach:
at least a portion of the second plurality of physical qubits of the second QPU are synchronization qubits; and
the synchronization qubits of the first QPU and the synchronization qubits of the second QPU are further configured to determine if the one or more quantum walks performed by the first QPU and the one or more quantum walks performed by the second QPU are in sync.
Tamascelli teaches
at least a portion of the second plurality of physical qubits of the second QPU are synchronization qubits; and
(Tamascelli [sec(s) 1.2] “In [21], for example, it is shown that there are graphs for which the time for a quantum walker to propagate between a particular pair of nodes is exponentially shorter than the analogous propagation time needed by a classical walker.” [sec(s) 3.4] “When defining the CµNOT circuit (section 2.3) we made massive use of delay lines, that is edges of the clocking device “during which” the state of the register does not change. As we said in there, this allows for every computational path to be of the same length 1; in turn, this makes it possible the interference between different computational paths corresponding to different conditions of the controlling qubits to happen. As an example of the role of synchronization in our interacting quantum walks, let us consider the following Hamiltonians.” [sec(s) 3.2] “this is an example of a conditional jump in the quantum walk performed by the cursor: it acts non trivially only in the eigenspace belonging to the eigenvalue +1 of ρ3, enabling the transition |Q = s> → |Q = s + 1>.” [sec(s) 3.3] “As a final remark of this section, we observe that, acting in effect as a Stern-Gerlach apparatus providing space separation between two different spin states, the term
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(3.20) can be used also to model the preparation (“putting the data in”) of a register qubit in a given spin state.” [sec(s) 2.1] “The oracle A performs a quantum reversible computation of the indicator function of a by flipping the component 3 of the output qubit σ(ν) iff the word a is written on the register in terms of the σ(1), σ(2), . . . , σ(µ) components of the input qubits.” [sec(s) 2.2] “For every non negative integer K, we wish to show a quantum clocking mechanism able to apply 2K times the transformation BA to the register qubits σ(1), σ(2). . . , σ(ν), by repeatedly using the same “piece of hardware” that applies BA just once. We will show that this clocking mechanism will involve s(K) = 4K + 3 (2.21) cursor qubits τ(1), τ(2). . . , τ(s(K))”;)
the synchronization qubits of the first QPU and the synchronization qubits of the second QPU are further configured to determine if the one or more quantum walks performed by the first QPU and the one or more quantum walks performed by the second QPU are in sync.
(Tamascelli [fig(s) 3.6-3.7] [fig(s) 3.10] “The same SWITCH of figure 3.8. The vertical dashed lines divide the circuit in slices, or levels” [sec(s) 1.2] “In [21], for example, it is shown that there are graphs for which the time for a quantum walker to propagate between a particular pair of nodes is exponentially shorter than the analogous propagation time needed by a classical walker.” [sec(s) 3.4] “When defining the CµNOT circuit (section 2.3) we made massive use of delay lines, that is edges of the clocking device “during which” the state of the register does not change. As we said in there, this allows for every computational path to be of the same length 1; in turn, this makes it possible the interference between different computational paths corresponding to different conditions of the controlling qubits to happen. As an example of the role of synchronization in our interacting quantum walks, let us consider the following Hamiltonians.” [sec(s) 3.2] “this is an example of a conditional jump in the quantum walk performed by the cursor: it acts non trivially only in the eigenspace belonging to the eigenvalue +1 of ρ3, enabling the transition |Q = s> → |Q = s + 1>.” [sec(s) 3.3] “As a final remark of this section, we observe that, acting in effect as a Stern-Gerlach apparatus providing space separation between two different spin states, the term
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(3.20) can be used also to model the preparation (“putting the data in”) of a register qubit in a given spin state.” [sec(s) 2.1] “The oracle A performs a quantum reversible computation of the indicator function of a by flipping the component 3 of the output qubit σ(ν) iff the word a is written on the register in terms of the σ(1), σ(2), . . . , σ(µ) components of the input qubits.” [sec(s) 2.2] “For every non negative integer K, we wish to show a quantum clocking mechanism able to apply 2K times the transformation BA to the register qubits σ(1), σ(2). . . , σ(ν), by repeatedly using the same “piece of hardware” that applies BA just once. We will show that this clocking mechanism will involve s(K) = 4K + 3 (2.21) cursor qubits τ(1), τ(2). . . , τ(s(K))”; e.g., “divide the circuit” read(s) on “first QPU” and “second QPU”.)
The combination of Andrés-Martínez, Monras is combinable with Tamascelli for the same rationale as set forth above with respect to claim 2.
Regarding claim 7
The combination of Andrés-Martínez, Monras teaches claim 6.
Andrés-Martínez further teaches
wherein a portion of the first plurality of nodes of the first QPU are global nodes, and wherein a portion of the second plurality of nodes of the second QPU are global nodes, wherein the global nodes of the first QPU are configured to perform the one or more quantum walks in conjunction with the global nodes of the second QPU.
(Andrés-Martínez [fig(s) 2] “Implementation, as in [30], of a group of nonlocal CZ gates that share a common qubit. Circuit a) is the original circuit, b) is the distributed version. The dashed line indicates how the circuit is separated into two QPUs. The bent wire on the left of b) represents an ebit. The measurement outcomes are communicated through a classical network.” [sec(s) II] “This section describes the essential characteristics of any distributed architecture and identifies communication across QPUs as the main bottleneck. We then detail the problem at hand and discuss related work from the literature. Finally, we describe the standard way nonlocal multi-qubit gates are executed across QPUs, which will be required when building distributed circuits. … We use an approach pioneered by Gottesman and Chuang [31] to implement multi-qubit gates across distant qubits using entangled mutipartite states and measurements. In particular, we will use the scheme proposed in [30] which, using a single ebit, implements any number of contiguous nonlocal CZ gates that act on a common qubit, as shown in Figure 2. To do so, a so-called cat-entangler first shares the state of the common qubit with the remote QPU, which requires the use of an ebit; then, the CZ gates are locally performed on the remote QPU and finally the cat-disentangler destructively measures the remaining ebit half to remove any residual entanglement.” [sec(s) IV] “Our algorithm was evaluated on five quantum circuits provided by Quipper’s library [39]. These circuits implement algorithms that have been discussed in the literature as examples where quantum computers achieve computational speedup. Their default configuration was used unless stated otherwise: • Boolean formula (BF) [41]: the circuit fragment implementing the quantum walk, the core of the algorithm; • Binary welded tree (BWT) [42]: tree height set to 200 (from 5 by default);”; e.g., nodes used for communication between the two QPUs read(s) on “global nodes”.)
Regarding claim 8
The combination of Andrés-Martínez, Monras teaches claim 7.
Andrés-Martínez further teaches
wherein at least a portion of the first plurality of physical qubits of the first QPU and at least a portion of the second plurality of physical qubits of the second QPU are entangled.
(Andrés-Martínez [fig(s) 2] “Implementation, as in [30], of a group of nonlocal CZ gates that share a common qubit. Circuit a) is the original circuit, b) is the distributed version. The dashed line indicates how the circuit is separated into two QPUs. The bent wire on the left of b) represents an ebit. The measurement outcomes are communicated through a classical network.” [fig(s) 3] “Initially, a pair of ebits (bent wires) entangle QPU A with C and QPU B with C.” [sec(s) II] “This section describes the essential characteristics of any distributed architecture and identifies communication across QPUs as the main bottleneck. We then detail the problem at hand and discuss related work from the literature. Finally, we describe the standard way nonlocal multi-qubit gates are executed across QPUs, which will be required when building distributed circuits. … An ebit is a maximally entangled bipartite quantum state shared across two QPUs. … We use an approach pioneered by Gottesman and Chuang [31] to implement multi-qubit gates across distant qubits using entangled mutipartite states and measurements. In particular, we will use the scheme proposed in [30] which, using a single ebit, implements any number of contiguous nonlocal CZ gates that act on a common qubit, as shown in Figure 2. To do so, a so-called cat-entangler first shares the state of the common qubit with the remote QPU, which requires the use of an ebit; then, the CZ gates are locally performed on the remote QPU and finally the cat-disentangler destructively measures the remaining ebit half to remove any residual entanglement.”;)
Regarding claim 14
The claim is a method claim corresponding to a combination of the apparatus claims 2 and 6, and is directed to largely the same subject matter. Thus, it is rejected for the same reasons as given in the rejections of the combination of the apparatus claims.
Regarding claim 15
The claim is a method claim corresponding to the apparatus claim 7, and is directed to largely the same subject matter. Thus, it is rejected for the same reasons as given in the rejections of the apparatus claim.
Regarding claim 16
The claim is a method claim corresponding to the apparatus claim 8, and is directed to largely the same subject matter. Thus, it is rejected for the same reasons as given in the rejections of the apparatus claim.
Regarding claim 17
The combination of Andrés-Martínez, Monras, Tamascelli teaches claim 14.
Andrés-Martínez further teaches
in an instance in which the one or more quantum walks performed by the first QPU and the one or more quantum walks performed by the second QPU are in [sync], further comprising receiving data generated by the one or more quantum walks performed by the first QPU and the second QPU.
(Andrés-Martínez [fig(s) 2] “The measurement outcomes are communicated through a classical network.” [fig(s) 3] [sec(s) II.A] “A classical communication network that the QPUs may send classical messages through when measuring their qubits and receive message over when applying corrections. … Moreover, while they assume the cost of classical communication to be negligible, the authors estimate that the generation of ebits will be roughly 300 times more costly than the application of a two-qubit gate locally within a QPU.” [sec(s) II] “This section describes the essential characteristics of any distributed architecture and identifies communication across QPUs as the main bottleneck. We then detail the problem at hand and discuss related work from the literature. Finally, we describe the standard way nonlocal multi-qubit gates are executed across QPUs, which will be required when building distributed circuits.” [sec(s) IV] “Their default configuration was used unless stated otherwise: • Boolean formula (BF) [41]: the circuit fragment implementing the quantum walk, the core of the algorithm; • Binary welded tree (BWT) [42]: tree height set to 200 (from 5 by default); … The times shown in the table indicate how long it took to obtain the distributed circuit using our implementation (available at [40]), running it on a standard desktop computer.” [sec(s) V] “that problem is intractable on a classical computer (namely, it is NP-hard [45]). Instead, we work with close to optimal solutions that can be found efficiently by classical computers. The results discussed in Section IV were obtained using such suboptimal partitions.”;)
Tamascelli further teaches
in an instance in which the one or more quantum walks performed by the first QPU and the one or more quantum walks performed by the second QPU are in sync, further comprising receiving data generated by the one or more quantum walks performed by the first QPU and the second QPU.
(Tamascelli [fig(s) 3.6-3.7] [fig(s) 3.10] “The same SWITCH of figure 3.8. The vertical dashed lines divide the circuit in slices, or levels” [sec(s) 1.2] “In [21], for example, it is shown that there are graphs for which the time for a quantum walker to propagate between a particular pair of nodes is exponentially shorter than the analogous propagation time needed by a classical walker.” [sec(s) 3.4] “When defining the CµNOT circuit (section 2.3) we made massive use of delay lines, that is edges of the clocking device “during which” the state of the register does not change. As we said in there, this allows for every computational path to be of the same length 1; in turn, this makes it possible the interference between different computational paths corresponding to different conditions of the controlling qubits to happen. As an example of the role of synchronization in our interacting quantum walks, let us consider the following Hamiltonians.” [sec(s) 3.2] “this is an example of a conditional jump in the quantum walk performed by the cursor: it acts non trivially only in the eigenspace belonging to the eigenvalue +1 of ρ3, enabling the transition |Q = s> → |Q = s + 1>.” [sec(s) 3.3] “As a final remark of this section, we observe that, acting in effect as a Stern-Gerlach apparatus providing space separation between two different spin states, the term
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(3.20) can be used also to model the preparation (“putting the data in”) of a register qubit in a given spin state.” [sec(s) 2.1] “The oracle A performs a quantum reversible computation of the indicator function of a by flipping the component 3 of the output qubit σ(ν) iff the word a is written on the register in terms of the σ(1), σ(2), . . . , σ(µ) components of the input qubits.” [sec(s) 2.2] “For every non negative integer K, we wish to show a quantum clocking mechanism able to apply 2K times the transformation BA to the register qubits σ(1), σ(2). . . , σ(ν), by repeatedly using the same “piece of hardware” that applies BA just once. We will show that this clocking mechanism will involve s(K) = 4K + 3 (2.21) cursor qubits τ(1), τ(2). . . , τ(s(K))”; e.g., “divide the circuit” read(s) on “first QPU” and “second QPU”.)
The combination of Andrés-Martínez, Monras, Tamascelli is combinable with Tamascelli for the same rationale as set forth above with respect to claim 2.
Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Perelshtein et al. (Practical Application-Specific Advantage through Hybrid Quantum Computing) teaches communications between a classical computer and QPUs.
Esposito et al. (Quantum walks of two correlated photons in a 2D synthetic lattice) teaches quantum walks.
Conclusion
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