DETAILED ACTION
This Office Action is in response to Applicant’s Remarks filed on 02/05/2026.
Currently, claims 1-9 and 11-20 are pending in the application. Currently, claims 3, 7-9, and 11-20 are withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Applicant has amended claim 1 to further include the formation of a high-k dielectric layer. Applicant argues that the high-k dielectric layer is formed only in the trenches within the pixel region while its use is avoided in the plug structures of the pad region and that Lai does not involve the pad region or electrical connection schemes. However, as written, claim 1 does not require a pad region, plug structures, nor an electrical connection scheme. Applicant also argues that the added feature integrates the high-k dielectric layer with a specific functional benefit of reducing dark current and improving signal to noise ratio, and that Lai does not disclose or suggest the combination of functional benefits. However, as written, claim 1 does not claim require the high-k dielectric layer to reduce dark current nor improve signal to noise ratio. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, and 4 are rejected under 35 U.S.C. 103 as being obvious over ZANG et al. (US Pub. No. 2021/0305440) in view of LI et al. (US Pub. No. 2019/0259797) and further in view of LAI et al. (US Pub. No. 2017/0062496).
Regarding independent claim 1, Zang teaches a method of manufacturing a semiconductor device (Figs. 5 & 21), comprising:
providing a substrate (Fig. 5, 8, ¶ [0075]) with a pixel region;
forming a trench fill structure (Fig. 5, 3, ¶ [0077]) in the pixel region (¶ [0075] teaches that Fig. 5 is a cross section view of a back side illuminated single photon avalanche diode) of the substrate by forming a trench in the pixel region of the substrate and filling the fill material in the trench (Fig. 21);
covering a backside (Fig. 5, top of 8) of the substrate in the pixel region with a buffer dielectric layer (Figs. 5 & 21, 13, ¶ [0079]) so that the trench fill structure is embedded under the buffer dielectric layer (Figs. 5 & 21 teaches that the protective layer 13 is formed over Zang’s filled cavity 3);
etching the buffer dielectric layer to form a first opening exposing at least part of the substrate around a top side wall portion of the trench fill structure (Fig. 21 teaches that in the method of manufacturing Zang’s device, the protective layer 13 is formed over Zang’s filled cavity and Zang’s substrate. Zang teaches a metal layer made of the same material as the filled cavity (layer A in annotated figure below. ¶ [0077] teaches that 3 can be metal) over the filled cavity and on the same layer as the protective layer 13. Therefore, a portion of the protective layer 13 that exposes the top of the filled cavity 3 and the substrate 8 around the top side wall portion is removed after the manufacturing steps of Fig. 21), or exposing both of at least part of the substrate around a top side wall portion of the trench fill structure and at least a top portion of the trench fill structure;
filling a first conductive metal layer (layer A in annotated figure below. Zang teaches a layer made of the same material as the filled cavity 3 over the filled cavity. ¶ [0077] teaches that 3 can be metal) in the first opening in the buffer dielectric layer in the pixel region so that the first conductive metal layer is electrically connected to the exposed part of the substrate (Fig. 5), or the first conductive metal layer is electrically connected to both of the exposed part of the substrate and the exposed portion of the trench fill structure.
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However, Zang does not explicitly teach forming a metal grid layer on the buffer dielectric layer in the pixel region so that the metal grid layer is electrically connected to the first conductive metal layer, and forming a high-k dielectric layer sandwiched between a side wall of the filling material in the trench in the pixel region and the substrate.
However, Li is a pertinent art that teaches forming a metal grid layer (Fig. 16, 526, ¶ [0063]) on the buffer dielectric layer (Fig. 16, 206, ¶ [0027]) so that the metal grid layer is electrically connected to the first conductive metal layer (Fig. 16, 126, ¶ [0028]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zang’s method to further comprise forming a metal grid layer according to the teaching of Li (Fig. 16) in order to connect the metal in the trench to a bias source and thus improve image sensor performance (Li ¶¶ [0048] & [0030]).
However, Zang modified by Li does not explicitly teach forming a high-k dielectric layer sandwiched between a side wall of the filling material in the trench in the pixel region and the substrate.
However, Lai is a pertinent art that teaches forming a high-k dielectric layer (Fig. 7, 128B, ¶ [0027]) sandwiched between a side wall of the filling material (Fig. 12, 142B, ¶ [0032]) in the trench in the pixel region and the substrate (Fig. 2, 102, ¶ [0015]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zang modified by Li’s method of manufacturing according to the teaching of Lai (Figs. 2-13A) in order to improve electrical function by increasing signal to noise ratio and reducing dark current degradation (Lai ¶ [0008]).
Regarding claim 2, Zang modified by Li modified by Lai teaches the method of claim 1.
And Lai teaches the step of forming the trench fill structure in the pixel region of the substrate comprises:
covering the backside of the substrate (Fig. 2, top surface of 102, ¶ [0015]) in the pixel region with a pad oxide layer (Fig. 2, 114, ¶ [0015]);
forming a first patterned photoresist layer (Fig. 2, 118, ¶ [0015]) on the pad oxide layer and, with the first patterned photoresist layer serving as a mask, etching through the pad oxide layer (Fig. 2, 120, ¶ [0017]) and at least a partial thickness of the substrate, thereby forming a trench (Fig. 3, 122, ¶ [0018]) in the pixel region of the substrate;
removing the first patterned photoresist layer and the pad oxide layer (Fig. 4, ¶ [0021]);
successively forming a first isolating oxide layer (Fig. 7, 128A, ¶ [0023]), a high-k dielectric layer (Fig. 7, 128B, ¶ [0027]) and a second isolating oxide layer (Fig. 10, 140, ¶ [0031]) both in the trench and on the backside of the substrate;
filling the fill material (Fig. 12, 142B, ¶ [0032]) in the trench in such a manner that the fill material also covers the second isolating oxide layer outside the trench; and
performing an etching or chemical mechanical polishing process to remove the fill material, the second isolating oxide layer, the high-k dielectric layer and the first isolating oxide layer above the backside of the substrate outside the trench, or to remove only the fill material above the backside of the substrate outside the trench (Fig. 12A, ¶ [0032]), thereby forming the trench fill structure in the trench.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zang modified by Li’s method according to the teaching of Lai (Figs. 2-13A) in order to improve electrical function (Lai ¶ [0008]).
Regarding claim 4, Zang modified by Li modified by Lai teaches the method of claim 1.
However, as it is not pertinent to the particulars of their invention, Zang does not explicitly teach that the step of forming the first opening by etching the buffer dielectric layer comprises:
forming a second patterned photoresist layer on the buffer dielectric layer and, with the second patterned photoresist layer serving as a mask, etching the buffer dielectric layer, thereby forming the first opening in the buffer dielectric layer in the pixel region, the first opening exposing at least part of the substrate around a top side wall portion of the trench fill structure and/or at least a top portion of the trench fill structure; and
removing the second patterned photoresist layer (the Examiner notes that Zang does teach removing a portion of the protective layer and forming a layer in the area previously occupied by the protective layer).
However, Li teaches the step of forming the first opening (Fig. 15, area occupied by 214, ¶ [0030]) by etching the buffer dielectric layer (Fig. 15, 206, ¶ [0027]) comprises:
forming a second patterned photoresist layer (Fig. 15, 1502, ¶ [0062]) on the buffer dielectric layer and, with the second patterned photoresist layer serving as a mask, etching the buffer dielectric layer (¶ [0062]), thereby forming the first opening in the buffer dielectric layer in the pixel region, the first opening exposing at least part of the substrate around a top side wall portion of the trench fill structure and/or at least a top portion of the trench fill structure (Zang modified by Li would fulfill this limitation); and
removing the second patterned photoresist layer (Fig. 16, no patterned masking layer 1502 remains after the processing step of Fig. 15).
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that Zang’s method does further comprise the step of photolithography in a similar manner to Li in order to reduce manufacturing costs.
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being obvious over ZANG et al. (US Pub. No. 2021/0305440) in view of LI et al. (US Pub. No. 2019/0259797) and further in view of LAI et al. (US Pub. No. 2017/0062496) and further in view of YANG (US Pub. No. 2024/0379566).
Regarding claim 5, Zang modified by Li modified by Lai teaches the method of claim 1.
However, as it is not pertinent to the particulars of their invention, Zang modified by Li does not explicitly teach that the step of filling the first conductive metal layer in the first opening comprises:
forming the first conductive metal layer so that it covers the buffer dielectric layer and fills up the first opening; and
performing an etching or chemical mechanical polishing process to remove the first conductive metal layer over the substrate, with the first conductive metal layer in the first opening being retained, which is electrically connected to the exposed part of the substrate and/or the exposed portion of the trench fill structure.
However, Yang is a pertinent art that teaches forming the first conductive metal layer (Fig. 9e, 28, ¶ [0081]) so that it covers the buffer dielectric layer (Fig. 9e, 24, ¶ [0078]) and fills up the first opening (Fig. 9e, openings in 24 occupied by 28) ; and
performing an etching or chemical mechanical polishing process to remove the first conductive metal layer (Fig. 9f, ¶ [0083]) over the substrate, with the first conductive metal layer in the first opening being retained, which is electrically connected to the exposed part of the substrate and/or the exposed portion of the trench fill structure.
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that Zang modified by Li’s method does further comprise the step of depositing metal and patterning it in a similar manner to Yang in order to reduce manufacturing costs.
Regarding claim 6, Zang modified by Li modified by Lai teaches the method of claim 1, and Zang modified by Li modified by Lai teaches that the step of forming the metal grid layer (Li Fig. 16, 526, ¶ [0063]) on the buffer dielectric layer (Li Fig. 16, 206, ¶ [0063]) comprises: forming a third conductive metal layer on the buffer dielectric layer (Li ¶ [0063] teaches forming a metal over dielectric 206. However, Li does not explicitly teach the specific kind of metal. However, it would be obvious to select a metal such as copper, aluminum, or tungsten for a conductive routing layer (Li Fig. 15, 214, ¶ [0062] teaches using copper for a conductive layer). It would be obvious to select copper depending on relative material costs), which is made of a material that is different from a material of the first conductive metal layer (Zang Fig. 11, 140F, ¶¶ [0081] & [0085] teaches that 140F is tungsten), so that the first conductive metal layer is buried under the third conductive metal layer;
However, as it is not pertinent to the particulars of their invention, Zang modified by Li modified by Lai does not explicitly teach forming a third patterned photoresist layer on the third conductive metal layer and, with the third patterned photoresist layer serving as a mask, etching the third conductive metal layer, thus forming the metal grid layer in the pixel region, which is electrically connected to the first conductive metal layer; and removing the third patterned photoresist layer.
However, Yang is a pertinent art that teaches forming a third patterned photoresist layer (Fig. 9l, 38, ¶ [0089]) on the third conductive metal layer (Fig. 9l, 36, ¶ [0088]) and, with the third patterned photoresist layer serving as a mask, etching the third conductive metal layer (Fig. 9m, ¶ [0090]), thus forming the metal grid layer in the pixel region, which is electrically connected to the first conductive metal layer (Zang modified by Li in view of Yang would fulfill this limitation ); and removing the third patterned photoresist layer (Fig. 9m, ¶ [0038]).
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that Zang modified by Li’s method does further comprise the step of patterning a metal using photoresist in a similar manner to Yang in order to reduce manufacturing costs.
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/R.P.S./
Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813