DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
Receipt is acknowledged of a request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e) and a submission, filed on 11/05/2025.
Response to Arguments
Applicant’s arguments with respect to claims rejected have been considered but are moot because the new ground of rejection does not rely on Schmidbauer et al. 6136709 applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-12 and are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. 20180277669 in view of Schmidbauer et al. 6136709.
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Regarding claim 1, figs. 1-12 of Cheng discloses a method of manufacturing a vacuum tunneling device, the method comprising:
forming a tunnelling device including a transistor (fig. 11) on a substrate 102;
forming an insulating interlayer 190 on the substrate such that the insulating interlayer has an opening (vias – par [0054]) exposing the tunneling device; and
performing a deposition process in a vacuum chamber (par [0054] - conductive metal may be deposited using, for example, deposition techniques including, but not limited to, CVD, PECVD, RFCVD, PVD, ALD, MLD, MBD, pulsed laser deposition, and/or LSMCD, sputtering – these deposition process uses a vacuum chamber) to form a sealing layer (conductive line and conductive metal) on the insulating interlayer such that the sealing layer fills an upper portion of the opening (see fig. 12).
Cheng does not disclose of that the deposition process is a gradient deposition process.
However, (13) Advantageously in accordance with the present invention, a seed layer deposition (small grain size, good nucleation) begins to form instantly as deposition begins. As the wafer begins to heat up (in accordance with a constant heating temperature of thermal surface or by a temperature gradient on thermal surface) and eventually reaches a set point (or target) temperature, for example, about 350 degrees Celsius, deposition of the metal continues forming contacts and a metal layer on top of a dielectric layer. Preferably, the contacts and metal lines are formed concurrently. As the temperature, increases warmer metal continues to be deposited on top of the smaller grain-sized metal deposited earlier. The warmer metal deposition advantageously provides improved planarization properties.
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(17) Referring to FIG. 4, wafer 201 is placed in a PVD chamber in accordance with the present invention. A metal 210 is deposited in vias 206 and on dielectric layer 202 by employing the one step process of the present invention. Alternately, a metal liner 207 may be deposited prior to metal 210 deposition. For example, liner 207 may include Ti/TiN, Ta, W or other materials. In accordance with the present invention. Wafer 201 is gradually heated from a "cold" temperature to a "hot" temperature during the deposition process. In accordance with one aspect of the present invention, the temperature of thermal surface 102 (FIG. 2) is adjusted (e.g., by changing the temperature of the thermal surface) to achieve optimal results for the given deposition process. During the heating process, metal 210 is deposited in trenches 204 (which may include vias 206 or other structures). Metal 210 is continuously deposited until open trenches 204 are filled and metal 210 covers top surfaces of dielectric layer 202. As described above, since the present invention provides a continuous deposition, oxides, for example, Al.sub.3 O.sub.2 in the case of Al deposition, do not have a chance to form between portions of metal 210. Also, since deposition times are reduced, the chances for the formation of undesirable compounds, for example TiAl.sub.3 in the case of Al deposition, are significantly reduced.
In view of such teaching, it would have been obvious to form a method of Cheng comprising a gradient deposition process such as taught by Schmidbauer as temperature gradient advantageously provides improved planarization properties.
Regarding claim 2, the resulting method would have been one wherein the gradient deposition process includes placing the substrate in a slanted orientation with respect to a source gas provider that is configured to provide a source gas for forming the sealing layer (as the source gas provider is keep in a chemically room and connected to through a pipe carry the gas to the chamber).
Regarding claim 4, par [0053] of Cheng discloses wherein forming the tunneling device and forming the insulating interlayer are performed in the vacuum chamber (par [0053] - ILD layer 190 can be deposited using deposition techniques including, but not limited to, CVD, PECVD – which has vacuum chamber).
Regarding claim 5, Cheng discloses wherein the sealing layer has a multi-layered structure including a plurality of layers sequentially stacked (conductive line and conductive metal).
Regarding claim 6, Cheng discloses wherein: a lowermost one of the plurality of layers included in the sealing layer and the resulting method would have been one that is formed by the gradient deposition process in the vacuum chamber, and other ones of the plurality of layers included in the sealing layer are formed by a vertical deposition process (conductive is vertical deposited into the via holes) in the vacuum chamber.
Regarding claim 7, Cheng discloses wherein: a lowermost one of the plurality of layers included in the sealing layer and the resulting method would have been one that is formed by the gradient deposition process in the vacuum chamber, and other ones of the plurality of layers included in the sealing layer are formed by a vertical deposition process in a normal chamber (room in which the processing take place is a type of normal chamber) that is not a vacuum chamber.
Regarding claim 8, figs. 1-12 of Cheng discloses a method of manufacturing a vacuum tunneling device, the method comprising:
forming a tunnelling device including a transistor (fig. 11) on a substrate 102;
forming an insulating interlayer 145 on the substrate such that the insulating interlayer has an opening (vias – par [0054]) exposing the tunneling device; and
performing a deposition process in a vacuum chamber (par [0054] - conductive metal may be deposited using, for example, deposition techniques including, but not limited to, CVD, PECVD, RFCVD, PVD, ALD, MLD, MBD, pulsed laser deposition, and/or LSMCD, sputtering – these deposition process uses a vacuum chamber) to form a sealing layer (conductive metal) on the insulating interlayer such that the sealing layer fills an upper portion of the opening (see fig. 12); and
further comprising forming an auxiliary layer (metal liner on top of conductive metal) on the insulating interlayer to at least partially cover a top end of the opening prior to forming the sealing layer, wherein the sealing layer is formed on the auxiliary layer and fills an upper portion of the opening at which the auxiliary layer is not formed.
Cheng does not disclose of that the deposition process is a gradient deposition process.
However, (13) Advantageously in accordance with the present invention, a seed layer deposition (small grain size, good nucleation) begins to form instantly as deposition begins. As the wafer begins to heat up (in accordance with a constant heating temperature of thermal surface or by a temperature gradient on thermal surface) and eventually reaches a set point (or target) temperature, for example, about 350 degrees Celsius, deposition of the metal continues forming contacts and a metal layer on top of a dielectric layer. Preferably, the contacts and metal lines are formed concurrently. As the temperature, increases warmer metal continues to be deposited on top of the smaller grain-sized metal deposited earlier. The warmer metal deposition advantageously provides improved planarization properties.
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(17) Referring to FIG. 4, wafer 201 is placed in a PVD chamber in accordance with the present invention. A metal 210 is deposited in vias 206 and on dielectric layer 202 by employing the one step process of the present invention. Alternately, a metal liner 207 may be deposited prior to metal 210 deposition. For example, liner 207 may include Ti/TiN, Ta, W or other materials. In accordance with the present invention. Wafer 201 is gradually heated from a "cold" temperature to a "hot" temperature during the deposition process. In accordance with one aspect of the present invention, the temperature of thermal surface 102 (FIG. 2) is adjusted (e.g., by changing the temperature of the thermal surface) to achieve optimal results for the given deposition process. During the heating process, metal 210 is deposited in trenches 204 (which may include vias 206 or other structures). Metal 210 is continuously deposited until open trenches 204 are filled and metal 210 covers top surfaces of dielectric layer 202. As described above, since the present invention provides a continuous deposition, oxides, for example, Al.sub.3 O.sub.2 in the case of Al deposition, do not have a chance to form between portions of metal 210. Also, since deposition times are reduced, the chances for the formation of undesirable compounds, for example TiAl.sub.3 in the case of Al deposition, are significantly reduced.
In view of such teaching, it would have been obvious to form a method of Cheng comprising a gradient deposition process such as taught by Schmidbauer as temperature gradient advantageously provides improved planarization properties.
Regarding claim 9, Cheng discloses wherein the auxiliary layer includes a monolayer material (metal liner is a singular which is mono).
Regarding claim 10, Cheng necessary discloses wherein the auxiliary layer is formed in a normal chamber (room where processing equipment is at is a normal chamber) and covers only a portion of a top end of the opening.
Regarding claim 11, Cheng discloses wherein the auxiliary layer is formed in the vacuum chamber (CVD, PECVD, RFCVD has vacuum chamber) and covers the entire top end of the opening.
Regarding claim 12, figs. 12 of Cheng discloses wherein: the tunneling device includes a gate electrode on the substrate and source and drain electrodes spaced apart from the gate electrode, the source and drain electrodes are spaced apart from each other, and a vacuum channel 210b/a is formed between the source and drain electrodes.
Claims 3 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng and Schmidbauer and MATSUSHITA et al. 20090184401 (MATSUSHITA).
Regarding claim 3, Cheng and Schmidbauer disclose claim 1, but do not disclose of wherein forming the tunneling device and forming the insulating interlayer are performed in a normal chamber that is not a vacuum chamber.
However, par [0119] of MATSUSHITA discloses that the temperature of the silicon substrate 1 is then set at 750.degree. C. or higher, and a 2.5-nm thick silicon oxide layer 64 is deposited on the silicon oxynitride layer 63 by HTO. By doing so, the tunnel insulating film 65 including the silicon oxide layer 62, the silicon oxynitride layer 63, and the silicon oxide layer 64 is formed as shown in FIGS. 23(e) and 23(f). The temperature of the silicon substrate 1 is then set at 950.degree. C., and the atmosphere in the chamber is changed to a N.sub.2 gas having a partial pressure of 760 Torr and an O.sub.2 gas having a partial pressure of 3 Torr.
Note vacuum is zero pressure.
As such it would have been obvious to form a method of Cheng and Schmidbauer comprising wherein forming the tunneling device and forming the insulating interlayer are performed in a normal chamber that is not a vacuum chamber as gases in chamber have pressure such as taught by MATSUSHITA.
Allowable Subject Matter
Claims 13-17 are allowed.
Claim 13 recites "a vacuum is formed in the remaining portion of the opening that is not filled by the sealing layer", this feature in combination with the other features of the claim, is not taught by the references of record.
Conclusion
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/VONGSAVANH SENGDARA/ Primary Examiner, Art Unit 2893