DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/7/2026 has been entered.
Response to Arguments
Specification Objections
Applicant has amended the specification at issue and the previous objections have therefore been withdrawn.
Claim Rejections – 35 USC 112
Applicant has amended the claims at issue and the previous rejections have therefore been withdrawn.
Claim Rejections – 35 USC 101
Applicant's arguments filed 7/7/2026 have been fully considered but they are not persuasive.
Applicant asserts the claims are similar to Example 38 of USPTO’s “Subject Matter Eligibility Examples: Abstract Ideas” in that they may be based on mathematical concepts but do not recite any of mathematical concepts of mathematical relationships, mathematical formulas or equations, or mathematical calculations.
Examiner respectfully disagrees. As described in the rejection, masking is understood as a mathematical calculation. Moreover, the reducing a number of computations of an operation is a consequence of the masking. Furthermore, performing an operation, or a reduced number of computations, on bitwise data is binary mathematical calculations. Therefore, mathematical concepts are recited in the claim and the limitations are not analogous to those in Example 38.
Applicant asserts the claims do not recite mental processes, wherein masking is a specific hardware-level operation performed by physical circuitry and not a mental process.
Examiner agrees for the reasons stated in the advisory action mailed 6/23/2026.
Applicant asserts the claims impose a meaningful limit on the claimed features such that the claims are more than a drafting effort designed to monopolize the claimed features cited by the Office and imposes a meaningful limit on the claimed features.
Examiner respectfully disagrees. The improvement is a result of the judicial exception alone, and is further discussed below. The judicial exception alone cannot provide the improvement. See MPEP 2106.05(a).
Applicant asserts the claims reflect an improvement in the functioning of a computer, or an improvement to another technologic or technical field by eliminating the structural bottleneck of repeated re-training and de-quantization/re-quantization cycles to compensate for accuracy loss by dynamically adjusting mantissa bit-width based on an allowable error range. The improvement improves processing speed and power efficiency by reducing a number of computations of the hardware accelerator. Moreover, one or more of the improvements are realized in the claimed features.
Examiner respectfully disagrees. The additional elements of “using a hardware accelerator” does not provide meaningful limits on practicing the judicial exception and is the equivalent of reciting “apply it” to the judicial exception. Moreover, the receiving limitation is mere data gathering. Thus, the improvement is a result of performing the judicial exception alone. The Examiner notes claims 13 and 24, and their dependents, do not recite a hardware accelerator.
Applicant asserts claim 31 recites receiving both floating point weight data and feature map data of a neural network layer and performing a neural network operation, which is not mere data gathering but an integral part of a specific technical mechanism that simultaneously minimizes accuracy loss and reduces computation complexity in neural network hardware.
Examiner respectfully disagrees. The “weight data” and “feature map data of a layer of a neural network” merely characterize the input data and the “neural network operation” is recited at a high level of generality without any detail of the operation, or include steps that meaningfully limit the method to a neural network operation. The limitations are merely generally linking the method to the technical field of neural networks rather than being an application of neural networks.
Prior Art Rejections
Applicant’s arguments, filed 7/7/2026, with respect to prior art rejections have been fully considered and are persuasive. The prior art rejections of claims 25-30 have been withdrawn.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-31 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding claim 1, at Step 1, the claim is directed to a processor-implemented method, which is a statutory category of invention (Process).
At Step 2A Prong 1, Examiner notes that the claims are directed towards an abstract idea. The claim language has been reproduced below:
A processor-implemented method, comprising: receiving, using a hardware accelerator, a plurality of pieces of input data expressed as floating point;
reducing, using the hardware accelerator, a number of computations of an operation to be performed by adjusting a bit-width of mantissa by performing masking on the mantissa of each piece of the input data based on a size of an exponent of each piece of the input data (mathematical calculation) and on an allowable error range (mathematical relationship);
and performing, using the hardware accelerator, an operation between the input data with the adjusted bit-width according to the reduced number of computations (mathematical calculation).
Masking, in the context of computing, is interpreted as its plain meaning to be a bitwise, or binary, operation and thus an abstract idea.
At Step 2A Prong 2, the additional elements are bolded above. The additional elements do not integrate the abstract ideas into a practical application because the computer elements, which are recited at a high level of generality, provide conventional computer functions that do not impose any meaningful limits on practicing the abstract ideas. See MPEP 2106.05(f). The limitation “receiving a plurality of pieces of input data” is an insignificant extra-solution activity of mere data gathering. The limitation “using a hardware accelerator” is merely the equivalent of reciting “apply it” to the judicial exception. Even when viewed in combination, these additional elements do not integrate the recited judicial exception into a practical application and the claim is directed to the judicial exception.
At Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception. As set forth in step 2A prong 2 analysis, the functions of data gathering is recognized by the courts as well-understood routine and conventional. See MPEP 2106.05(d)(II). Furthermore, the “hardware accelerator” is the equivalent of adding the words “apply it” to the judicial exception and are mere instructions to implement the abstract idea on a computer. Even when considered in combination, these additional elements represent mere instructions to apply an exception and insignificant extra-solution activity, which do not provide an inventive concept. The claim is not eligible.
Regarding claim 2, it is directed to the mathematical concept and/or mental process of “adjusting the bit-width of the mantissa in proportion to the size of the piece of the input data”.
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 3, it is directed to the mathematical concept and/or mental process of “comparing the piece of the input data to a threshold; and adjusting the bit-width of mantissa based on a result of the comparing”.
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 4, it is directed to the mathematical concept and/or mental process of “the threshold is determined based on the distribution of the plurality of pieces of the input data and the allowable error range.”
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 5, it is directed to the mathematical concept and/or mental process “determining a threshold corresponding to each of the plurality of pieces of the input data based on the distribution of the plurality of pieces of the input data”.
Under Step 2A Prong 2, the claim recites additional element “receiving a distribution of the plurality of pieces of the input data”. The additional element does not integrate the abstract ideas into a practical application because the receiving is an insignificant extra-solution activity of mere data gathering and does not impose any meaningful limits on practicing the abstract idea.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 6, it is directed to the mathematical concept and/or mental process of “controlling a position and a timing of an operator to which the input data with the adjusted bit-width is input.”.
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 7, it is directed to the mathematical concept and/or mental process of “determining a number of cycles of the operation performed by a preset number of operators based on the adjusted bit-width of each piece of the input data”.
Under Step 2A Prong 2, the claim recites additional element “inputting the input data with the adjusted bit-width to one or more of the operators based on the determined number of cycles”. The additional element does not integrate the abstract ideas into a practical application because the inputting is an insignificant extra-solution activity of selecting a particular data source or type of data to be manipulated and does not impose any meaningful limits on practicing the abstract idea.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 8, it is directed to the mathematical concept and/or mental process of “determining the number of cycles of the operation based on the adjusted bit-width of the mantissa of each piece of the input data and a number of bits processible by the one or more of the operators in a single cycle”.
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 9, under Step 2A Prong 2, the claim recites additional elements “a multiplier”, “a shifter”, and “an accumulator”. The additional elements do not integrate the abstract ideas into a practical application because the multiplier, shifter, and accumulator are recited at a high level of generality and do not impose any meaningful limits on practicing the abstract idea.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 10, it is directed to the mathematical concept and/or mental process of “determining a number of operators for performing the operation within a preset number of cycles of the operation based on the adjusted bit-width of the mantissa of each piece of the input data”.
Under Step 2A Prong 2, the claim recites additional element “inputting the input data with the adjusted bit-width to one or more of the operators based on the determined number of operators”. The additional element does not integrate the abstract ideas into a practical application because the inputting is an insignificant extra-solution activity of selecting a particular data source or type of data to be manipulated and does not impose any meaningful limits on practicing the abstract idea.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 11, it is directed to the mathematical concept and/or mental process of “determining the number of operators based on the adjusted bit-width of the mantissa of each piece of the input data and a number of bits processible by the one or more of the operators in a single cycle”.
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 12, it is directed to a non-transitory computer-readable medium of claim 1 and is therefore rejected for the same reasons.
Regarding claims 13-23, the claims are directed to an apparatus with the same or similar limitations as claims 1-11, respectively, and are therefore rejected for the same reasons.
Regarding claim 24, it is directed to an apparatus with the same or similar limitations as claim 5 and is therefore rejected for the same reasons.
Regarding claim 25, the claim is directed to a processor-implemented method with the same or similar limitations as claim 1 and is therefore rejected for the same reasons.
Regarding claim 26, it is directed to the mathematical concept and/or mental process of “allocating a smaller bit-width to the mantissa in response to the exponent being less than the threshold than in response to the exponent being greater than or equal to the threshold”.
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 27, it is directed to the mathematical concept and/or mental process of “performing of the operation comprises using an operator, and the adjusted bit-width of the mantissa is less than or equal to a number of bits processible by the operator in a single cycle”.
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 28, it is directed to the mathematical concept and/or mental process of “maintaining the bit-width of the mantissa in response to the exponent being greater than or equal to the threshold”.
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 29, it is directed to the mathematical concept and/or mental process of “the threshold comprises a plurality of threshold ranges each corresponding to a respective bit-width, and the adjusting of the bit-width of the mantissa comprises adjusting, in response to the input data corresponding to one of the threshold ranges, the bit-width of the mantissa to be the bit-width corresponding to the one of the threshold ranges”.
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 30, it is directed to the mathematical concept and/or mental process of “performing a multiply and accumulate operations using an operator”.
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 31, at Step 1, the claim is directed to a processor-implemented method, which is a statutory category of invention (Process).
At Step 2A Prong 1, Examiner notes that the claims are directed towards an abstract idea. The claim language has been reproduced below:
receiving, using a hardware accelerator, floating point weight data and floating point feature map data of a layer of a neural network;
reducing, using the hardware accelerator, a number of computations of a neural network operation to be performed by adjusting a mantissa bit-width of the weight data and a mantissa bit-width of the feature map data by respectively comparing a size of an exponent of the weight data to a threshold and a size of an exponent of the feature map data to another threshold (mathematical calculation), and based on an allowable error range (mathematical relationship);
and performing, using the hardware accelerator, the neural network operation between the floating point weight data and the floating point feature map data with the adjusted bit-widths according to the reduced number of computations (mathematical calculation).
At Step 2A Prong 2, the additional elements are bolded above. The additional elements do not integrate the abstract ideas into a practical application because the computer elements, which are recited at a high level of generality, provide conventional computer functions that do not impose any meaningful limits on practicing the abstract ideas. See MPEP 2106.05(f). The limitation “receiving floating point weight data…” is an insignificant extra-solution activity of mere data gathering. The limitation “using a hardware accelerator” is merely the equivalent of reciting “apply it” to the judicial exception. Even when viewed in combination, these additional elements do not integrate the recited judicial exception into a practical application and the claim is directed to the judicial exception.
At Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception. As set forth in step 2A prong 2 analysis, the functions of data gathering is recognized by the courts as well-understood routine and conventional. See MPEP 2106.05(d)(II). Furthermore, the “hardware accelerator” is the equivalent of adding the words “apply it” to the judicial exception and are mere instructions to implement the abstract idea on a computer. Even when considered in combination, these additional elements represent mere instructions to apply an exception and insignificant extra-solution activity, which do not provide an inventive concept. The claim is not eligible.
Conclusion
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/P.N.L./
Phat LeExaminer, Art Unit 2182 (571) 272-0546
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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