DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Specification Objections
Applicant has not amended the title at issue and the previous objection is therefore maintained. Applicant is reminded a complete response to this office action will include either arguments traversing the objection to the title or an amendment change in the title.
Claim Rejections – 35 USC 112
Applicant has amended claims 7-11, 19-23 at issue and the previous rejections have therefore been withdrawn.
Applicant has not amended claim 4 at issue and the previous rejection is therefore maintained. Applicant is reminded a complete response to this office action will include either arguments traversing the rejection or an amendment change in the claim.
Furthermore, 35 U.S.C. 112(a) rejections are introduced due to amendments.
Claim Rejections – 35 USC 101
Applicant's arguments filed 1/16/2026 have been fully considered but they are not persuasive.
Applicant asserts the claims do not recite mathematical concept abstract ideas as the limitations are based on mathematical concepts and not reciting mathematical concepts. Examiner respectfully disagrees. Adjusting the bit-width by performing masking is a mathematical process, or mental process performing mathematical steps, wherein “masking” is interpreted as a bitwise operation, which is a mathematical process. Additionally, “comparing a size of an exponent of the input data to a threshold” is a mathematical process or mental process, as it is merely an operation of comparing two values. Furthermore, the scope of “performing an operation”, in relation to floating point values, includes mathematical processes or mental processes.
Applicant asserts the claims do not recite mental processes because the human mind is not equipped to perform such complex operations. Examiner respectfully disagrees. As discussed above, adjusting the bit-width by performing masking is understood as a bitwise operation, which can be reasonably done in the human mind for 16-bit floating-point values, which are exemplary sizes for the input values as shown in applicant’s Fig. 5. Furthermore, the scope of “performing an operation” includes operations that can be reasonable performed in the human mind, such as applicant’s Fig. 7, and thus includes mental processes.
Applicant asserts the claims impose a meaningful limit on the claimed features such that the claims are more than a drafting effort designed to monopolize the claimed features. Examiner respectfully disagrees. Applicant’s assertion is conclusory, the 101 rejection is maintained for the reasons stated in this Office Action.
Applicant asserts the claims reflect an improvement to the technical fields of at least artificial intelligence, neural networks, and hardware processing by reducing loss of accuracy and improving computational performance. Examiner respectfully disagrees. The present independent claims only recite “receiving a plurality of pieces of input data” as an additional element, which is an insignificant extra-solution activity of data gathering. Thus, the additional element does not contribute significantly to the improvement, and therefore the improvement is a consequence of the judicial exception alone. However, the judicial exception alone cannot provide the improvement. See MPEP 2106.05(a).
Prior Art Rejections
Applicant’s arguments, filed 1/16/2026, with respect to 35 U.S.C. 103 have been fully considered and are persuasive. The prior art rejections of claims 1, 13, 24, 31 have been withdrawn. However, independent claim 25 has not been amended as such, and thus the prior art rejections of claims 25-30 are therefore maintained.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The current title does not reflect the dynamic, or mixed, precision mantissa adjusting. The following title is suggested: Method and Apparatus of Dynamic Mantissa Adjusting with Calculation.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 13 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The pertinent subject matter is “performing an operation between the input data with the adjusted bit-width on an allowable error range”. Applicant’s paragraph [0079] discloses quantization error, and paragraph [0100] discloses average error in relation to threshold combinations, which are threshold ranges corresponding to adjusting of the bit-width of the mantissa ([0033]). Thus, it seems applicant’s specification only describes an allowable error range in relation to the operation of adjusting a bit-width of mantissa, and is silent on an allowable error range in relation to performing an operation between the input data with the adjusted bit-width. The Examiner notes independent claims 24 and 31 do not have the discussed issue.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitation "the threshold". There is insufficient antecedent basis for this limitation in the claim as “a threshold is not declared in the parent claims, however the Examiner notes that “a threshold” is declared in claim 3.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-31 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding claim 1, at Step 1, the claim is directed to a processor-implemented method, which is a statutory category of invention (Process).
At Step 2A Prong 1, Examiner notes that the claims are directed towards an abstract idea. The claim language has been reproduced below:
A processor-implemented method, comprising: receiving a plurality of pieces of input data expressed as floating point;
adjusting a bit-width of mantissa by performing masking on the mantissa of each piece of the input data based on a size of an exponent of each piece of the input data (mathematical process or mental process);
and performing an operation between the input data with the adjusted bit-width (mathematical process or mental process) and on an allowable error range (mathematical relationship).
Masking, in the context of computing, is interpreted as its plain meaning to be a bitwise operation, and thus an abstract idea.
At Step 2A Prong 2, the additional elements are bolded above. The additional elements do not integrate the abstract ideas into a practical application because the computer elements, which are recited at a high level of generality, provide conventional computer functions that do not impose any meaningful limits on practicing the abstract ideas. See MPEP 2106.05(f). The limitation “receiving a plurality of pieces of input data” is an insignificant extra-solution activity of mere data gathering.
At Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception. As set forth in step 2A prong 2 analysis, the functions of mere data gathering is recognized by the courts as well-understood routine and conventional. See MPEP 2106.05(d)(II).
Regarding claim 2, it is directed to the mathematical concept and/or mental process of “adjusting the bit-width of the mantissa in proportion to the size of the piece of the input data”.
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 3, it is directed to the mathematical concept and/or mental process of “comparing the piece of the input data to a threshold; and adjusting the bit-width of mantissa based on a result of the comparing”.
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 4, it is directed to the mathematical concept and/or mental process of “the threshold is determined based on a distribution of the plurality of pieces of the input data and the allowable error range.”
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 5, it is directed to the mathematical concept and/or mental process “determining a threshold corresponding to each of the plurality of pieces of the input data based on the distribution of the plurality of pieces of the input data”.
Under Step 2A Prong 2, the claim recites additional element “receiving a distribution of the plurality of pieces of the input data”. The additional element does not integrate the abstract ideas into a practical application because the receiving is an insignificant extra-solution activity of mere data gathering and does not impose any meaningful limits on practicing the abstract idea.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 6, it is directed to the mathematical concept and/or mental process of “controlling a position and a timing of an operator to which the input data with the adjusted bit-width is input.”.
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 7, it is directed to the mathematical concept and/or mental process of “determining a number of cycles of the operation performed by a preset number of operators based on the adjusted bit-width of each piece of the input data”.
Under Step 2A Prong 2, the claim recites additional element “inputting the input data with the adjusted bit-width to one or more of the operators based on the determined number of cycles”. The additional element does not integrate the abstract ideas into a practical application because the inputting is an insignificant extra-solution activity of selecting a particular data source or type of data to be manipulated and does not impose any meaningful limits on practicing the abstract idea.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 8, it is directed to the mathematical concept and/or mental process of “determining the number of cycles of the operation based on the adjusted bit-width of the mantissa of each piece of the input data and a number of bits processible by the one or more of the operators in a single cycle”.
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 9, under Step 2A Prong 2, the claim recites additional elements “a multiplier”, “a shifter”, and “an accumulator”. The additional elements do not integrate the abstract ideas into a practical application because the multiplier, shifter, and accumulator are recited at a high level of generality and do not impose any meaningful limits on practicing the abstract idea.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 10, it is directed to the mathematical concept and/or mental process of “determining a number of operators for performing the operation within a preset number of cycles of the operation based on the adjusted bit-width of the mantissa of each piece of the input data”.
Under Step 2A Prong 2, the claim recites additional element “inputting the input data with the adjusted bit-width to one or more of the operators based on the determined number of operators”. The additional element does not integrate the abstract ideas into a practical application because the inputting is an insignificant extra-solution activity of selecting a particular data source or type of data to be manipulated and does not impose any meaningful limits on practicing the abstract idea.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 11, it is directed to the mathematical concept and/or mental process of “determining the number of operators based on the adjusted bit-width of the mantissa of each piece of the input data and a number of bits processible by the one or more of the operators in a single cycle”.
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claims 13-23, the claims are directed to an apparatus with the same or similar limitations as claims 1-11, respectively, and are therefore rejected for the same reasons.
Regarding claim 24, it is directed to an apparatus with the same or similar limitations as claim 5 and is therefore rejected for the same reasons.
Regarding claim 25, the claim is directed to a processor-implemented method with the same or similar limitations as claim 1 and is therefore rejected for the same reasons.
Regarding claim 26, it is directed to the mathematical concept and/or mental process of “allocating a smaller bit-width to the mantissa in response to the exponent being less than the threshold than in response to the exponent being greater than or equal to the threshold”.
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 27, it is directed to the mathematical concept and/or mental process of “performing of the operation comprises using an operator, and the adjusted bit-width of the mantissa is less than or equal to a number of bits processible by the operator in a single cycle”.
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 28, it is directed to the mathematical concept and/or mental process of “maintaining the bit-width of the mantissa in response to the exponent being greater than or equal to the threshold”.
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 29, it is directed to the mathematical concept and/or mental process of “the threshold comprises a plurality of threshold ranges each corresponding to a respective bit-width, and the adjusting of the bit-width of the mantissa comprises adjusting, in response to the input data corresponding to one of the threshold ranges, the bit-width of the mantissa to be the bit-width corresponding to the one of the threshold ranges”.
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 30, it is directed to the mathematical concept and/or mental process of “performing a multiply and accumulate operations using an operator”.
Under Step 2A Prong 2, the claim does not recite additional elements.
Under Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Regarding claim 31, at Step 1, the claim is directed to a processor-implemented method, which is a statutory category of invention (Process).
At Step 2A Prong 1, Examiner notes that the claims are directed towards an abstract idea [abstract idea, natural phenomenon, law of nature]. The claim language has been reproduced below:
receiving floating point weight data and floating point feature map data of a layer of a neural network;
adjusting a mantissa bit-width of the weight data and a mantissa bit-width of the feature map data by respectively comparing a size of an exponent of the weight data to a threshold and a size of an exponent of the feature map data to another threshold (mathematical process or mental process), and based on an allowable error range (mathematical relationship);
and performing a neural network operation between the floating point weight data and the floating point feature map data with the adjusted bit-widths (mathematical process or mental process).
At Step 2A Prong 2, the additional elements are bolded above. The additional elements do not integrate the abstract ideas into a practical application because the computer elements, which are recited at a high level of generality, provide conventional computer functions that do not impose any meaningful limits on practicing the abstract ideas. See MPEP 2106.05(f). The limitation “receiving floating point weight data…” is an insignificant extra-solution activity of mere data gathering.
At Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 25-26, 28-29 are rejected under 35 U.S.C. 103 as being unpatentable over DiCecco et al. (US 20200218508 A1, hereinafter “DiCecco”) in view of Wegener (US 20130007077 A1, hereinafter “Wegener”).
As per claim 25, DiCecco teaches A processor-implemented method, comprising: receiving a floating point input data (DiCecco: Fig. 4, element 402; [0030]); and performing an operation on the input data with the adjusted bit-width (DiCecco: Fig. 4 element 406; [0033]).
However, while DiCecco discloses controlling the precision (Fig. 4 element 408; [0032]), DiCecco does not explicitly disclose the process for determining the precision control. Thus, DiCecco does not teach adjusting a bit-width of mantissa by comparing a size of an exponent of the input data to a threshold.
Wegener teaches adjusting a bit-width of mantissa by comparing a size of an exponent of the input data to a threshold (Wegener: Fig. 20 element 656; [0103]; wherein the mapping of element 656 can consider each step as a threshold range).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the precision control circuitry of DiCecco with the floating-point compression circuitry of Wegener. One would have been motivated to combine these references because both references disclose reducing precision before performing computations, and Wegener teaches a computationally efficient compression of floating-point data ([0006]).
As per claim 26, DiCecco/Wegener further teaches The method of claim 25, wherein the adjusting of the bit-width of the mantissa comprises allocating a smaller bit-width to the mantissa in response to the exponent being less than the threshold than in response to the exponent being greater than or equal to the threshold (Wegener: Fig. 20 element 656; [0103]; wherein the mapping of element 656 can consider each step as a threshold range).
As per claim 28, DiCecco/Wegener further teaches The method of claim 25, wherein the adjusting of the bit-width of the mantissa comprises maintaining the bit-width of the mantissa in response to the exponent being greater than or equal to the threshold (Wegener: Fig. 20 element 656; [0103]; wherein the mapping of element 656 can consider each step as a threshold range).
As per claim 29, DiCeccor/Wegener further teaches The method of claim 25, wherein the threshold comprises a plurality of threshold ranges each corresponding to a respective bit-width, and the adjusting of the bit-width of the mantissa comprises adjusting, in response to the input data corresponding to one of the threshold ranges, the bit-width of the mantissa to be the bit-width corresponding to the one of the threshold ranges (Wegener: Fig. 20 element 656; [0103]; wherein the mapping of element 656 can consider each step as a threshold range).
Claims 27, 30 are rejected under 35 U.S.C. 103 as being unpatentable over DiCecco/Wegener in further view of Henry et al. (US 20190042244 A1, hereinafter “Henry”).
As per claim 27, DiCecco/Wegener further teaches The method of claim 25.
However, while DiCecco discloses low precision multiplier circuits (Fig. 5 element 502; [0036]), DiCecco does not explicitly disclose the processing method of the multipliers. Thus, DiCecco does not teach wherein the performing of the operation comprises using an operator, and the adjusted bit-width of the mantissa is less than or equal to a number of bits processible by the operator in a single cycle.
Henry teaches wherein the performing of the operation comprises using an operator, and the adjusted bit-width of the mantissa is less than or equal to a number of bits processible by the operator in a single cycle (Henry: Fig. 1; [0057]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the multiplier circuitry of DiCecco with the multiplication method of Henry. One would have been motivated to combine these references because both references disclose small integer multipliers in floating-point arithmetic, and Henry teaches the lower precision integer multiplications are more efficient than original floating-point precision ([0059]).
As per claim 30, DiCecco/Wegener/Henry further teaches The method of claim 25, wherein the performing of the operation comprises performing a multiply and accumulate operation using an operator (Henry: Fig. 1 elements 122-128; [0058]; Fig. 2E element 240; [0072]).
It would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the multiplier circuitry of DiCecco with the multiplication method of Henry for at least the same reasons as discussed above in claim 27.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHAT N LE whose telephone number is (571)272-0546. The examiner can normally be reached Monday-Friday 8:30AM-5PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew T Caldwell can be reached at (571) 272-3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/P.N.L./
Phat LeExaminer, Art Unit 2182 (571) 272-0546
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
Prosecution Insights