DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Claims 1, 9 and 17 have been amended. Claims 2-8, 10-16 and 18-21 have been cancelled. Claims 22-38 have been newly added. Claims 1, 9, 17 and 22-38 remain pending and are ready for examination.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 9, and 17 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 contains corresponding limitations to independent claims 1 and 17, however, claim 9 first introduces “a non-volatile memory device” in line 2, and then refers to “selecting based on characteristics of a memory device…”. While the other claims only contain the initial memory device introduced, claim 9 introduces two distinct memory devices, and it is unclear whether the memory device upon whose characteristics are determining the selection of the compaction strategy. In other words, it is unclear if this is referring to the non-volatile memory device, or if this refers to another memory device entirely. In line with the corresponding claims 1 and 17, the examiner is interpreting this as the same memory device. If this is the case, claim 9 should be amended to reflect this by changing the claim to “selecting, based on characteristics of the memory device”.
Additionally, claim 9 reads “determining that the plurality of SLCs memories is fully programmed …” The claim should read “determining that the plurality of SLC memories…” similar to the other references to SLC memories. Corresponding claims 1 and 17 contain the same informality.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 9, 17, 22-23, 28-29 and 34-35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Prudviraj Gunda et al. (US Publication No. 2022/0413758 – “Prudviraj”) in view of Sharma et al. (US Publication No. 2022/0342585 – “Sharma”).
Regarding claim 9, Prudviraj teaches A system comprising: a non-volatile memory device; and a processing device, operatively coupled with the non-volatile memory device, to perform operations comprising: (Prudviraj paragraph [0004], One embodiment of the present disclosure includes a data storage device including a non-volatile memory device including a memory block, the memory block including a number of memory dies, and a controller coupled to the non-volatile memory device. The controller is configured to monitor an activity level of the data storage device and determine whether the data storage device is in an idle condition based on the monitored activity level. The controller is further configured to perform one or more background operations) selecting, based on characteristics of a memory device a compaction strategy of a plurality of compaction strategies to be applied to host data received from a host system, (Prudviraj paragraph [0023], Alternatively, one or more individual memory dies 103 may include corresponding read/write circuitry 140 that is operable to read from and/or write to storage elements within the individual memory die independent of any other read and/or write operations at any of the other memory dies. The relocation circuitry 142 may be configured to perform one or more relocation functions to reallocate data within the memory dies 103. For example, the relocation circuitry 142 may be configured to perform relocation functions such as Single Level Cell (“SLC”) to Single Level Cell compaction, Quad Level Cell (“QLC”) to Quad Level Cell compaction, SLC-QLC compactions, and/or other relocation functions as required for a given application. A given compaction type can be selected based on the requirement for a given application type) wherein characteristics of the memory device is at least one: a size of the memory device, an intended usage of the memory device, a percentage storage space of the memory device that the host intends to reserve towards host data, or an indication of an over-provisioning of the memory device (Prudviraj paragraph [0027], The controller 106 may include a processor 124, a memory 126, and other associated circuitry. The memory 126 may be configured to store data and/or instructions that may be executable by the processor 124. The memory 126 may include a garbage collection application 130, an activity monitor 131, and a background operation (“BKOPS”) module among other applications, programs, etc. The garbage collection application 130 and the activity monitor 131 may be a hardware circuit or instructions that are executable by the processor 124. While shown as being stored in the memory 126, in some examples the garbage collection application 130 and the activity monitor 131 may be configured as circuits within the memory device 104. The activity monitor may determine an intended usage for the memory device with respect to an application type which can be used to determine the compaction strategy selected, as seen above) wherein the compaction strategy is stored in the memory device (Prudviraj paragraph [0020], The host device 108 may include a processor and a memory. The memory may be configured to store data and/or instructions that may be executable by the processor. The memory may be a single memory or may include one or more memories, such as one or more non-volatile memories, one or more volatile memories, or a combination thereof. The host device 108 may issue one or more commands to the data storage device 102, such as one or more requests to erase data at, read data from, or write data to the memory device 104 of the data storage device 102. The instructions for performing commands may be stored in the data storage device) and comprises one of: a quad-level cell (QLC) level batch compaction strategy, a single-level cell (SLC) level compaction strategy, or a partial SLC level compaction strategy (Prudviraj paragraph [0038], In response to the sequential read operation being determined to equal or exceed the sequential threshold, a determination is made as to whether any previous relocation operations have been paused at block 310. In one embodiment, the relocation circuitry 142 determines whether any previous relocation operations have been completed. The relocation circuitry 142 may communicate with the controller 106 to determine whether any relocation operations have been paused. In other examples, the garbage collection application 130 determines whether any previous relocation operations have been paused. In response to determining that previous relocation operations had been paused, the previous relocation operations are completed at block 312. Upon completing the paused relocation operations, prioritized garbage collection operations are performed at block 314 along with the performing the requested sequential reads. As noted above, the prioritized garbage collection operations may include QLC-QLC block compaction operations, SLC-SLC block compaction operations, and SLC-QLC block folding operations. In response to determining that no previous relocation operations were paused, garbage collection operations are performed at block 314 along with performing the requested sequential reads. The compaction operations/strategies taking place may be based on SLC level compaction, QLC level compaction, or even partial SLC level compaction utilizing both SLC and QLC levels in a single compaction operation/strategy) wherein each of the plurality of compaction strategies is to program host data from at least one SLC of the memory device to at least one QLC of the memory device; (Prudviraj paragraph [0025], The controller 106 is configured to receive data and instructions from the host device 108 and to send data to the host device 108. For example, the controller 106 may send data to the host device 108 via the interface 120, and the controller 106 may receive data from the host device 108 via the interface 120. The controller 106 is configured to send data and commands (e.g., the memory operation 136, which may be a cycle operation of a memory block of the memory device 104) to the memory device 104 and to receive data from the memory device 104. Data can be programmed from the host from SLC to QLC data, see Prudviraj paragraph [0032], As discussed above, example relocation operations may SLC-QLC folding, SLC-SLC compaction, QLC-QLC compaction) wherein the selected compaction strategy provides a different balance between available host data storage space and at least one of: garbage collection efficiency, quality of service, or endurance of the memory device; (Prudviraj paragraph [0039], In one embodiment, the prioritized garbage collection operations are performed in priority order. The priority order of the garbage collection operations may be based on a latency time to perform each operation. For example, where the garbage collection operations are relocation operations, such as those described above, the relocation operation with the highest latency time will have the highest priority, and so on for the remaining relocation operations. In one embodiment, a QLC-QLC compaction operation may be a latency time of approximately 8.25 seconds. A QLC-SLC folding operation may have a latency time of approximately 3.8 seconds, and an SLC-SLC compaction may have a latency time of approximately 2.4 seconds. The above latency times are for exemplary purposes, and it is understood that latency times may vary based on different factors, such as data storage device type, controller type, electronic processor speed, etc. By prioritizing the relocation operations based on latency time, the longest latency time operations are performed first during the sequential read instead of during a write operation which may result in a loss in performance. In one embodiment, all of the highest priority relocation operations are completed before the next highest priority relocation operation are started to ensure that all the highest priority relocation operations are completed first. While the above prioritization of the relocation operations is based on latency time, in some embodiments other criteria, such as available memory space, data type, etc. may be used to prioritize the relocation operations. Various factors such as garbage collection efficiency or latency (i.e., quality of service) may depend on the type of compaction strategy selected) determining that the plurality of SLC memories is fully programmed with the one or more host data; (Prudviraj paragraph [0056], Generally, physical fullness of memory occurs significantly earlier than logical fullness due to padding, overlap writes, control data updates, and/or more invalidations on SLC or QLC blocks. In previous approaches, such as those shown in data plot 700, relocation operations are triggered based on the threshold of remaining free blocks within a memory. Due to this, no compaction or folding operations are performed until the threshold of remaining fee blocks is met, which may result in invalid data and can cause physical fullness to occur substantially earlier than logical fullness. This can impact performance of the memory device substantially once the physical fullness reaches a critical level. By utilizing the prioritized relocation process 600 during idle periods, relocation operations, such as QLC-QLC compaction, SLC-SLC compaction, and SLC-QLC folding during times where physical fullness is at lower levels, performance improvement, such as logical fullness shown on data plot 702, is achieved. The compaction operation may be initiated in response to a fullness indicator regarding the programmed SLC memory) and programming a QLC memory with the one or more host data stored in the plurality of SLC memories (Prudviraj paragraphs [0041], The above process 300 is configured to allow for certain garbage collection operations to be performed during sequential read operations. Typically, these garbage collection operations are performed during write operations, which may lead to a reduced performance. By utilizing the relative idleness of the memory device 104 and/or controller 106 during sequential reads, multiple relocations may be able to be performed during the sequential read. For example, a sequential read may be a movie or other video clip being accessed for a period of time. Where the sequential read is 100 seconds, 12 QLC-QLC compactions (using the above latency times) may be performed, resulting in up to 48 QLC blocks being freed. Similarly, 25 SCL-QLC folding operations may be performed, resulting in up to 100 SLC blocks being freed, etc. The QLC memory may be written to as part of a folding operation transferring the SLC memory data to the QLC memory).
Prudviraj does not teach responsive to determining that the selected compaction strategy is a QLC level batch compaction strategy, initializing a plurality of SLC memories of the memory device; receiving, after initializing the plurality of SLC memories one or more host data from the host system.
However, Sharma teaches responsive to determining that the selected compaction strategy is a QLC level batch compaction strategy, initializing a plurality of SLC memories of the memory device; receiving, after initializing the plurality of SLC memories one or more host data from the host system. (Sharma paragraph [0022], In contrast, the legacy programming sequences in QLC NAND memory cells requires all four pages to start the foggy programming operation. In the MLC-Fine programming sequence, the lower and middle pages of data become readable after completion of the MLC programming stage. The lower and middle page data can be either stored in SLC blocks (e.g., folding architectures) or in volatile memory (e.g., RAM). During the fine programming stage, the memory controller can perform internal read of lower and middle pages, whereas the storage system may need to only provide two pages of data (e.g., upper and top pages) to start the fine programming operation. As such, the MLC-Fine programming sequence can significantly reduce the write buffer requirements. To begin the QLC compaction (i.e., folding operation), the SLC blocks must be initialized and written to).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Prudviraj with those of Sharma. Sharma teaches initializing SLC memory before performing a QLC compacting operation, which can ensure that the compaction operation is targeting the precise memory blocks which are targeted by write operations, resulting in more efficient memory space utilization (i.e., see Sharma paragraph [0003], The growing demand for high capacity storage devices has catalyzed the use of multi-level NAND flash memory cells, which include multi-level cells (MLC, 2 bits per cell), triple-level cells (TLC, 3 bits per cell), quad-level cells (QLC, 4 bits per cell), and higher capacities. As the number of bits stored in a memory cell increases, the level of precision required for reliable data programming also becomes stricter in tandem. Existing approaches for precise programming of multi-level NAND flash memory cells may demand additional hardware resources, which increases the complexity and cost of the storage device while reducing available space for other productive uses. Thus, there is a need for a more efficient method of programming multi-level NAND flash memory cells).
Claims 1 and 17 are the corresponding method and non-transitory computer readable medium claims to system claim 9. They are rejected with the same references and rationale.
Regarding claim 28, Prudviraj in view of Sharma teaches The system of claim 9, wherein the processing device is to perform operations further comprising: determining whether the QLC memory has been fully programmed with the host data stored in the plurality of SLC memories (Prudviraj paragraph [0032], However, in other examples, other components such as the relocation circuitry 142 may be configured to determine whether the one or more garbage collection operations are required. Garbage collection operations are generally implemented in the flash translation layer (“FTL”) of NAND-type memory to free previously invalidated memory space to allow for further write operations to be performed. Garbage collection generally eliminates the requirement that an entire memory block be erased prior to every write operation. In some examples, garbage collection processes may include one or more relocation operations to relocate valid data to new data blocks. As discussed above, example relocation operations may SLC-QLC folding, SLC-SLC compaction, QLC-QLC compaction, etc. In some examples, an SLC-SLC compaction and/or SLC-QLC folding operation may be performed where the number of available SLC blocks are below or almost below a minimum threshold, such as 10%. However, minimum threshold values of more than 10% or less than 10% may also be used as appropriate for a given application. The data stored in the SLC memory may be compacted into QLC memory when a given data threshold is reached, which may correspond to fully programming the QLC memory, also see Prudviraj paragraph [0041], For example, a sequential read may be a movie or other video clip being accessed for a period of time. Where the sequential read is 100 seconds, 12 QLC-QLC compactions (using the above latency times) may be performed, resulting in up to 48 QLC blocks being freed. Similarly, 25 SCL-QLC folding operations may be performed, resulting in up to 100 SLC blocks being freed, etc).
Claims 22 and 34 are the corresponding method and non-transitory computer readable medium claims to system claim 28. They are rejected with the same references and rationale.
Regarding claim 29, Prudviraj in view of Sharma teaches The system of claim 28, wherein the processing device is to perform operations further comprising: responsive to determining that the QLC memory has been fully programmed with the host data stored in the plurality SLC memories, erasing the plurality of SLC memories to continue receiving host data from the host system (Prudviraj paragraph [0032], However, in other examples, other components such as the relocation circuitry 142 may be configured to determine whether the one or more garbage collection operations are required. Garbage collection operations are generally implemented in the flash translation layer (“FTL”) of NAND-type memory to free previously invalidated memory space to allow for further write operations to be performed. Garbage collection generally eliminates the requirement that an entire memory block be erased prior to every write operation. In some examples, garbage collection processes may include one or more relocation operations to relocate valid data to new data blocks. As discussed above, example relocation operations may SLC-QLC folding, SLC-SLC compaction, QLC-QLC compaction, etc. In some examples, an SLC-SLC compaction and/or SLC-QLC folding operation may be performed where the number of available SLC blocks are below or almost below a minimum threshold, such as 10%. However, minimum threshold values of more than 10% or less than 10% may also be used as appropriate for a given application. After the data compaction occurs, the SLC memory blocks may be freed/erased to clear up space for future writes, also see Prudviraj paragraph [0041], The above process 300 is configured to allow for certain garbage collection operations to be performed during sequential read operations. Typically, these garbage collection operations are performed during write operations, which may lead to a reduced performance. By utilizing the relative idleness of the memory device 104 and/or controller 106 during sequential reads, multiple relocations may be able to be performed during the sequential read. For example, a sequential read may be a movie or other video clip being accessed for a period of time. Where the sequential read is 100 seconds, 12 QLC-QLC compactions (using the above latency times) may be performed, resulting in up to 48 QLC blocks being freed. Similarly, 25 SCL-QLC folding operations may be performed, resulting in up to 100 SLC blocks being freed, etc).
Claims 23 and 35 are the corresponding method and non-transitory computer readable medium claims to system claim 29. They are rejected with the same references and rationale.
Claim(s) 24, 30 and 36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Prudviraj in view of Sharma as applied to claims 1, 9 and 17 above, and further in view of Natarajan et al. (US Publication No. 2020/0105363 – “Natarajan”).
Regarding claim 30, Prudviraj in view of Sharma in further view of Natarajan teaches The system of claim 9, wherein the QLC memory is programmed using a copy-back operation (Natarajan paragraph [0033], Turning now to FIG. 4, an embodiment of a SSD 45 may include single level cell (SLC) NAND media 46, quad level cell (QLC) NAND media 47, and a storage controller 48. For example, the SLC NAND media 46 may have a smaller block size and provide faster performance as compared to the QLC NAND media 47. To improve the performance for the slower media (e.g., such as the QLC NAND media 47), the SSD 45 may support a copyback operation. For example, the copyback operation may be utilized to improve sequential write performance As part of the copyback operation, data is copied from the faster media (e.g., the SLC NAND media 46) to the slower media (e.g., the QLC NAND media 47) without any checks performed for bit errors. A copy-back operation can be used to program QLC memory).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Prudviraj and Sharma with those of Natarajan. Natarajan teaches using a copy-back operation for programming QLC memory, which can improve sequential write operations targeted towards slower memory forms, such as QLC (i.e., see Natarajan paragraph [0033], Turning now to FIG. 4, an embodiment of a SSD 45 may include single level cell (SLC) NAND media 46, quad level cell (QLC) NAND media 47, and a storage controller 48. For example, the SLC NAND media 46 may have a smaller block size and provide faster performance as compared to the QLC NAND media 47. To improve the performance for the slower media (e.g., such as the QLC NAND media 47), the SSD 45 may support a copyback operation. For example, the copyback operation may be utilized to improve sequential write performance As part of the copyback operation, data is copied from the faster media (e.g., the SLC NAND media 46) to the slower media (e.g., the QLC NAND media 47) without any checks performed for bit errors).
Claims 24 and 36 are the corresponding method and non-transitory computer readable medium claims to system claim 30. They are rejected with the same references and rationale.
Claim(s) 25-27, 31-33 and 37-38 is/are rejected under 35 U.S.C. 103 as being unpatentable over Prudviraj in view of Sharma in further view of Natarajan as applied to claims 24, 30 and 36 above, and further in view of Zhang et al. (US Publication No. 2022/0319591 – “Zhang”).
Regarding claim 31, Prudviraj in view of Sharma in further view of Natarajan and further in view of Zhang teaches The system of claim 30, wherein the copy-back operation (see Natarajan above) moves the one or more host data stored in the plurality of SLC memories to the QLC memory using a coarse programming pass and a fine programming pass (Zhang paragraph [0023], Specifically, for a QLC NAND Flash memory device, two schemes, an 8-16 scheme and a 16-16 scheme, can be used for program and read operations. According to the 8-16 scheme, the NAND Flash cells are first programmed to 8 intermediate levels in a coarse programming pass (e.g., a non-last programming pass), and then programmed to 16 levels (16 threshold voltage levels corresponding to the 16 states of a QLC NAND Flash cell) in a fine programming pass (e.g., the last programming pass). According to the 16-16 scheme, the NAND Flash cells are first programmed to 16 levels of broader distributions in a coarse programming pass, and then reprogrammed to 16 voltages levels of narrower distributions in a fine programming pass. The NAND QLC memory may be programmed using both fine and coarse pass programming).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Prudviraj, Sharma and Natarajan with those of Zhang. Zhang teaches using a fine and coarse programming pass for programming data to QLC memory, which can allow for more efficient programming operations based on factors such as voltage levels (i.e., see Zhang paragraph [0023], Error correction can be easier using a gray-coded programming value in the program and read operations of a NAND Flash memory device. The gray-coded programming value can then be programmed into and read from the NAND Flash memory device. Specifically, for a QLC NAND Flash memory device, two schemes, an 8-16 scheme and a 16-16 scheme, can be used for program and read operations. According to the 8-16 scheme, the NAND Flash cells are first programmed to 8 intermediate levels in a coarse programming pass (e.g., a non-last programming pass), and then programmed to 16 levels (16 threshold voltage levels corresponding to the 16 states of a QLC NAND Flash cell) in a fine programming pass (e.g., the last programming pass). According to the 16-16 scheme, the NAND Flash cells are first programmed to 16 levels of broader distributions in a coarse programming pass, and then reprogrammed to 16 voltages levels of narrower distributions in a fine programming pass. To read the levels, respective read voltages are applied on the QLC NAND Flash cells to read the states and determine the state. The levels programmed using the two schemes are respectively readable to their read operations).
Claims 25 and 37 are the corresponding method and non-transitory computer readable medium claims to system claim 31. They are rejected with the same references and rationale.
Regarding claim 32, Prudviraj in view of Sharma in further view of Natarajan and further in view of Zhang teaches The system of claim 31, wherein the coarse programming pass reads the one or more host data stored in the plurality of SLC memories (see Prudviraj above for compaction from SLC-QLC) and programs at a first pace the one or more host data to the QLC memory (Zhang paragraph [0023], Specifically, for a QLC NAND Flash memory device, two schemes, an 8-16 scheme and a 16-16 scheme, can be used for program and read operations. According to the 8-16 scheme, the NAND Flash cells are first programmed to 8 intermediate levels in a coarse programming pass (e.g., a non-last programming pass), and then programmed to 16 levels (16 threshold voltage levels corresponding to the 16 states of a QLC NAND Flash cell) in a fine programming pass (e.g., the last programming pass). According to the 16-16 scheme, the NAND Flash cells are first programmed to 16 levels of broader distributions in a coarse programming pass, and then reprogrammed to 16 voltages levels of narrower distributions in a fine programming pass. To read the levels, respective read voltages are applied on the QLC NAND Flash cells to read the states and determine the state. The levels programmed using the two schemes are respectively readable to their read operations. Zhang describes using a coarse and fine programming pass for programming QLC memory, wherein the coarse programming speed is faster than the fine programming speed, as seen in Zhang paragraph [0051], As previously described, the first gray-coded programming value corresponds to a first scheme of a higher read speed, and the second gray-coded programming value corresponds to a second scheme of a higher program speed. In some embodiments, memory cell 306 is a QLC having 16 states, the first scheme is a 16-16 scheme, and the second scheme is an 8-16 scheme. As shown in FIGS. 6A and 6B, each of the gray codes depicts the 16 states of a memory cell and the mapping gray-coded value, e.g., having 4 bits of data. For example, state 2 is mapped to gray-coded value 0110 based on the first gray code shown in FIG. 6A and is mapped to gray-coded value 0110 based on the second gray code shown in LUT 2 in FIG. 6B. In the present disclosure, the first gray code can also be referred to as a read gray code, and the second gray code can also be referred to as a program gray code).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Prudviraj, Sharma and Natarajan with those of Zhang. Zhang teaches using a fine and coarse programming pass for programming data to QLC memory, which can allow for more efficient programming operations based on factors such as voltage levels (i.e., see Zhang paragraph [0023], Error correction can be easier using a gray-coded programming value in the program and read operations of a NAND Flash memory device. The gray-coded programming value can then be programmed into and read from the NAND Flash memory device. Specifically, for a QLC NAND Flash memory device, two schemes, an 8-16 scheme and a 16-16 scheme, can be used for program and read operations. According to the 8-16 scheme, the NAND Flash cells are first programmed to 8 intermediate levels in a coarse programming pass (e.g., a non-last programming pass), and then programmed to 16 levels (16 threshold voltage levels corresponding to the 16 states of a QLC NAND Flash cell) in a fine programming pass (e.g., the last programming pass). According to the 16-16 scheme, the NAND Flash cells are first programmed to 16 levels of broader distributions in a coarse programming pass, and then reprogrammed to 16 voltages levels of narrower distributions in a fine programming pass. To read the levels, respective read voltages are applied on the QLC NAND Flash cells to read the states and determine the state. The levels programmed using the two schemes are respectively readable to their read operations).
Claims 26 and 38 are the corresponding method and non-transitory computer readable medium claims to system claim 32. They are rejected with the same references and rationale.
Regarding claim 33, Prudviraj in view of Sharma in further view of Natarajan and further in view of Zhang teaches The system of claim 32, wherein the fine programming pass programs the one or more host data stored in the plurality of SLC memories (see Prudviraj above for compaction from SLC-QLC) and programs at a second pace the QLC memory, wherein the first pace is faster than the second pace (Zhang paragraph [0023], Specifically, for a QLC NAND Flash memory device, two schemes, an 8-16 scheme and a 16-16 scheme, can be used for program and read operations. According to the 8-16 scheme, the NAND Flash cells are first programmed to 8 intermediate levels in a coarse programming pass (e.g., a non-last programming pass), and then programmed to 16 levels (16 threshold voltage levels corresponding to the 16 states of a QLC NAND Flash cell) in a fine programming pass (e.g., the last programming pass). According to the 16-16 scheme, the NAND Flash cells are first programmed to 16 levels of broader distributions in a coarse programming pass, and then reprogrammed to 16 voltages levels of narrower distributions in a fine programming pass. To read the levels, respective read voltages are applied on the QLC NAND Flash cells to read the states and determine the state. The levels programmed using the two schemes are respectively readable to their read operations. Zhang describes using a coarse and fine programming pass for programming QLC memory, wherein the coarse programming speed is faster than the fine programming speed, as seen in Zhang paragraph [0051], As previously described, the first gray-coded programming value corresponds to a first scheme of a higher read speed, and the second gray-coded programming value corresponds to a second scheme of a higher program speed. In some embodiments, memory cell 306 is a QLC having 16 states, the first scheme is a 16-16 scheme, and the second scheme is an 8-16 scheme. As shown in FIGS. 6A and 6B, each of the gray codes depicts the 16 states of a memory cell and the mapping gray-coded value, e.g., having 4 bits of data. For example, state 2 is mapped to gray-coded value 0110 based on the first gray code shown in FIG. 6A and is mapped to gray-coded value 0110 based on the second gray code shown in LUT 2 in FIG. 6B. In the present disclosure, the first gray code can also be referred to as a read gray code, and the second gray code can also be referred to as a program gray code).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Prudviraj, Sharma and Natarajan with those of Zhang. Zhang teaches using a fine and coarse programming pass for programming data to QLC memory, which can allow for more efficient programming operations based on factors such as voltage levels (i.e., see Zhang paragraph [0023], Error correction can be easier using a gray-coded programming value in the program and read operations of a NAND Flash memory device. The gray-coded programming value can then be programmed into and read from the NAND Flash memory device. Specifically, for a QLC NAND Flash memory device, two schemes, an 8-16 scheme and a 16-16 scheme, can be used for program and read operations. According to the 8-16 scheme, the NAND Flash cells are first programmed to 8 intermediate levels in a coarse programming pass (e.g., a non-last programming pass), and then programmed to 16 levels (16 threshold voltage levels corresponding to the 16 states of a QLC NAND Flash cell) in a fine programming pass (e.g., the last programming pass). According to the 16-16 scheme, the NAND Flash cells are first programmed to 16 levels of broader distributions in a coarse programming pass, and then reprogrammed to 16 voltages levels of narrower distributions in a fine programming pass. To read the levels, respective read voltages are applied on the QLC NAND Flash cells to read the states and determine the state. The levels programmed using the two schemes are respectively readable to their read operations).
Claim 27 is the corresponding method claim to system claim 33. It is rejected with the same references and rationale.
Response to Arguments
Applicant’s arguments, see pages 1-3 (numbered pages 9-11) filed April 6th, 2026, with respect to the rejection(s) of claim(s) 1, 9 and 17 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Prudviraj Gunda et al. (US Publication No. 2022/0413758 – “Prudviraj”) in view of Sharma et al. (US Publication No. 2022/0342585 – “Sharma”).
The applicant’s amendments to the independent claims 1, 9 and 17 further recite details regarding the selection of the compaction strategy, as well as additional features describing the determining memory characteristics and tradeoffs between various memory functions and an initialization of SLC memory, which is now disclosed by the Sharma reference, as seen above. In light of the newly added references, the 35 USC 103 Rejection is maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Takada et al. (US Publication No. 2022/0059164) teaches using a plurality of different compaction modes for data storage/write methods, based on a variety of factors such as enhancing write performance (i.e., see Takada paragraph [0224], FIG. 32 shows an example of a combination of the data storage method between the buffer write operation and the compaction write operation in the first variation of the second embodiment. As shown in FIG. 32, when the SLC mode is used for the buffer write operation, the MLC mode, TLC mode, or QLC mode is used for the compaction write operation. When the MLC mode is used for the buffer write operation, the TLC mode or the QLC mode is used for the compaction write operation. When the TLC mode is used for the buffer write operation, the QLC mode is used for the compaction write operation, for example. A data storage method of 5 bits/cell or more may be used for the compaction write operation. Also see [0227]).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.C.K./Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133
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