Authorization for Internet Communications
The examiner encourages Applicant to submit an authorization to communicate with the examiner via the Internet by making the following statement (from MPEP 502.03):
“Recognizing that Internet communications are not secure, I hereby authorize the USPTO to communicate with the undersigned and practitioners in accordance with 37 CFR 1.33 and 37 CFR 1.34 concerning any subject matter of this application by video conferencing, instant messaging, or electronic mail. I understand that a copy of these communications will be made of record in the application file.”
Please note that the above statement can only be submitted via Central Fax, Regular postal mail, or EFS Web (PTO/SB/439).
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Examiner Notes
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1: Regarding claim 1, this part of the eligibility analysis evaluates whether the claim falls within any statutory category. MPEP §2106.03. The claim recites method steps; thus, the claim is directed to a process which is one of the statutory categories of invention.
Step 2A Prong 1: This part of the eligibility analysis evaluates whether the claim recites a judicial exception. As explained in MPEP 2106.04(II) and the October 2019 Update, a claim “recites” a judicial exception when the judicial exception is “set forth” or “described” in the claim.
The limitations “identifying, a guest memory page referenced by a guest memory page address in a guest memory space of a virtual machine managed by the hypervisor,” “mapping a host memory page to the guest memory page,” as drafted, recite functions that, under its broadest reasonable interpretation, covers functions that could reasonably be performed in the mind, including with the aid of pen and paper, but for the recitation of generic computer components. That is, the limitations as drafted, are functions that, under its broadest reasonable interpretation, recite the abstract idea of a mental process. The limitations encompass a human mind carrying out the functions through observation, evaluation, judgment and/or opinion, or even with the aid of pen and paper. Thus, these limitations recite and fall within the “Mental Processes” grouping of abstract ideas. See MPEP §2106.04(a)(2). Accordingly, claim 1 recites a judicial exception (i.e. an abstract idea).
Step 2A, Prong 2, This part of the eligibility analysis evaluates whether the claim as a whole integrates the recited judicial exception into a practical application of the exception. This evaluation is performed by (a) identifying whether there are any additional elements recited in the claim beyond the judicial exception, and (b) evaluating those additional elements individually and in combination to determine whether the claim as a whole integrates the exception into a practical application. 2019 PEG Section III(A)(2), 84 Fed. Reg. at 54-55.
In this case, this judicial exception is not integrated into a practical application. The claim recites the following additional elements “by a hypervisor running on a host computer system,” “wherein the virtual machine comprises a virtual central processing unit (CPU) emulated by the hypervisor,” “a host CPU that is different from the virtual CPU” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using a generic computer component, or merely a generic processor or generic computer components to perform the judicial exception. Accordingly, the additional elements do not integrate the recited judicial exception into a practical application, and the claim is therefore directed to the judicial exception. See MPEP 2106.05(f).
The claim includes additional elements of insignificant extra solution activity “making the guest memory page inaccessible by the virtual machine; notifying the virtual machine of the guest memory page address; receiving, from the virtual machine via a communication channel in a data storage shared by the virtual machine and the hypervisor, a page fault notification with respect to the guest memory page of the virtual machine; and after and responsive to receiving”
The ”receiving” step is not a practical application because it is merely data gathering which the court have identified as well understood, routine, and conventual activity. See MPEP 2106.05(d).
The “making” step is not a practical application because it fails to meaningfully limit the claim because it does not require any particular application of the recited “making” and is at best the equivalent of merely adding the words “apply it” to the judicial exception. Accordingly, the additional elements do not integrate the recited judicial exception into a practical application, and the claim is therefore directed to the judicial exception. See MPEP 2106.05(f).
The ”after and responsive” step only amounts to insignificant extra-solution activity of data input and output or applying it. Data input and output is consider well understood, routine, and conventual activity. See MPEP 2106.05(g).
Step 2B, This part of the eligibility analysis evaluates whether the claim as a whole amounts to significantly more than the recited exception, i.e., whether any additional element, or combination of additional elements, adds an inventive concept to the claim. MPEP 2106.05.
As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of the “by a hypervisor running on a host computer system” are merely a generic computer or generic computer components to apply the judicial exception which cannot provide an inventive concept. The claims include additional elements “making the guest memory page inaccessible by the virtual machine; notifying the virtual machine of the guest memory page address; receiving, from the virtual machine via a communication channel in a data storage shared by the virtual machine and the hypervisor, a page fault notification with respect to the guest memory page of the virtual machine; and after and responsive to receiving.”
The ”receiving” is not significantly more than the abstract idea and fails inventive concept because it is merely data gathering which the court have identified as well understood, routine, and conventual activity. See MPEP 2106.05(d).
The “making” step is not significantly more than the abstract idea and fails inventive concept because it fails to meaningfully limit the claim because it does not require any particular application of the recited “making” and is at best the equivalent of merely adding the words “apply it” to the judicial exception. Mere instructions to apply an exception cannot provide an inventive concept.
The ”notifying” and “responsive” step only amounts to insignificant extra-solution activity of data input and output or applying it. Data input and output is consider well understood, routine, and conventual activity. See MPEP 2106.05(g).
Accordingly, the claim does not appear to be patent eligible under 35 USC 101.
Regarding claim 2 is a dependent claim rejected for the same reasons as claim 1. Furthermore, the claims include additional elements “wherein notifying the virtual machine of the guest memory page address further comprises notifying, via a message written to a shared memory shared between the hypervisor and the virtual machine, the virtual machine of the guest memory page address.” This additional element does not amount to a practical application, nor recite significantly more than a judicial exception, is merely data gathering which the court have identified as well understood, routine, and conventual activity. See MPEP 2106.05(d).
Regarding claim 3, is a dependent claim rejected for the same reasons as claim 1. Furthermore, claims include additional elements “responsive to making the guest memory page inaccessible, assigning the guest memory page to a second virtual machine managed by the hypervisor.”
This additional element does not amount to a practical application, nor recite significantly more than a judicial exception, because the additional elements are merely instructions to implement an abstract idea on a computer. MPEP 2106.04(d).
Regarding claim 4, is a dependent claim rejected for the same reasons as claim 1. Furthermore, claims include additional elements “responsive to mapping the host memory page to the guest memory page, notifying the virtual machine of accessibility of the guest memory page address.” This additional element does not amount to a practical application, nor recite significantly more than a judicial exception, is merely data gathering which the court have identified as well-understood, routine, and conventional activity. See MPEP 2106.05(d).
Regarding claim 5, is a dependent claim rejected for the same reasons as claim 1. Furthermore, claims include additional elements “wherein making the guest memory page inaccessible further comprises modifying a page table entry in a host page table.”
Regarding claim 6, is a dependent claim rejected for the same reasons as claim 1. Furthermore, claims include additional elements “wherein mapping the host memory page to the guest memory page further comprises modifying a page table entry in a host page table.” This additional element does not amount to a practical application, nor recite significantly more than a judicial exception, because the additional elements are merely instructions to implement an abstract idea on a computer. MPEP 2106.04(d).
Regarding claim 7, is a dependent claim rejected for the same reasons as claim 1. Furthermore, claims include additional elements “wherein notifying the virtual machine of the guest memory page address further comprises having the virtual machine, responsive to receiving the guest memory page address notification, make the guest memory page referenced by the guest memory page address inaccessible by a guest application running on the virtual machine.” This additional element does not amount to a practical application, nor recite significantly more than a judicial exception, is merely data gathering which the court have identified as well-understood, routine, and conventional activity. See MPEP 2106.05(d).
Regarding claim 8, is a dependent claim rejected for the same reasons as claim 1. Furthermore, claims include additional elements “wherein having the virtual machine make the guest memory page inaccessible by the guest application further comprises modifying a page table entry in a guest page table.” This additional element does not amount to a practical application, nor recite significantly more than a judicial exception, because the additional elements are merely instructions to implement an abstract idea on a computer. MPEP 2106.04(d).
Regarding claim 9, is a dependent claim rejected for the same reasons as claim 1. Furthermore, claims include additional elements “wherein the page fault notification indicates a page fault with respect to the guest memory page and is generated responsive to detecting the page fault by the virtual machine.” This additional element does not recite significantly more than a judicial exception, because it is recognized as well-understood, routine, and conventional activity of storing and retrieving information in memory. See MPEP 2106.05(d)(II)(iv).
Regarding claim 10, is a dependent claim rejected for the same reasons as claim 1. Furthermore, claims include additional elements “wherein notifying the virtual machine of the accessibility of the guest memory page address further comprises having the virtual machine, responsive to receiving the notification of the accessibility of the guest memory page address, make the guest memory page accessible by a guest application.” This additional element does not recite significantly more than a judicial exception, because it is recognized as well-understood, routine, and conventional activity of storing and retrieving information in memory. See MPEP 2106.05(d)(II)(iv).
Regarding claim 11, is a dependent claim rejected for the same reasons as claim 1. Furthermore, claims include additional elements “wherein having the virtual machine make the guest memory page accessible by the guest application further comprises modifying a page table entry in a guest page table.” This additional element does not recite significantly more than a judicial exception, because it is recognized as well-understood, routine, and conventional activity of storing and retrieving information in memory. See MPEP 2106.05(d)(II)(iv).
Claim 12, is an independent system claim which corresponds with claim 1 and is rejected for the same reasons as claim 1. In particular, the claim recites two additional elements “a memory” and “a processor.” The memory and a processor are recited at a high-level of generality (i.e., as a generic processor performing a generic computer function, and generic memory) such that it amounts no more than mere instructions to apply the exception using a generic computer component. Accordingly, these additional element does not integrate the abstract idea into a practical application, nor recite significantly more than the abstract idea. The claim is directed to an abstract idea.
Regarding claim 13-18, are medium claims corresponding to claims 3-4, 10, 5, 8 above, respectively, and are rejected for the same reasons.
Regarding claim 18, is an independent medium claim rejected for the same reasons as claim 1. In particular, the claim recites additional element “storage medium” and “processing device” The storage medium and processing device is recited at a high-level of generality (i.e., as a generic medium, and generic processing device) such that it amounts no more than mere instructions to apply the exception using a generic computer component. Accordingly, these additional element does not integrate the abstract idea into a practical application, nor recite significantly more than the abstract idea. The claim is directed to an abstract idea.
Regarding claim 19-20, are medium claims corresponding to claims 3-4 above, respectively, and are rejected for the same reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 4, 6, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tsirkin et al. (U.S. PG PUB 2018/0150232).
Regarding claim 1, Tsirkin teaches a method comprising:
identifying, by a hypervisor running on a host computer system, a guest memory page referenced by a guest memory page address in a guest memory space of a virtual machine managed by the hypervisor (see ¶ [0020] “For example, when the guest allocates memory pages, it selects a guest memory address to use for a memory page and puts this guest memory address into the guest's set of page tables within the guest.”),
wherein the virtual machine comprises a virtual central processing unit (CPU) emulated by the hypervisor (see ¶[0031] “Virtual machine 130 includes at least one guest 136, which may include a kernel, OS, and/or other application running on the virtual machine. A guest kernel of virtual machine 130 may provide core computing functionality, such as allocating memory pages of guest memory 132 to processes and/or threads, communicating I/O to and from virtual devices, managing a file system, handling interrupts, scheduling and running processes to execute instructions of computing tasks by a virtual processor, providing an interface between devices and software applications, and/or providing other important computing features.”);
making the guest memory page inaccessible by the virtual machine (see ¶[0037] “ Additionally, hypervisor 120 may deallocate and unmap some of the guest memory pages that were previously allocated to guest 136 and backed up by host memory 108.”);
notifying, by a host CPU that is different from the virtual CPU (see ¶ [0023] “Host machine 102 is coupled to host hardware 104. Host hardware 104 includes physical elements such as a processor 106 and a memory 108”),
the virtual machine of the guest memory page address (see ¶ [0047] “Processor 106 may make this page table entry writable and insert the host memory address to which a guest memory page is mapped into the page table entry. Accordingly, memory manager 128 that the plurality of guest-allocated memory pages 214 included in allocation request 218 is backed by host physical memory. In this way, memory manager 128 may map guest memory addresses to actual physical memory.”);
receiving, from the virtual machine via a communication channel in a data storage shared by the virtual machine and the hypervisor (see ¶[0038] “In an example, guest 136 sends a request to allocate a plurality of guest memory pages for guest 136 to hypervisor 120. I/O module 126 may receive the memory allocation request and pass it along to memory manager 128 for processing”), a page fault notification with respect to the guest memory page of the virtual machine (see ¶[0041] “] An attempted access to a guest memory page may cause a page fault for a variety of reasons. In an example, guest 136 may attempt to read a memory page that is not present in main memory.”); and
after and responsive to the receiving, mapping a host memory page to the guest memory page (Note: The mapping occurs after and responsive to the page fault, as described in ¶[0041] that a guest attempts to read a memory page that is not present and thus a mapping later occurs, see ¶[0041] “An attempted access to a guest memory page may cause a page fault for a variety of reasons. In an example, guest 136 may attempt to read a memory page that is not present in main memory. In this example, an exit to hypervisor 120 may occur, and hypervisor 120 may detect the attempted read, allocate some host physical memory (e.g., random access memory (RAM) memory) corresponding to the attempted read, map guest memory pages to this allocated host physical memory, and perform the read on behalf of the guest.”).
Because Tsirkin discloses multiple embodiments and implementations, and all the findings may be disclosed in different embodiments/implementations, obviousness rejection is made. One of ordinary skill in the art at the time of the invention would be able to combine different embodiments adjacent to each other in the prior art and does not require a leap of inventiveness. Tsirkin discloses that these embodiments/implementations are used in order to reducing the number of exits to the hypervisor (see Tsirkin ¶[0018]).
Regarding claim 3, Tsirkin teaches further comprising: responsive to making the guest memory page inaccessible, assigning the guest memory page to a second virtual machine managed by the hypervisor (see ¶[0029] “Set of host page tables 122 uses the entries to map one or more ranges of the host-physical memory addresses into one or more guest-physical address ranges that are assigned to virtual machine 130 as guest memory 132. Host-physical memory is hardware memory 108.”).
Regarding claim 4, Tsirkin teaches further comprising: responsive to mapping the host memory page to the guest memory page, notifying the virtual machine of accessibility of the guest memory page address (see ¶ [0005] “Each page table entry stores one or more mappings of a guest memory address to host physical memory. The system further includes a memory manager that manages the set of host page tables, allocates a plurality of host memory pages, and maps the guest memory addresses included in the list to the plurality of host memory pages. The plurality of host memory pages is part of the host memory”).
Regarding claim 6, Tsirkin teaches wherein mapping the host memory page to the guest memory page further comprises modifying a page table entry in a host page table (see ¶[0047] “Memory manager 128 may implement this mapping by, for example, setting up entries in set of host page tables 122 to allow the guest 136 access to guest-allocated memory pages 214. In an example, memory manager 128 writes a page table entry into a host page table of set of host page tables 122. Processor 106 may make this page table entry writable and insert the host memory address to which a guest memory page is mapped into the page table entry. Accordingly, memory manager 128 that the plurality of guest-allocated memory pages 214 included in allocation request 218 is backed by host physical memory. In this way, memory manager 128 may map guest memory addresses to actual physical memory.”).
Regarding claim 18, is an independent storage medium claim correspond to method claim 1. Therefore, it is rejected for the same reasons. In addition, Tsirkin teaches a non-transitory machine-readable storage medium storing instructions which, when executed, cause a processing device executing a hypervisor to perform operations (see Fig. 1, Memory).
Regarding claim 19, is a storage medium claim correspond to method claim 3. Therefore, it is rejected for the same reasons.
Regarding claim 20, is a storage medium claim correspond to method claim 4. Therefore, it is rejected for the same reasons.
Claim(s) 2, 5, and 7-17 are rejected under 35 U.S.C. 103 as being unpatentable over Tsirkin et al. (U.S. PG PUB 2018/0150232) in view of Tsirkin et al. (U.S. PG PUB 2019/0370044).
Regarding claim 2, Tsirkin does not expressly disclose, however, Tsirkin ‘044 teaches wherein notifying the virtual machine of the guest memory page address further comprises notifying, via a message written to a shared memory shared between the hypervisor and the virtual machine, the virtual machine of the guest memory page address (see ¶ [0013] “For example, upon releasing a memory page of a guest memory by a guest operating system of a virtual machine, the virtual machine can transmit, to a hypervisor managing the virtual machine, a notification that the memory page is released and/or that the memory page is to be inaccessible. The virtual machine can also send, to the hypervisor, a request to notify the virtual machine of attempts to access the memory page and/or accesses to the memory page”).
Hence it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the teachings of Tsirkin by adapting Tsirkin ‘044 to efficiently manage address space and memory used by the virtual machine (see ¶ [0002] of Tsirkin ‘044).
Regarding claim 5, Tsirkin does not expressly disclose, however, Tsirkin ‘044 teaches wherein making the guest memory page inaccessible further comprises modifying a page table entry in a host page table (see ¶[0032] “. The host memory management component 132 can then define a parameter of the page table entry to indicate that the page table entry is invalid and/or that the memory page is inaccessible (e.g., “write-protected,” “non-present,” etc.). As such, attempts to access the memory page may cause a page fault.”).
Regarding claim 7, Tsirkin does not expressly disclose, however, Tsirkin ‘044 teaches wherein notifying the virtual machine of the guest memory page address further comprises having the virtual machine, responsive to receiving the guest memory page address notification, make the guest memory page referenced by the guest memory page address inaccessible by a guest application running on the virtual machine (see ¶[0041] “In some embodiments, the page protection module 346 may detect an attempt to access the memory page by the VM 350 (e.g., the guest OS of the VM 350) or any other device. The attempt to access may be detected by listening for page faults or in any other suitable manner. The page allocation module 346 may determine that the memory page is inaccessible in view of the access status parameter of the page table entry associated with the memory page (e.g., by determining that the value of the access status parameter is the first value).”).
Hence it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the teachings of Tsirkin by adapting Tsirkin ‘044 to efficiently manage address space and memory used by the virtual machine (see ¶ [0002] of Tsirkin ‘044).
Regarding claim 8, Tsirkin does not expressly disclose, however, Tsirkin ‘044 teaches wherein having the virtual machine make the guest memory page inaccessible by the guest application further comprises modifying a page table entry in a guest page table (see ¶[0032] “. The host memory management component 132 can then define a parameter of the page table entry to indicate that the page table entry is invalid and/or that the memory page is inaccessible (e.g., “write-protected,” “non-present,” etc.). As such, attempts to access the memory page may cause a page fault.”).
Hence it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the teachings of Tsirkin by adapting Tsirkin ‘044 to efficiently manage address space and memory used by the virtual machine (see ¶ [0002] of Tsirkin ‘044).
Regarding claim 9, Tsirkin does not expressly disclose, however, Tsirkin ‘044 teaches wherein the page fault notification indicates a page fault with respect to the guest memory page and is generated responsive to detecting the page fault by the virtual machine (see ¶ [0042] “In another implementation, the page protection module 346 can send, to the VM 350, a notification indicating the detection of the attempt to access the memory page (also referred to as the “second notification”). For example, the second notification may be an interrupt, message, exception, any other signal indicating the detection of the attempt to access the memory page, or a combination thereof. As another example, the page protection module 346 may store the second notification in the shared memory. The VM 350 can then retrieve the second notification from the shared memory.”).
Hence it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the teachings of Tsirkin by adapting Tsirkin ‘044 to efficiently manage address space and memory used by the virtual machine (see ¶ [0002] of Tsirkin ‘044).
Regarding claim 10, Tsirkin does not expressly disclose, however, Tsirkin ‘044 teaches wherein notifying the virtual machine of the accessibility of the guest memory page address further comprises having the virtual machine, responsive to receiving the notification of the accessibility of the guest memory page address, make the guest memory page accessible by a guest application (see ¶[0014] “In one implementation, the virtual machine can notify the hypervisor to render the memory page accessible (e.g., by marking the page table entry as “valid”) to use the memory page. In another implementation, the hypervisor can render the memory page accessible in view of the detection of the attempt to access the memory page. The virtual machine may receive the notification indicting the detection of the attempt to access the memory and skip the notification. The virtual machine can then use the memory page.”).
Hence it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the teachings of Tsirkin by adapting Tsirkin ‘044 to efficiently manage address space and memory used by the virtual machine (see ¶ [0002] of Tsirkin ‘044).
Regarding claim 11, Tsirkin does not expressly disclose, however, Tsirkin ‘044 teaches wherein having the virtual machine make the guest memory page accessible by the guest application further comprises modifying a page table entry in a guest page table (see ¶[0014] “In one implementation, the virtual machine can notify the hypervisor to render the memory page accessible (e.g., by marking the page table entry as “valid”) to use the memory page. In another implementation, the hypervisor can render the memory page accessible in view of the detection of the attempt to access the memory page.”).
Hence it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the teachings of Tsirkin by adapting Tsirkin ‘044 to efficiently manage address space and memory used by the virtual machine (see ¶ [0002] of Tsirkin ‘044).
Regarding claim 12, Tsirkin teaches a system comprising:
a memory (see Fig. 1 Memory);
a processing device executing a hypervisor and operatively coupled to the memory, the processing device to (see Fig. 1 Processor):
identify, by a hypervisor running on a host computer system, a guest memory page identified by a guest memory page address in a guest memory space of a virtual machine managed by the hypervisor (see ¶ [0020] “For example, when the guest allocates memory pages, it selects a guest memory address to use for a memory page and puts this guest memory address into the guest's set of page tables within the guest.”); wherein the virtual machine comprises a virtual central processing unit (CPU) emulated by the hypervisor (see ¶[0031] “Virtual machine 130 includes at least one guest 136, which may include a kernel, OS, and/or other application running on the virtual machine. A guest kernel of virtual machine 130 may provide core computing functionality, such as allocating memory pages of guest memory 132 to processes and/or threads, communicating I/O to and from virtual devices, managing a file system, handling interrupts, scheduling and running processes to execute instructions of computing tasks by a virtual processor, providing an interface between devices and software applications, and/or providing other important computing features.”);
make, by the hypervisor, the guest memory page inaccessible by the virtual machine (see ¶[0037] “ Additionally, hypervisor 120 may deallocate and unmap some of the guest memory pages that were previously allocated to guest 136 and backed up by host memory 108.”);
the virtual machine of the guest memory page address to have the virtual machine make the guest memory page inaccessible by a guest application running on the virtual machine (see ¶[0039] “For example, memory manager 128 may map a guest memory page to host memory 108 and at some later point in time, de-allocate and unmap this guest memory page because the total amount of the free host memory is low (e.g., below a threshold).”);
receiving, from the virtual machine via a communication channel in a data storage shared by the virtual machine and the hypervisor (see ¶[0038] “In an example, guest 136 sends a request to allocate a plurality of guest memory pages for guest 136 to hypervisor 120. I/O module 126 may receive the memory allocation request and pass it along to memory manager 128 for processing”), a page fault notification with respect to the guest memory page of the virtual machine (see ¶[0041] “] An attempted access to a guest memory page may cause a page fault for a variety of reasons. In an example, guest 136 may attempt to read a memory page that is not present in main memory.”); and
after and responsive to receiving the page fault notification map, by the hypervisor, a host memory page to the guest memory page (Note: The mapping occurs after and responsive to the page fault, as described in ¶[0041] that a guest attempts to read a memory page that is not present and thus a mapping later occurs, see ¶[0041] “An attempted access to a guest memory page may cause a page fault for a variety of reasons. In an example, guest 136 may attempt to read a memory page that is not present in main memory. In this example, an exit to hypervisor 120 may occur, and hypervisor 120 may detect the attempted read, allocate some host physical memory (e.g., random access memory (RAM) memory) corresponding to the attempted read, map guest memory pages to this allocated host physical memory, and perform the read on behalf of the guest.”)
wherein the notification of the page fault is generated by the virtual machine responsive to detecting the page fault with respect to the guest memory page (see ¶[0039] “In an example, a guest access to a guest memory page causes a page fault if the guest memory page is not mapped to a host memory page.”).
Tsirkin does not expressly disclose, however, Tsirkin ‘044 teaches notify, by a host CPU that is different from the virtual CPU (see ¶[0018] “As illustrated, host computer system 100 may include one or more processors 110 (e.g., host central processing units (CPUs)) communicatively coupled to memory devices 160”), via a first message written to a shared memory shared between the hypervisor and the virtual machine (see ¶ [0042] “For example, the second notification may be an interrupt, message, exception, any other signal indicating the detection of the attempt to access the memory page, or a combination thereof. As another example, the page protection module 346 may store the second notification in the shared memory. The VM 350 can then retrieve the second notification from the shared memory.”, see Fig. 3, the page protection module, 346 is on the host, therefore notification is by a host CPU).
Hence it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the teachings of Tsirkin by adapting Tsirkin ‘044 to efficiently manage address space and memory used by the virtual machine (see ¶ [0002] of Tsirkin ‘044).
Regarding claim 13, Tsirkin teaches wherein the processing device is further configured to: responsive to making the guest memory page inaccessible, assign the guest memory page to a second virtual machine managed by the hypervisor (see ¶[0029] “Set of host page tables 122 uses the entries to map one or more ranges of the host-physical memory addresses into one or more guest-physical address ranges that are assigned to virtual machine 130 as guest memory 132. Host-physical memory is hardware memory 108.”).
Regarding claim 14, Tsirkin teaches wherein the processing device is further configured to: responsive to mapping the host memory page to the guest memory page, notify the virtual machine of accessibility of the guest memory page address (see ¶ [0005] “Each page table entry stores one or more mappings of a guest memory address to host physical memory. The system further includes a memory manager that manages the set of host page tables, allocates a plurality of host memory pages, and maps the guest memory addresses included in the list to the plurality of host memory pages. The plurality of host memory pages is part of the host memory”).
Regarding claim 15, is a system claim correspond to method claim 10. Therefore, it is rejected for the same reasons.
Regarding claim 16, is a system claim correspond to method claim 5. Therefore, it is rejected for the same reasons.
Regarding claim 17, is a system claim correspond to method claim 8. Therefore, it is rejected for the same reasons.
Response to Arguments
Applicant's arguments filed 3/31/2026 have been fully considered but they are not persuasive.
Regarding 101 rejections, applicant argues that the amended limitations contribute to improvement of virtual machine management and a beneficial use of page fault notifications is to reduce page fault notifications with hypervisor, making improvement to the operations of virtual machines.
Examiner disagrees. The added limitations of “wherein the virtual machine comprises a virtual central processing unit (CPU) emulated by the hypervisor” and “by a host CPU that is different from the virtual CPU” is merely an additional element which is neither a practical application nor significantly more than the abstract idea, because they are generic computing component to apply the judicial exception which cannot provide an inventive concept.
Regarding 103 rejections, applicants argue that Tsirkin does not disclose a host CPU that is different from the virtual CPU, and that the host CPU does the notifying.
Examiner disagrees. Tsirkin teaches host hardware, such as a processor, is distinct from a virtual processor which is in the virtual machine.
see ¶ [0023] “Host machine 102 is coupled to host hardware 104. Host hardware 104 includes physical elements such as a processor 106 and a memory 108”
see ¶[0031] “Virtual machine 130 includes at least one guest 136, which may include a kernel, OS, and/or other application running on the virtual machine. A guest kernel of virtual machine 130 may provide core computing functionality, such as allocating memory pages of guest memory 132 to processes and/or threads, communicating I/O to and from virtual devices, managing a file system, handling interrupts, scheduling and running processes to execute instructions of computing tasks by a virtual processor, providing an interface between devices and software applications, and/or providing other important computing features.”
Tsirkin teaches that the host processor notifies the virtual machine of the guest memory pages by use of the memory manger that maps the guest memory address to the physical address.
see ¶ [0047] “Processor 106 may make this page table entry writable and insert the host memory address to which a guest memory page is mapped into the page table entry. Accordingly, memory manager 128 that the plurality of guest-allocated memory pages 214 included in allocation request 218 is backed by host physical memory. In this way, memory manager 128 may map guest memory addresses to actual physical memory.”
Support for Amendments and Newly Added Claims
Applicants are respectfully requested, in the event of an amendment to claims or submission of new claims, that such claims and their limitations be directly mapped to the specification, which provides support for the subject matter. This will assist in expediting compact prosecution. MPEP 714.02 recites: “Applicant should also specifically point out the support for any amendments made to the disclosure. See MPEP § 2163.06. An amendment which does not comply with the provisions of 37 CFR 1.121(b), (c), (d), and (h) may be held not fully responsive. See MPEP § 714.” Amendments not pointing to specific support in the disclosure may be deemed as not complying with provisions of 37 C.F.R. 1.121(b), (c), (d), and (h) and therefore held not fully responsive. Generic statements such as “Applicants believe no new matter has been introduced” may be deemed insufficient.
Interview Requests
In accordance with 37 CFR 1.133(a)(3), requests for interview must be made in advance. Interview requests are to be made by telephone (571-270-7848) call or email (carina.yun@uspto.gov). Applicants must provide a detailed agenda as to what will be discussed (generic statement such as “discuss §102 rejection” or “discuss rejections of claims 1-3” may be denied interview). The detail agenda along with any proposed amendments is to be written on a PTOL-413A or a custom form and should be emailed, (subject to MPEP 713.01.I / MPEP 502.03) to the Examiner prior to requesting for interview. Interview requests submitted within amendments may be denied because the Examiner was not notified, in advance, of the Applicant Initiated Interview Request and due to time constraints may not be able to review the interview request to prior to the mailing of the next Office Action.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Leveille et al. (US PG PUB 2007/0214340) teaches a symmetric multiprocessing fault-tolerant computer system controls memory access in a symmetric multiprocessing computer system. To do so, virtual page structures are created, where the virtual page structures reflect physical page access privileges to shared memory for processors in a symmetric multiprocessing computer system. Access to shared memory is controlled based on physical page access privileges reflected in the virtual paging structures to coordinate deterministic shared memory access between processors in the symmetric multiprocessing computer system. A symmetric multiprocessing fault-tolerant computer system may use duplication or continuous replay.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CARINA YUN whose telephone number is (571)270-7848. The examiner can normally be reached Mon, Tues, Thurs, 9-4 (EST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to call.
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Carina Yun
Patent Examiner
Art Unit 2194
/CARINA YUN/Examiner, Art Unit 2194
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