DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is Final and is in response to the claims filed 02/13/2026. Claims 1 and 5-31 are currently pending, of which claims 1 and 5-31 are currently rejected.
Response to Arguments
Applicant’s arguments filed 02/16/2026 have been fully considered.
Drawing objection: Objection to the drawings has been withdrawn necessitated by amendments.
35 U.S.C. 112(b): Claim rejections under 35 U.S.C. 112(b) have been withdrawn necessitated by amendments. However, see new 35 U.S.C. 112(b) rejection.
35 U.S.C. 103: Applicant’s arguments regarding the 35 U.S.C. 103 rejection have been fully considered, but they are not persuasive.
Applicant argues in page 11 of 16 that LaFrieda fails to teach or suggest the claimed fixed carry input structure. Applicant specifically argues “However, in LaFrieda, the disclosure that a carry-in (CIN) may be set to zero at a lowest-order slice merely describes an initial condition for initiating a carry propagation structure”, and “Accordingly, the carry input in LaFrieda is a signal whose value depends on internal carry generation and propagation, not a fixed input bit forming part of the input data itself.”
Examiner respectfully disagrees. As explained in the non-final rejection on 11/18/2025, LaFrieda explains “Additionally, for the lowest-order block, CIN is set to 0. For the remaining blocks, CIN is connected to the INT_COUT signal from the highest-order slice of the previous block.” See LaFrieda: ¶0076. Hence, LaFrieda teaches the carry-in (CIN) value to be set to 0 (fixed) when the block is the lowest-order block of the adder. There is no limitation in the claim that describes the fixed carry in value set to “0” outside the initial condition for using a carry propagation structure.
Applicant further argues in page 12 of 16 that amended claim 1 defines “a fundamentally different structure”. Applicant explains “This distinction is not merely a difference in numerical value, but a structural and architectural difference in how the carry value is supplied and used.”
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., a structural and architectural difference in how the carry value is supplied and used) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant further argues in page 12 of 16 that amended claim 1 does not rely on any inter-stage or inter-block carry propagation as disclosed in LaFrieda’s adder structure. Applicant explains “Such a carry propagation chain is a core aspect of LaFrieda's adder architecture. By contrast, amended claim 1 does not rely on any inter-stage or inter-block carry propagation. Instead, the least significant carry value is fixed at the input and used only in the summation of the least significant bit.”
Examiner respectfully disagrees. Examiner does not rely on the adder structure disclosed in LaFrieda. Instead, Examiner points to paragraph 0076 of LaFrieda to teach the limitation of the carry data being a fixed value of “0”. Combination of LaFrieda with Lokappa in view of Singh in view of Harris teach amended claim 1. See 35 U.S.C. 103 Rejection below.
Applicant further argues in pages 13 and 14 of 16 that Harris is directed to a fundamentally different circuit architectures. Applicant explains “In Harris, the least significant bit is defined and determined within a carry- generation and carry-propagation-based prefix network. Although certain figures illustrate that the LSB output may appear unchanged, this behavior results from the manner in which carry signals are generated, propagated, or suppressed within the prefix adder structure. In other words, the LSB value in Harris is a byproduct of a carry-propagation architecture, not a result of an input data structure that fixes the carry value.”
Examiner respectfully disagrees. Harris discloses a bitwise adder using a prefix adder structure, which is disclosed in the instant application. Further, Examiner points to the CIN value in Harris being inputted into the precomputation stage. Having a CIN input in adders allows for the stages of adders using outputs for previous stages as carry-in inputs for the next stage. Additionally, Combination of LaFrieda with Lokappa in view of Singh in view of Harris teach amended claim 1, including a fixed carry-in input. See 35 U.S.C. 103 Rejection below.
Applicant argues in page 14 of 16 that Harris does not teach a fixed input carry bit selectively combined with a second operand bit using a dedicated summation structure. Applicant explains “Moreover, Harris does not disclose or suggest a summation logic stage in which a fixed input carry bit is selectively combined with a second operand bit using a dedicated summation structure, such as the selectively disposed second-group XOR gate and inverter recited in the dependent claims. Rather, Harris integrates XOR and inverter elements as part of prefix cells that inherently rely on carry generation and propagation. Accordingly, even though Harris may show embodiments where the LSB output appears unchanged, Harris does not teach or suggest the claimed input-data-based fixed carry structure, nor does it render obvious the amended claim when properly construed.”
Examiner respectfully disagrees. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., fixed input carry bit is selectively combined with a second operand bit using a dedicated summation structure) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Further, Examiner relies on Russell in combination with Lokappa in view of Singh in view of Harris to teach limitations from claims 27-31 including XOR gates. See 35 U.S.C. 103 Rejection below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 5-31 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “including logic gates selected from the group consisting of an AND gate, an OR gate, and a buffer gate” It is unclear if Applicant intends the logic gates selected from the group to be either one of the recited gates, or all of them. For purposes of examination, it will be interpreted as either one of the recited gates. Further, there is insufficient antecedent basis for the limitation “the group” in the claim. Examiner suggests amending this limitation to read “including one logic gate selected from a group consisting of an AND gate, an OR gate, and a buffer gate”
Claims 5-31 inherit the same deficiency by reason of dependence.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 5-26 are rejected under 35 U.S.C. 103 as being unpatentable over Lokappa et al. (U.S. Patent Application Publication No.: US 20200167127 A1), hereinafter “Lokappa”, in view of Singh (U.S. Patent Application Publication No.: US 20120036172 A1), hereinafter “Singh”, further in view of Harris (U.S. Patent Application Publication No.: US 20040225706 A1), hereinafter “Harris”, further in view of LaFrieda et al. (U.S. Patent Application Publication No.: US 20220206758 A1), hereinafter “LaFrieda”.
Regarding Claim 1, Lokappa teaches:
[A] … binary adder for generating "N+1"-bit output data (N=2M, M is a natural number) by adding an "N"-bit second operand to a first operand having an "N"-bit … value (Fig. 6, e.g., shows adder 600 (binary adder) receiving operands A and B (second and first operands) and outputting Cout and Sout (N+1) output data), the … binary adder comprising:
a plurality of transfer logic stages, each of the plurality of transfer logic stages including logic gates selected from the group consisting of an AND gate, an OR gate, … (Fig. 6A, e.g., shows plurality of dot, or logic operations (transfer logic gates); Fig. 3, e.g., shows the logic gates represented by the dots; Fig. 3, e.g., shows AND / OR gates); and
a summation logic stage configured to generate the "N+1"-bit output data by using the "N"-bit second operand and transfer data that is generated through the plurality of transfer logic stages (Fig. 6B, e.g., shows sum circuit 630 (summation logic stage) outputting Sout 639 and Cout 638 (N+1 bit output data));
… a second input terminal to which "N+1"-bit input data is input (Fig. 6, e.g., shows adder receiving Addends through input terminal (second input terminal)); and
an output terminal from which the "N+1"-bit output data is output, wherein the "N+1"-bit input data is configured with the "N"-bit second operand … (Fig. 6, e.g., shows output signals 638 and 639 (output terminal) outputting Cout and Sout (N+1 -bit output data); ¶0060), …
and wherein the summation logic stage is configured to generate a least significant bit of the "N+1"-bit output data by using … a least significant bit of the "N"-bit second operand (Fig. 6, e.g., Sum circuit 630 (summation logic) generates S0 using least significant bits of operands A and B).
Lokappa does not teach:
A fixed binary adder for generating "N+1"-bit output data (N=2M, M is a natural number) by adding an "N"-bit second operand to a first operand having an "N"-bit fixed value, the fixed binary adder comprising:
… each of the plurality of transfer logic stages including logic gates selected from the group consisting of an AND gate, an OR gate, and a buffer gate;
a first input terminal and a second input terminal to which "N+1"-bit input data is input; and
… wherein the "N+1"-bit input data is configured with the "N"-bit second operand and 1-bit carry data,
wherein the 1-bit carry data constitutes a least significant bit of the "N+1"- bit input data,
wherein the "N"-bit second operand constitutes an "N+1"th bit to a second bit of the "N+1"-bit input data,
wherein the 1-bit carry data has a fixed binary value of "0,"
and wherein the summation logic stage is configured to generate a least significant bit of the "N+1"-bit output data by using the 1-bit carry data and a least significant bit of the "N"-bit second operand.
However, in the same field of endeavor, Singh teaches an expanded scope incrementor that adds a binary value by a constant binary value. Singh explains “However, in some computer systems, it is advantageous to add one of several different constant integers to a value... The following expanded scope incrementor invention provides an incrementor that may add numeric values of +0, +1, +2, +3, or +4 in a single operation.”(Singh: ¶0016)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the incrementor to add a constant value to an input value as disclosed by Singh with the Sum circuit 630 as disclosed by Lokappa. One would have been motivated to combine these references because both references disclose bitwise adders, and Singh enhances the model of Lokappa because “The expanded scope incrementor does not have the complexity of a full scale adder and, therefore, uses a much smaller area than a full scale adder. This results in the expanded scope incrementor using less power and fewer routing resources while executing faster than a full-scale adder.” Singh: ¶0016
Lokappa in view of Singh do not teach:
… each of the plurality of transfer logic stages including logic gates selected from the group consisting of an AND gate, an OR gate, and a buffer gate;
a first input terminal and a second input terminal to which "N+1"-bit input data is input; and
… wherein the "N+1"-bit input data is configured with the "N"-bit second operand and 1-bit carry data,
wherein the 1-bit carry data constitutes a least significant bit of the "N+1"- bit input data,
wherein the "N"-bit second operand constitutes an "N+1"th bit to a second bit of the "N+1"-bit input data,
wherein the 1-bit carry data has a fixed binary value of "0,"
and wherein the summation logic stage is configured to generate a least significant bit of the "N+1"-bit output data by using the 1-bit carry data and a least significant bit of the "N"-bit second operand.
However, Harris teaches:
… each of the plurality of transfer logic stages including logic gates selected from the group consisting of an AND gate, an OR gate, and a buffer gate (Fig. 4, e.g., shows a buffer being used after each last cell of the bit position);
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine buffer after each of the last cell of each bit position as taught by Harris with the primary carry bit generation circuit 620 as taught by Lokappa in view of Singh. One would have been motivated to combine these references because both references disclose bitwise adders using a prefix adder structure, and Harris enhances the model of Lokappa in view of Singh because “White buffers are used to reduce the loading of later non-critical stages on the critical path." Harris: ¶0012
Harris further teaches:
… wherein the "N+1"-bit input data is configured with the "N"-bit second operand and 1-bit carry data (Fig. 1, e.g., Precomputation stage receives Cin value (through a terminal), then it is inputted to prefix network),
wherein the 1-bit carry data constitutes a least significant bit of the "N+1"- bit input data (Fig. 1, e.g., Precomputation stage receives Cin value (through a terminal), then it is inputted to prefix network),
wherein the "N"-bit second operand constitutes an "N+1"th bit to a second bit of the "N+1"-bit input data (Fig. 1, e.g., Precomputation stage receives Cin value and input A4:1, then it is inputted to prefix network. MSB of Addend A is "N+1"th bit), …
and wherein the summation logic stage is configured to generate a least significant bit of the "N+1"-bit output data by using the 1-bit carry data (Fig. 1, e.g., shows Cin being inputted as the LSB to the prefix network, Postcomputation stage outputs sum outputs (using carry-in bit); Fig. 4, e.g., shows LSB (carry-in) being directly outputted; ) …
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the input terminal to receive a Cin value as disclosed by Harris with the signal generation circuit 610 as disclosed by Lokappa in view of Singh in view of Harris. One would have been motivated to combine these references because both references disclose bitwise adders using a prefix adder structure, and Harris enhances the model of Lokappa in view of Singh in view of Harris by allowing for the adder to receive carry input from a possible previous computation.
Lokappa in view of Singh in view of Harris do not teach:
wherein the 1-bit carry data has a fixed binary value of "0,"
However, in the same field of endeavor, LaFrieda teaches how the lowest order block of a multi-stage addition operation can have the carry in value set to “0”. LaFrieda explains “Additionally, for the lowest-order block, CIN is set to 0. For the remaining blocks, CIN is connected to the INT_COUT signal from the highest-order slice of the previous block.” See LaFrieda: ¶0076
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the Carry in value be set to “0” as taught by LaFrieda with the Cin value inputted in the adder as taught by Lokappa in view of Singh in view of Harris. One would have been motivated to combine these references because both references disclose bitwise adders, and LaFrieda enhances the model of Lokappa in view of Singh in view of Harris by setting the Cin value to “0” for accurate adder calculations if there is no lower order adder.
Regarding Claim 5, Lokappa in view of Singh in view of Harris in view of LaFrieda teach:
The fixed binary adder of claim 3, wherein each of the plurality of transfer logic stages and summation logic stage has "N+1" bit positions corresponding to each of the "N+1"-bit input data (Lokappa: Fig. 6A, e.g., Each Stage has corresponding logic for each bit position; Harris: Fig. 1, e.g., Precomputation stage receives Cin value, then it is inputted to prefix network; Combination would cause for each stage taught by Lokappa to have an extra bit position for Cin value as taught by Harris (N+1)).
The motivation to combine provided with respect to claim 1 applies equally to claim 5.
Regarding Claim 6, Lokappa in view of Singh in view of Harris in view of LaFrieda teach:
The fixed binary adder of claim 5, wherein the number of the plurality of transfer logic stages is set to "M" (Lokappa: Fig. 6A, e.g., shows 5 stages (M stages)).
Regarding Claim 7, Lokappa in view of Singh in view of Harris in view of LaFrieda teach:
The fixed binary adder of claim 5, wherein a first transfer logic stage, among the plurality of transfer logic stages, is configured to receive the "N+1"-bit input data and output "N+1"-bit first transfer data (Lokappa: Fig. 6A, e.g., Each Stage has corresponding logic for each bit position; Harris: Fig. 1, e.g., Precomputation stage receives Cin value, then it is inputted to prefix network; Combination would cause for each stage taught by Lokappa to have an extra bit position for Cin value as taught by Harris (N+1)).
The motivation to combine provided with respect to claim 1 applies equally to claim 7.
Regarding Claim 8, Lokappa in view of Singh in view of Harris in view of LaFrieda teach:
The fixed binary adder of claim 7, wherein , at each "P"th bit position (where "P" is N+1, N, ..., 3) among the "N+1" bit positions of the first transfer logic stage, one of the AND gate, the OR gate, and the buffer gate is disposed as the logic gate (Lokappa: Fig. 6A, e.g., each bit position in each stage has logic operations; Fig. 3, e.g., shows logic gates used for each dot/logic operation),
wherein the buffer gate is disposed as the logic gate at a second bit position of the first transfer logic stage (Lokappa: Fig. 6A, e.g., shows Stage 1 not using any dot/logic operation in the first bit position; Harris: Fig. 4, e.g., shows a buffer being used after each last cell of the bit position; Combination would cause for the first bit position taught by Lokappa to be considered the second bit position, and the carry in bit taught by Harris would be the first bit position), and
wherein a logic gate is not disposed at a first bit position of the first transfer logic stage (Harris: Fig. 4, e.g., no logic is used in the carry-in bit position).
The motivation to combine provided with respect to claim 1 applies equally to claim 8.
Regarding Claim 9, Lokappa in view of Singh in view of Harris in view of LaFrieda teach:
The fixed binary adder of claim 8, wherein the AND gate or the OR gate that is disposed at the "P"th bit position of the first transfer logic stage is configured to receive a "P"th bit and a "P-1"th bit of the "N+1"-bit input data (Lokappa: Fig. 6A, e.g., shows Stage 1 using black dots (AND/OR gates); Fig. 3, e.g., shows AND gate receiving Ph and Pi ("P"th bit and "P-1"th bit) to output Pj ("N+1"-bit)).
Regarding Claim 10, Lokappa in view of Singh in view of Harris in view of LaFrieda teach:
The fixed binary adder of claim 9, wherein the AND gate disposed at the "P"th bit position of the first transfer logic stage is configured to perform an AND operation on the "P"th bit and the "P- 1"th bit of the "N+1"-bit input data and configured to output a result of the AND operation as a "P"th bit of the "N+1"-bit first transfer data (Lokappa: Fig. 6A, e.g., shows Stage 1 (first transfer logic stage) using black dots (AND/OR gates) receiving data from current bit position ("P"th -bit) and data from lower bit position ("P-1"th -bit); Fig. 3, e.g., shows AND gate in black dot receiving Pi and Ph ("P"th bit and "P-1"th bit) to output Pj ("N+1"-bit first transfer data)).
Regarding Claim 11, Lokappa in view of Singh in view of Harris in view of LaFrieda teach:
The fixed binary adder of claim 9, wherein the OR gate disposed at the "P"th bit position of the first transfer logic stage is configured to perform an OR operation on the "P"th bit and the "p-1"th bit of the "N+1"-bit input data and configured to output a result of the OR operation as the "P"th bit of the "N+1"-bit first transfer data (Lokappa: Fig. 6A, e.g., shows Stage 1 (first transfer logic stage) using black dots (AND/OR gates) receiving data from current bit position ("P"th -bit) and data from previous bit position ("P-1"th -bit); Fig. 3, e.g., shows OR gate in black dot receiving Gi and Gh ("P"th bit and "P-1"th bit) to output Pj ("N+1"-bit first transfer data)).
Regarding Claim 12, Lokappa in view of Singh in view of Harris in view of LaFrieda teach:
The fixed binary adder of claim 8, wherein the buffer gate disposed at the "P"th bit position of the first transfer logic stage is configured to receive the "P"th bit of the "N+1"-bit input data (Lokappa: Fig. 6A, e.g., shows Stage 1 (first transfer logic stage) not using any dot/logic operation in the last bit position (“P”th bit position); Harris: Fig. 4, e.g., shows a buffer being used after each last cell of the bit position).
The motivation to combine provided with respect to claim 1 applies equally to claim 12.
Regarding Claim 13, Lokappa in view of Singh in view of Harris in view of LaFrieda teach:
The fixed binary adder of claim 12, wherein the buffer gate disposed at the "P"th bit position of the first transfer logic stage is configured to output the "P"th bit of the "N+1"-bit input data as the "P"th bit of the "N+1"-bit first transfer data (Lokappa: Fig. 6A, e.g., shows Stage 1 (first transfer logic stage) not using any dot/logic operation in the last bit position (“P”th bit position), each stage directly outs bits corresponding to their bit position, respectively, to the next stage; Harris: Fig. 4, e.g., shows a buffer being used after each last cell of the bit position).
The motivation to combine provided with respect to claim 1 applies equally to claim 13.
Regarding Claim 14, Lokappa in view of Singh in view of Harris in view of LaFrieda teach:
The fixed binary adder of claim 8, wherein the buffer gate disposed at the second bit position of the first transfer logic stage is configured to output a second bit of the "N+1"-bit input data as a second bit of the "N+1"-bit first transfer data (Lokappa: Fig. 6A, e.g., shows Stage 1 not using any dot/logic operation in the first bit position, each stage directly outs bits corresponding to their bit position, respectively, to the next stage; Harris: Fig. 4, e.g., shows a buffer being used after each last cell of the bit position; Combination would cause for the first bit position taught by Lokappa to be considered the second bit position, and the carry in bit taught by Harris would be the first bit position).
The motivation to combine provided with respect to claim 1 applies equally to claim 14.
Regarding Claim 15, Lokappa in view of Singh in view of Harris in view of LaFrieda teach:
The fixed binary adder of claim 8, wherein the first transfer logic stage is configured such that, at the first bit position of the first transfer logic stage, the first bit of the "N+1"-bit input data is output as the first bit of the "N+1"-bit first transfer data (Lokappa: Fig. 6A, e.g., Stage 1 (first transfer logic stage) is directly outputted to the second stage).
Regarding Claim 16, Lokappa in view of Singh in view of Harris in view of LaFrieda teach:
The fixed binary adder of claim 5, wherein a "K"th transfer logic stage ("K" is a natural number greater than or equal to 2 and less than or equal to "M"), among the plurality of transfer logic stages, is configured to receive "N+1"-bit "K-1"th transfer data that is output from a "K-1"th transfer logic stage and configured to output "N+1"-bit "K"th transfer data (Lokappa: Fig. 6A, e.g., shows Stage 4 ("K"th transfer logic stage) receiving MSB (N+1 bit) that is output from previous stage ("K-1"th transfer logic stage)).
Regarding Claim 17, Lokappa in view of Singh in view of Harris in view of LaFrieda teach:
The fixed binary adder of claim 16, wherein, at each "P"th bit position (where "P" is N+1, N, ..., 2K-1+) among the "N+1" bit positions of the "K"th transfer logic stage, one of the AND gate, the OR gate, and the buffer gate is disposed as the logic gate (Lokappa: Fig. 6A, e.g., each bit position in each stage has logic operations; Fig. 3, e.g., shows logic gates used for each dot/logic operation),
wherein the buffer gate is disposed as the logic gate at a "2K-1+1"th bit position of the "K"th transfer logic stage (Lokappa: Fig. 6A, e.g., shows Stage 4 (K"th transfer logic stage) not using any dot/logic operation in the first bit position; Harris: Fig. 4, e.g., shows a buffer being used after each last cell of the bit position), and
wherein a logic gate is not disposed at "2K-1"th to first bit positions of the "K"th transfer logic stage (Harris: Fig. 4 e.g., no logic is used in the carry-in bit position).
The motivation to combine provided with respect to claim 1 applies equally to claim 17.
Regarding Claim 18, Lokappa in view of Singh in view of Harris in view of LaFrieda teach:
The fixed binary adder of claim 17, wherein the AND gate or the OR gate that is disposed at the "P"th bit position of the "K"th transfer logic stage is configured to receive a "P"th bit and a "P-2K-1"th bit of the "N+1"-bit "K-1"th transfer data (Lokappa: Fig. 6A, e.g., shows Stage 4 (“K”th transfer logic stage) using black dots (AND/OR gates); Fig. 3, e.g., shows AND gate receiving Ph and Pi ("P"th bit and "P-1"th bit) to output Pj ("N+1"-bit)).
Regarding Claim 19, Lokappa in view of Singh in view of Harris in view of LaFrieda teach:
The fixed binary adder of claim 18, wherein the AND gate disposed at the "P"th bit position of the "K"th transfer logic stage is configured to perform an AND operation on the "P"th bit and the "P-2K- 1"th bit of the "N+1"-bit "K-1"th transfer data and configured to output a result of the AND operation as a "P"th bit of the "N+1"-bit "K"th transfer data (Lokappa: Fig. 6A, e.g., shows Stage 4 (“K”th transfer logic stage) using black dots (AND/OR gates) receiving data from current bit position ("P"th -bit) and data from lower bit position ("P-1"th -bit); Fig. 3, e.g., shows AND gate in black dot receiving Pi and Ph ("P"th bit and "P-1"th bit) to output Pj ("N+1"-bit “K”th first transfer data)).
Regarding Claim 20, Lokappa in view of Singh in view of Harris in view of LaFrieda teach:
The fixed binary adder of claim 18, wherein the OR gate disposed at the "P"th bit position of the "K"th transfer logic stage is configured to perform an OR operation on the "P"th bit and the "P-2K-1"th bit of the "N+1"-bit "K-1"th transfer data and configured to output a result of the OR operation as the "P"th bit of the "N+1"-bit "K-1”th transfer data (Lokappa: Fig. 6A, e.g., shows Stage 4 (“K” transfer logic stage) using black dots (AND/OR gates) receiving data from current bit position ("P"th -bit) and data from previous bit position ("P-1"th -bit); Fig. 3, e.g., shows OR gate in black dot receiving Gi and Gh ("P"th bit and "P-1"th bit) to output Pj ("N+1"-bit “K-1”th first transfer data)).
Regarding Claim 21, Lokappa in view of Singh in view of Harris in view of LaFrieda teach:
The fixed binary adder of claim 17, wherein the buffer gate disposed at a "2K-1+1"th bit position of the "K"th transfer logic stage is configured to receive the "P"th bit of the "N+1"-bit "K-1"th transfer data (Lokappa: Fig. 6A, e.g., shows Stage 4 (“K”th transfer logic stage) not using any dot/logic operation in the last bit position (“P”th bit position); Harris: Fig. 4, e.g., shows a buffer being used after each last cell of the bit position).
The motivation to combine provided with respect to claim 1 applies equally to claim 21.
Regarding Claim 22, Lokappa in view of Singh in view of Harris in view of LaFrieda teach:
The fixed binary adder of claim 21, wherein the buffer gate disposed at the "P"th bit position of the "K"th transfer logic stage is configured to output the "P"th bit of the "N+1"-bit "K-1"th transfer data as the "p"th bit of the "N+1"-bit "K"th transfer data (Lokappa: Fig. 6A, e.g., shows Stage 4 (“K”th transfer logic stage) not using any dot/logic operation in the last bit position (“P”th bit position), each stage directly outs bits corresponding to their bit position, respectively, to the next stage; Harris: Fig. 4, e.g., shows a buffer being used after each last cell of the bit position).
The motivation to combine provided with respect to claim 1 applies equally to claim 22.
Regarding Claim 23, Lokappa in view of Singh in view of Harris in view of LaFrieda teach:
The fixed binary adder of claim 17, wherein the buffer gate disposed at the "2K-1+1"th bit position of the "K"th transfer logic stage is configured to output a "2K-1+1"th bit of the "N+1"-bit "K-1"th transfer data as a "2K-1+1"th bit of the "N+1"-bit "K"th transfer data (Lokappa: Fig. 6A, e.g., shows Stage 4 (“K”th transfer logic stage) not using any dot/logic operation in some bit positions (“2K-1”th bit position), each stage directly outs bits corresponding to their bit position, respectively, to the next stage; Harris: Fig. 4, e.g., shows a buffer being used after each last cell of the bit position (non-critical paths)).
The motivation to combine provided with respect to claim 1 applies equally to claim 23.
Regarding Claim 24, Lokappa in view of Singh in view of Harris in view of LaFrieda teach:
The fixed binary adder of claim 17, wherein the "K"th transfer logic stage is configured such that "2K-1"th to first bits of the "N+1"-bit "K-1"th transfer data is output as "2K-1"th to first bits of the "N+1"-bit "K”th transfer data at the "2K-1"th to first bit positions, respectively (Lokappa: Fig. 6A, e.g., Stage 4 (“K”th transfer logic stage) directly outs bits corresponding to their bit position, respectively, to the next stage).
Regarding Claim 25, Lokappa in view of Singh in view of Harris in view of LaFrieda teach:
The fixed binary adder of claim 5, wherein the "M"th transfer logic stage, among the plurality of transfer logic stages, is configured to output "N+1"-bit "M"th transfer data (Lokappa: Fig. 6A, e.g., shows Stage 5 ("M"th transfer logic stage) outputting odd carry bits C21:1 ("N+1" -bit "M"th transfer data)), and wherein the summation logic stage is configured to receive the "N+1"-bit "M"th transfer data and the "N"-bit second operand and configured to output the "N+1"-bit output data (Lokappa: Fig. 6B, e.g., shows sum circuit 630 (summation logic stage) receiving carry bits from Stage 5 and Operand A (second operand)).
Regarding Claim 26, Lokappa in view of Singh in view of Harris in view of LaFrieda teach:
The fixed binary adder of claim 25, wherein the summation logic stage is configured to output an "N+1"th bit of the "N+1"-bit "M"th transfer data as an "N+1"th bit of the "N+1"-bit output data at the "N+1"th bit position (Lokappa: Fig. 6B, e.g., shows sum circuit 630 (summation logic stage) outputting Cout ("N+1"th bit position)).
Claims 27-31 are rejected under 35 U.S.C. 103 as being unpatentable over Lokappa in view of Singh in view of Harris in view of LaFrieda, further in view of Russell (U.S. Patent No.: US 4417315 A), hereinafter “Russell”.
Regarding Claim 27, Lokappa in view of Singh in view of Harris in view of LaFrieda teach:
The fixed binary adder of claim 26, wherein the summation logic stage includes "N" logic circuits disposed at the "N"th to first bit positions (Singh: Fig. 2, e.g., Incrementor 222 has sections INCR[N-1:0] (“N” logic circuits) for each bit position; ¶0020, e.g., Incrementor 222 receives and outputs a bit for each bit position),
Lokappa in view of Singh in view of Harris in view of LaFrieda do not teach:
wherein each of the "N" logic circuits is configured with XOR gates of a first group or configured with XOR gates of a second group and a NOT gate.
However, Russell teaches:
wherein each of the "N" logic circuits is configured with XOR gates of a first group or configured with XOR gates of a second group and a NOT gate (Fig. 2, e.g., shows incrementing circuit using a NOT gate and an XOR gate outputting SUM(N+1) (interpreted as second group), and an XOR gate outputting SUM IN value (interpreted as first group)).
Additionally, Singh suggests that the incrementor may be modified to produce a carry bit. See Singh: ¶0020. Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the incrementor circuit as taught by Russell with the Incrementor 222 as taught by Lokappa in view of Singh in view of Harris in view of LaFrieda. One would have been motivated to combine these references because both references disclose bitwise adders, and Russell enhances the model of Lokappa in view of Singh in view of Harris in view of LaFrieda by allowing for the incrementor to produce carry bits, and to perform bitwise addition operation with less delay. See Russell Column 1 Lines 36-47.
Regarding Claim 28, Lokappa in view of Singh in view of Harris in view of LaFrieda in view of Russell teach:
The fixed binary adder of claim 27, wherein the XOR gate of the first group is disposed at a selected "P"th bit position ("P" is an integer selected from N, ..., 1) of the summation logic stage, and is configured to receive a "P"th bit of the "N+1"- bit "M"th transfer data through a first input terminal and configured to receive a "P"th bit of the "N"-bit second operand through a second input terminal (Lokappa: Fig. 6B, e.g., sum circuit 630 receives operand A (second operand through a second input terminal) and the carry data (transfer data through a first input terminal); Russell: Fig. 2, e.g., shows XOR gate receiving carry in data 30 and input in data 40).
The motivation to combine provided with respect to claim 27 applies equally to claim 28.
Regarding Claim 29, Lokappa in view of Singh in view of Harris in view of LaFrieda in view of Russell teach:
The fixed binary adder of claim 28, wherein the XOR gate of the first group is disposed at the selected "P"th ("P" is an integer selected from N, ..., 1) bit position of the summation logic stage, and is configured to perform an XOR operation on the "P"th bit of the "N+1"-bit "M"th transfer data and the "P"th bit of the "N"-bit second operand and configured to output a result of the XOR operation as a "P"th bit of the "N+1"-bit output data (Lokappa: Fig. 6B, e.g., sum circuit 630 receives operand A (second operand through a second input terminal) and the carry data (transfer data through a first input terminal); Russell: Fig. 2, e.g., shows XOR gate receiving carry in data 30 and input in data 40).
The motivation to combine provided with respect to claim 27 applies equally to claim 29.
Regarding Claim 30, Lokappa in view of Singh in view of Harris in view of LaFrieda in view of Russell teach:
The fixed binary adder of claim 27, wherein the XOR gate of the second group is disposed at a selected "P"th bit position ("P" is an integer selected from N, ..., 1) of the summation logic stage, and includes a first input terminal that receives the "P"th bit of the "N+1"-bit "M"th transfer data and a second input terminal that is coupled to an output terminal of the NOT gate (Lokappa: Fig. 6B, e.g., sum circuit 630 receives operand A (second operand through a second input terminal) and the carry data (transfer data through a first input terminal); Russell: Fig. 2, e.g., shows XOR gate receiving carry signal 36 and output from NOT gate 48), and
wherein the NOT gate is configured to receive the "P"th bit of the "N"-bit second operand (Russell: Fig. 2, e.g., NOT gate 48 receives input (N+1)).
The motivation to combine provided with respect to claim 27 applies equally to claim 30.
Regarding Claim 31, Lokappa in view of Singh in view of Harris in view of LaFrieda in view of Russell teach:
The fixed binary adder of claim 30, wherein the XOR gate of the second group is disposed at the selected "P"th bit position ("P" is an integer selected from N, ..., 1) of the summation logic stage, and is configured to perform an XOR operation on the "P"th bit of the "N+1"-bit "M"th transfer data and an inverted bit of the "P"th bit of the "N"-bit second operand and configured to output a result of the XOR operation as the "P"th bit of the "N+1"-bit output data (Lokappa: Fig. 6B, e.g., sum circuit 630 (summation logic stage) receives operand A and the carry data; Russell: Fig. 2, e.g., shows XOR gate receiving carry signal 36 and output from NOT gate 48, and XOR gate 44 outputs SUM(N+1)).
The motivation to combine provided with respect to claim 27 applies equally to claim 31.
Prior Art Made of Record
US 12524204 B1 – teaches a multiplier array wherein each cell of the array includes a 1-bit full adder and an AND gate, wherein at least one of the 1-bit full adder and/or the AND gate. See Fig. 3 and corresponding description.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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/C.H.D./
Carlos H. De La Garza
Examiner, Art Unit 2182
/EMILY E LAROCQUE/Primary Examiner, Art Unit 2182
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