DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 1, 2025 has been entered.
Response to Arguments
Applicant’s arguments with respect to Claims 1 through 6, 12 through 15 and 18, have been fully considered, but are now moot because the following new grounds of rejections do not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
Claims 1, 6, 12, 14 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication 2014/0083743 to Ishida et al (hereinafter “Ishida”) in view of the teachings of U.S. Publication 2014/0360760 to Kiwanami et al (hereinafter “Kiwanami”), U.S. Patent 6,631,556 to Burgess (hereinafter “Burgess”), and U.S. Publication 2008/0067160 to Suutarinen (hereinafter “Suutarinen”).
Claim 1: Ishida discloses a method for making a printed circuit board, comprising:
forming a slot (e.g. 373, Fig. 4M) in a substrate by laser drilling, the substrate having multiple layers of traces (e.g. 356, 355, 365, 366) and insulators (e.g. 340, 360, 370) including an internal trace (e.g. 330), the substrate having a first (top) side and a second (bottom) side and having at least three layers (e.g. 340, 360, 370, etc.), the slot extending through at least two of the at least three layers (e.g. Fig. 4M) from the first side and terminating prior to intersecting the second side of the substrate such that the slot is blind, the slot having a length and a width, the slot having a bottom and a perimeter sidewall (e.g. 4O, ¶ [0031]);
coating (e.g. plating) the perimeter sidewall of the substrate with a conductive layer (e.g. 30, Fig. 4P, ¶ [0033]);
dicing or cutting the bottom of the slot (e.g. ¶ [0037]); and
separating the conductive layer into at least two separate conductive segments (e.g. left 20 and right 20, in Fig. 4T) that are electrically isolated from each other along the perimeter sidewall of the substrate for providing an electrical connection between the internal trace and an external trace (e.g. 30, 21, 22, ¶¶ [0035] to [0037]).
Claim 6: Ishida discloses the method of claim 1, wherein the slot has a floor (Fig. 4P), and further comprising coating the floor with the conductive layer, and wherein separating the conductive layer is defined further as removing a portion of the conductive layer on the floor of the slot (e.g. Figs. 4S to 4T).
Claim 12: Ishida discloses the method of claim 1, further comprising one additional layer (e.g. 375) covering the slot in the substrate, such that the slot is in a buried configuration (e.g. Fig. 4O).
Claim 14: Ishida discloses the method of claim 1, further comprising introducing a filling material (e.g. 246) into the slot (Fig. 2E).
Ishida does not teach that the slot is formed by a router. Moreover, due to only a cross-sectional view of the slot shown by Ishida, Ishida does not appear to mention that the slot includes a length that is greater than the width with the perimeter sidewall surrounding the slot, and a portion of the perimeter sidewall is linear along the length of the slot. Lastly, Ishida does not mention that a laser is applied to the bottom of the slot.
Kiwanami discloses that a slot (e.g. 80Y, Fig. 11A) can be formed with a router as an alternative to laser drilling (e.g. ¶ [0118]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have substituted the router of Kiwanami for the laser drilling of Ishida, as an alternative well-known process to form a slot in an art-recognized equivalent printed circuit board.
Burgess slots that are blind can have many different shapes (Fig. 27). Once such shape is to have the slot (13A or 13A’, Fig. 27) such that a length is greater that a width with a perimeter sidewall surrounding the slot, and a portion of the perimeter sidewall is linear along the length of the slot (e.g. plan views of 13A, 13A’ in Fig. 27, col. 13, lines 5-15). The benefit of this allows various shapes of terminals (i.e. elongated ones) to connect with the printed circuit board.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the slot of Ishida by forming it in the shape taught by Burgess, to positively allow the printed circuit board to have elongated connections.
Regarding Claim 18, from the shape of the slot taught by Burgess, it appears that the length is much greater than the width in Burgess’s the plan view of Figure 27. It would have been an obvious matter of design choice to choose any desired ratio of length to width of the slot, since Applicant’s have not disclosed that the claimed ratio of 2.85 solves any stated problem or is for any particular purpose and it appears that the invention would perform equally well with the ratio taught by Burgess.
In Ishida, the dicing or cutting that is applied to the bottom of the slot is done so to form individual printed circuit boards. Suutarinen teaches that a laser can be applied to the bottom of the slot to form individual printed circuit boards (e.g. ¶ [0034]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the dicing or cutting of Ishida by using a laser that is applied to the bottom of the slot, as taught by Suutarinen, to achieve the same purpose of forming individual printed circuit boards.
Claims 2 through 5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Ishida in view of Kiwanami, Burgess, and Suutarinen as applied to Claim 1 above, and further in view of U.S. Publication 2009/0017647 to Horiuchi (hereinafter “Horiuchi”).
Ishida, as modified by Kiwanami, Burgess, and Suutarinen disclose the claimed manufacturing method as relied upon above in Claim 1.
Regarding Claim 2, the modified Ishida method does not teach separating of the conductive layer includes creating at least one cross-slot by removing a first portion of the conductive layer and the substrate and a second portion of the conductive layer and the substrate.
Regarding Claims 5 and 13, the modified Ishida method does not teach separating of the conductive layer includes using a bit or a tool that can be moved in at least two different lateral directions within the substrate to remove portions of the conductive layer and/or the substrate.
Horiuchi discloses a process of making a circuit board (e.g. Figs. 3 to 4) that includes a slot (e.g. 14) and a conductive layer (e.g. 16) where separating the conductive layer is defined by creating at least one cross-slot (e.g. 30) by removing a first portion of the conductive layer and the substrate and a second portion of the conductive layer and the substrate (e.g. dotted lines in Fig. 3). Horiuchi uses a bit (tool) that can be moved in at least two different lateral directions within the substrate to remove portions of the conductive layer and the substrate (e.g. ¶ [0013]). Such a slot arrangement allows for connections to a variety of other electrical components (e.g. fuses, etc., ¶ [0002]).
Regarding Claims 3 and 4, Horiuchi further teaches that the slot has the first portion and the second portion aligned, located on opposite sides of the slot, and spaced apart along the length of the slot (plan views of Figs. 3, 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the slot of Ishida by adding a cross-slot with first and second portions removed by using a bit or tool, as taught by the process of Horiuchi, to positively allow the circuit board to be connected to a variety of components.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Ishida in view of Kiwanami, Suutarinen and Burgess as applied to Claim 1 above, and further in view of U.S. Publication 2005/0062160 to Naito et al (hereinafter “Naito”).
Ishida, as modified by Kiwanami, Burgess and Suutarinen, disclose the claimed manufacturing method as relied upon above in Claim 1, further including that the thin-film substrate appears to be rigid. The modified Ishida method does not mention that the substrate is a flexible thin-film substrate.
Printed circuit boards that include at least one blind slot having a thin-film substrate that is flexible is conventional and notoriously well-known in the art. As an example, Naito disclose such a feature to allow the circuit board to be used in a variety of applications (e.g. electronic and information appliances, ¶¶ [0098], [0099]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the thin-film substrate of Ishida by using a thin-film substrate that is flexible, as taught by Naito, to provide a conventional well-known printed circuit board having a variety of applications in a number of appliances.
Allowable Subject Matter
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 7 through 11 and 16 are allowed.
Conclusion
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/A. DEXTER TUGBANG/Primary Examiner
Art Unit 2896