DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I and Species I (claims 1-4,8-18, and 22-24) in the reply filed on 12/29/2025 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/29/2022 and 10/16/2025 was filed after the mailing date of the non-final action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 and 8-12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 and 4-7 and 9 of U.S. Patent No. 12,550,373 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims are anticipated by the reference claims as illustrated below and as directed to Figure 1C of both applications.
U.S. Patent No. 12,550,373 B2.
Instant Application
1. (Original) A semiconductor structure comprising: an upper device stacked over a lower device, wherein the upper device comprises (i) a first source region, (ii) a first drain region, (iii) a body of semiconductor material extending laterally from the first source region to the first drain region, and (iv) a first gate structure at least in part wrapped around the body, and wherein the lower device comprises (i) a second source region, (ii) a second drain region, and (iii) a second gate structure at least in part laterally between the second source region and the second drain region, and wherein the lower device lacks a body of semiconductor material extending laterally from the second source region to the second drain region.
1. (Original) A semiconductor structure comprising: a second device stacked over a first device, wherein the first device comprises (i) a first source region, (ii) a first drain region, (iii) a body of semiconductor material extending laterally from the first source region to the first drain region, and (iv) a first gate structure at least in part wrapped around the body, wherein the second device comprises (i) a second source region, (ii) a second drain region, and (iii) a second gate structure at least in part laterally between the second source region and the second drain region, and wherein the second device lacks a body of semiconductor material extending laterally from the second source region to the second drain region.
4. The semiconductor structure of claim 1, wherein the body is a first body, and wherein the lower device comprises a discontinuous second body comprising (i) a first end section in contact with the second source region, and (ii) a second end section in contact with the second drain region, the second body lacking a middle region between the first end section and the second end section.
8. The semiconductor structure of claim 1, wherein the body is a first body, and wherein the second device comprises a discontinuous second body comprising (i) a first end section in contact with the second source region, and (ii) a second end section in contact with the second drain region, the second body lacking a middle region between the first end section and the second end section.
5. The semiconductor structure of claim 4, wherein the second gate structure includes (i) a gate electrode, and (ii) gate dielectric material that is between the gate electrode and the first end section of the second body, and that is also between the gate electrode and the second end section of the second body.
9. The semiconductor structure of claim 8, wherein the second gate structure includes (i) a gate electrode, and (ii) gate dielectric material that is between the gate electrode and the first end section of the second body, and that is also between the gate electrode and the second end section of the second body.
6. (Original) The semiconductor structure of claim 4, further comprising: a gate spacer separating the first gate structure from the first source region, and separating the second gate structure from the second source region, wherein the first end section of the second body is at least in part wrapped around by the gate spacer.
10. (Original) The semiconductor structure of claim 8, further comprising: a gate spacer separating the first gate structure from the first source region, and separating the second gate structure from the second source region, wherein the first end section of the second body is at least in part wrapped around by the gate spacer.
7. (Original) The semiconductor structure of claim 6, wherein the gate spacer is a first gate spacer, and wherein the semiconductor structure further comprises: a second gate spacer separating the first gate structure from the first drain region, and separating the second gate structure from the second drain region, wherein the second end section of the second body is at least in part wrapped around by the second gate spacer.
11. (Original) The semiconductor structure of claim 10, wherein the gate spacer is a first gate spacer, and wherein the semiconductor structure further comprises: a second gate spacer separating the first gate structure from the first drain region, and separating the second gate structure from the second drain region, wherein the second end section of the second body is at least in part wrapped around by the second gate spacer.
9. (Original) The semiconductor structure of claim 4, wherein the first end section and the second end section of the second body are coplanar.
12. (Original) The semiconductor structure of claim 8, wherein the first end section and the second end section of the second body are coplanar.
Claim Objections
Claims 2-4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Allowable Subject Matter
Claims 13-18 and 22-24 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: Hickey et al (US 2021/0408285 A1) shows (fig.2A/2B) multiple bodies of semiconductor material (256/254) wrapped by spacers (210A) however fails to demonstrate two bodies of semiconductor material being coplanar to each other along a first direction and between a gate electrode and as shown in fig.1C of the instant application (semiconductor bodies 118a2).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICKY VERDES whose telephone number is (703)756-1401. The examiner can normally be reached Monday - Friday 07:30 - 03:30 PM.
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/RICKY VERDES/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898