CTFR 17/832,999 CTFR 95226 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 1-25 are pending in this application. Claims 1-2 are currently amended; claims 3-25 are original. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. A. an assignment of sign elements of the first and second floating-point numbers to an XOR gate of the integer-based compute engines as specified in claims 8, 16 and 25 B. an assignment of exponent elements of the first and second floating-point numbers to an adder of the integer-based compute engines as specified in claims 8, 16 and 25 06-22-03 C. an assignment of mantissa elements of the first and second floating-point numbers to a multiplier of the integer-based compute engines as specified in claims 8, 16 and 25 Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. 07-30-03-h AIA Claim Interpretation The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. For example, assume a method claim requires step A if a first condition happens and step B if a second condition happens. If the claimed invention may be practiced without either the first or second condition happening, then neither step A or B is required by the broadest reasonable interpretation of the claim. If the claimed invention requires the first condition to occur, then the broadest reasonable interpretation of the claim requires step A. If the claimed invention requires both the first and second conditions to occur, then the broadest reasonable interpretation of the claim requires both steps A and B. The broadest reasonable interpretation of a system (or apparatus or product) claim having structure that performs a function, which only needs to occur if a condition precedent is met, requires structure for performing the function should the condition occur. The system claim interpretation differs from a method claim interpretation because the claimed structure must be present in the system regardless of whether the condition is met and the function is actually performed. See MPEP 2111.04 for more information. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 6, 14 and 23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 6 is rejected on the basis that it contains an improper Markush grouping of alternatives. See In re Harnisch , 631 F.2d 716, 721-22 (CCPA 1980) and Ex parte Hozumi , 3 USPQ2d 1059, 1060 (Bd. Pat. App. & Int. 1984). A Markush grouping is proper if the alternatives defined by the Markush group (i.e., alternatives from which a selection is to be made in the context of a combination or process, or alternative chemical compounds as a whole) share a “single structural similarity” and a common use. A Markush grouping meets these requirements in two situations. First, a Markush grouping is proper if the alternatives are all members of the same recognized physical or chemical class or the same art-recognized class, and are disclosed in the specification or known in the art to be functionally equivalent and have a common use. Second, where a Markush grouping describes alternative chemical compounds, whether by words or chemical formulas, and the alternatives do not belong to a recognized class as set forth above, the members of the Markush grouping may be considered to share a “single structural similarity” and common use where the alternatives share both a substantial structural feature and a common use that flows from the substantial structural feature. See MPEP § 2117. The Markush grouping of “one or more of partial reduction operations, quantization shifter operations, activation function operations or max pooling operations” is improper because the alternatives defined by the Markush grouping do not share both a single structural similarity and a common use for the following reasons: the members of the alternatives are not functionally equivalent and do not have a common use. See at least paragraph [0054] which discloses that the partial reduction 396, quantization shifting 400, activation function 398 and max pooling 402 different compute pipelines that execute different functions . Therefore, the members of the alternatives are substitutable, one for the other, with the expectation that the same intended result would be achieved. Claims 14 and 23 recite the same limitations and are rejected for the same reasons. To overcome this rejection, Applicant may set forth each alternative (or grouping of patentably indistinct alternatives) within an improper Markush grouping in a series of independent or dependent claims and/or present convincing arguments that the group members recited in the alternative within a single claim in fact share a single structural similarity as well as a common use. Claim Rejections - 35 USC § 101 Claims 18-24 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. Under Step 1, claims 18-24 recite a series of steps and, therefore, is a process. Under Step 2A prong 18, claim 1 recites “determining whether an operation is a floating-point based computation or an integer-based computation 1 ” and “when the operation is the integer-based computation, controlling to execute the integer-based computation.” The above limitation of determining whether an operation is a floating-point based computation or an integer-based computation is an evaluation or observation step which falls within the “Mental Processes” grouping of abstract ideas. The step of executing the integer-based computation amounts to processing mathematical calculations that can be performed mentally which falls within the “Mathematical Concepts” and/or “Mental Processes” grouping of abstract ideas. The step of “determining” and “execute” is a process that under its broadest reasonable interpretation, covers performance of the limitation in the mind. That is, nothing in the claim element precludes the step from practically being performed in the human mind. For example, the claim encompasses manually evaluating whether an operation is a floating-point based computation or an integer-based computation by observing whether a bit corresponding to an int/FP computation is set to a value of “0” to indicate an integer-based computation or set to “1” to indicate a floating-point based computation as shown in at least Table II in paragraph [0057] and when the operation indicates a integer-based computation, performing an integer multiplication such as multiplying a first and second integers. Accordingly, the claim is directed to recite an abstract idea. Under step 2A prong 2, the claim recites the following additional elements: integer-based compute engines. However, the additional elements of “integer-based compute engines” is recited at a high-level of generality (i.e., as integer-based compute engines for performing integer-based computations) such that it amounts no more than reciting the words “apply it” (or an equivalent) with the judicial exception or merely as a tool to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f) for more information. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application. Under step 2B, claim 18 does not include additional elements that, individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “integer-based compute engines” is recited at a high-level of generality (i.e., as integer-based compute engines for performing integer-based computations) such that it amounts no more than reciting the words “apply it” (or an equivalent) with the judicial exception or merely as a tool to implement the abstract idea. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f) for more information. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea. Under step 2A prong 1, claims 19-24 recite the same abstract idea as claim 18 by reason of dependence. Further, claims 19-20, and 24 recite further details of the contingent limitations that are not required to be performed when the operation is the integer-based computation; claim 21 recite further abstract idea of “identifying weight data associated with the operation, wherein the weight data has a first number of dimensions; adjusting the weight data to increase the first number of dimensions to a second number of dimensions” and claim 23 recites further abstract idea of “execute one or more of partial reduction operations, quantization shifter operations, activation function operations or max pooling operations” which falls within the “Mathematical Concepts” and/or “Mental Processes” grouping of abstract ideas. In particular claims 19-20 and 23-24 do not include additional elements that would require further analysis under step 2A prong 2 and step 2B. Accordingly, the claims are directed to recite an abstract idea. Under step 2A prong 2, claim 21 recites the following additional elements: storing the weight data having the second number of dimensions in a tile-based fashion to a memory; and storing input features associated with the operation and output features associated with the operation to the memory in the tile-based fashion; and claim 22 recites the following additional elements: wherein the operation is associated with a deep neural network workload. However, the additional elements of “a memory” in claim 21 is recited at a high-level of generality (i.e., as a generic computer component for storing data) such that it amounts to no more than mere instructions using a generic computer component or merely as a tool to implement the abstract idea. The additional elements of “wherein the operation is associated with a deep neural network workload” in claim 22 does no more than generally link the use of the abstract idea to a particular technological environment or field of use. The additional elements of “storing the weight data having the second number of dimensions in a tile-based fashion to a memory” and “storing input features associated with the operation and output features associated with the operation to the memory in the tile-based fashion” in claim 21 is merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application. Under step 2B, claims 21-22 do not include additional elements that, individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a memory” in claim 21 is recited at a high-level of generality (i.e., as a generic computer component for storing data) such that it amounts to no more than mere instructions using a generic computer component or merely as a tool to implement the abstract idea. The additional elements of “wherein the operation is associated with a deep neural network workload” in claim 22 does no more than generally link the use of the abstract idea to a particular technological environment or field of use. The additional elements of “storing the weight data having the second number of dimensions in a tile-based fashion to a memory” and “storing input features associated with the operation and output features associated with the operation to the memory in the tile-based fashion” in claim 21 is merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claims do not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claims do not amount to significantly more than the abstract idea. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-3, 6, 8, 18-20, 23 and 25 are rejected under 35 U.S.C. 102( a)(1) and (a)(2 ) as being anticipated by Pugh et al. (US 20210042087 A1), hereinafter Pugh . Regarding claim 1, Pugh teaches a computing system comprising: a plurality of computational engines implemented in one or more of configurable logic or fixed-functionality logic hardware, wherein the plurality of computational engines includes integer-based compute engines (Pugh Figs. 5-8 and paragraphs [0048, 0090]; plurality of computational engines - plurality of integer arithmetic logic blocks) ; a controller implemented in the one or more of configurable logic or fixed-functionality logic hardware, wherein the controller is to (Pugh Figs. 4-5, paragraph [0045] and claim 1; controller - mode selection input circuitry and bit remapping circuitry) : determine whether an operation is a floating-point based computation or an integer-based computation (Pugh Fig. 17 and paragraphs [0087-0090] “In operation 1710, the multiple mode arithmetic circuit receives a mode selection inputs that selects a mode from a set of modes comprising a first mode and a second mode … Depending on the value of the mode selection signal, either operation 1720 or operation 1730 is performed”) , when the operation is the floating-point based computation, generate a map of the operation to the integer-based compute engines to control the integer-based compute engines to execute the floating-point based computation (Pugh Fig. 17 and paragraph [0089] “In response to the mode selection input selecting the second mode, the multiple mode arithmetic circuit configures the plurality of integer arithmetic logic blocks to perform operations on floating-point operands, in operation 1730”; paragraph [0045] “Each of the bit remap logics 430A-430D remaps the inputs based on a multiplication mode and byte selection mode input. Exponent and sign bits are output from the bit remap logics 430A-430D as signals <EXPA>, <SGNA>, <EXPB>, <SGNB>, <EXPC>, <SGNC>, <EXPD>, and <SGND>. The remapped inputs are provided to the stage 1 delay registers 440, for access by the next portion of the arithmetic circuit”) , and when the operation is the integer-based computation, control the integer- based compute engines to execute the integer-based computation (Pugh Fig. 17 and paragraph [0088] “In response to the mode selection input selecting the first mode, the multiple mode arithmetic circuit, in operation 1720, configures a plurality of integer arithmetic logic blocks to perform operations on integer operands”). Regarding claim 2, Pugh teaches all the limitations of claim 1 as stated above. Further, Pugh teaches wherein the controller is to generate the map through: a division of a floating-point number associated with the floating-point based computation into a plurality of portions (Pugh Figs. 4-8 and paragraphs [0045-0046, 0052] plurality of portions – at least two of the following: sign, exponent and mantissa) ; and an assignment of each of the plurality of portions to a different integer-based compute engine of the integer-based compute engines (Pugh Figs. 4-8 and paragraphs [0052, 0061-0062]). Regarding claim 3, Pugh teaches all the limitations of claim 2 as stated above. Further, Pugh teaches wherein: the plurality of portions includes a sign portion, an exponent portion and a mantissa portion (Pugh Figs. 4-8 and paragraphs [0045-0046, 0052]) , the controller is to store the sign portion into a sign register, the exponent portion into an exponent register and the mantissa portion into a mantissa register (Pugh Figs. 4-6 and paragraphs [0045, 0052, 0061] sign register – at least one of 630A, 630B, 630E, 630F; exponent register - at least one of 630C, 630D, 630G, 630H; mantissa register - at least one of 510A-510P) , and the plurality of computational engines includes floating-point compute engines (Pugh Fig. 8 and paragraph [0071-0072] floating-point compute engines – logic block 850-850B). Regarding claim 6, Pugh teaches all the limitations of claim 1 as stated above. Further, Pugh teaches wherein the integer-based compute engines are to execute one or more of partial reduction operations, quantization shifter operations, activation function operations or max pooling operations (Pugh paragraph [0075] partial reduction operations – addition operations related to the row multiplication of the first operand with the column multiplication of the second operand to generate one element of a matrix result). Regarding claim 8, Pugh teaches all the limitations of claim 1 as stated above. Further, Pugh teaches wherein the operation is the floating- point based computation and is associated with first and second floating-point numbers, wherein the map is to include one or more of: an assignment of sign elements of the first and second floating-point numbers to an XOR gate of the integer-based compute engines; an assignment of exponent elements of the first and second floating-point numbers to an adder of the integer-based compute engines; and an assignment of mantissa elements of the first and second floating-point numbers to a multiplier of the integer-based compute engines (Pugh Figs. 4-5 and paragraph [0042] “The portion 400 accepts inputs for two multiply operands, A and B, remaps the operands to a format used by the next portion of the arithmetic circuit, and provides the remapped operands to delay registers used by the next portion”; first and second floating-point numbers – operands A and B; paragraph [0048] “The integer arithmetic logic blocks may be used to perform floating-point operations on the mantissas of floating-point operands”; paragraphs [0052-0053] “ Each of the multipliers 520A-520H accepts eight bits of the A operand and eight bits of the B operand”; claim 1 “the plurality of integer multiplier logic blocks is configured to perform operations on floating-point operands”; Note: the claim only requires at least one of the three assignments and Pugh teaches at least the third one). Regarding claims 18 2 -20, 23 and 25, they are directed to a method practiced by the system of claims 1-3, 6 and 8 respectively. All steps performed by the method of claims 18-20, 23 and 25 would be practiced by the system of claims 1-3, 6 and 8 respectively. Claims 1-3, 6 and 8 analysis applies equally to claims 18-20, 23 and 25 respectively . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 9-11, 14 and 16-20, 23 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Pugh as modified in view of Garegrat et al. (US 20190324723 A1), hereinafter Garegrat . Regarding claim 9, Pugh teaches one or more substrates; and logic coupled to the one or more substrates , wherein the logic is implemented in one or more of configurable logic or fixed-functionality logic hardware, the logic coupled to the one or more substrates to (Pugh Figs. 4-5, paragraph [0045] and claim 1; logic - mode selection input circuitry and bit remapping circuitry) : determine whether an operation is a floating-point based computation or an integer- based computation (Pugh Fig. 17 and paragraphs [0087-0090] “In operation 1710, the multiple mode arithmetic circuit receives a mode selection inputs that selects a mode from a set of modes comprising a first mode and a second mode … Depending on the value of the mode selection signal, either operation 1720 or operation 1730 is performed”) , when the operation is the floating-point based computation, generate a map of the operation to integer-based compute engines to control the integer-based compute engines to execute the floating-point based computation (Pugh Fig. 17 and paragraph [0089] “In response to the mode selection input selecting the second mode, the multiple mode arithmetic circuit configures the plurality of integer arithmetic logic blocks to perform operations on floating-point operands, in operation 1730”; paragraph [0045] “Each of the bit remap logics 430A-430D remaps the inputs based on a multiplication mode and byte selection mode input. Exponent and sign bits are output from the bit remap logics 430A-430D as signals <EXPA>, <SGNA>, <EXPB>, <SGNB>, <EXPC>, <SGNC>, <EXPD>, and <SGND>. The remapped inputs are provided to the stage 1 delay registers 440, for access by the next portion of the arithmetic circuit”) , and when the operation is the integer-based computation, control the integer-based compute engines to execute the integer-based computation (Pugh Fig. 17 and paragraph [0088] “In response to the mode selection input selecting the first mode, the multiple mode arithmetic circuit, in operation 1720, configures a plurality of integer arithmetic logic blocks to perform operations on integer operands”). Pugh does not explicitly teach one or more substrates ; and logic coupled to the one or more substrates . However, on the same field of endeavor, Garegrat discloses one or more substrates and logic coupled to the one or more substrates (Garegrat Fig. 7 and paragraph [0066]). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Pugh using Garegrat and configure the circuit to include one or more substrates coupled to the logic in order to implement the circuit as a semiconductor device (Garegrat paragraph [0066]). Therefore, the combination of Pugh as modified in view of Garegrat teaches one or more substrates; and logic coupled to the one or more substrates. Regarding claim 10, Pugh as modified in view of Garegrat teaches all the limitations of claim 9 as stated above. Further, Pugh as modified in view of Garegrat teaches wherein the logic is to generate the map through: a division of a floating-point number associated with the floating-point based computation into a plurality of portions (Pugh Figs. 4-8 and paragraphs [0045-0046, 0052] plurality of portions – at least two of the following: sign, exponent and mantissa) ; and and an assignment of each of the plurality of portions to a different integer-based compute engine of the integer-based compute engines (Pugh Figs. 4-8 and paragraphs [0052, 0061-0062]). Regarding claim 11, Pugh as modified in view of Garegrat teaches all the limitations of claim 10 as stated above. Further, Pugh as modified in view of Garegrat teaches wherein: the plurality of portions includes a sign portion, an exponent portion and a mantissa portion (Pugh Figs. 4-8 and paragraphs [0045-0046, 0052]) , the logic coupled to the one or more substrates is to store the sign portion into a sign register, the exponent portion into an exponent register and the mantissa portion into a mantissa register (Pugh Figs. 4-6 and paragraphs [0045, 0052, 0061] sign register – at least one of 630A, 630B, 630E, 630F; exponent register - at least one of 630C, 630D, 630G, 630H; mantissa register - at least one of 510A-510P) . Regarding claim 14, Pugh as modified in view of Garegrat teaches all the limitations of claim 9 as stated above. Further, Pugh as modified in view of Garegrat teaches wherein the integer-based compute engines are to execute one or more of partial reduction operations, quantization shifter operations, activation function operations or max pooling operations (Pugh paragraph [0075] partial reduction operations – addition operations related to the row multiplication of the first operand with the column multiplication of the second operand to generate one element of a matrix result). Regarding claim 16, Pugh as modified in view of Garegrat teaches all the limitations of claim 9 as stated above. Further, Pugh as modified in view of Garegrat teaches wherein the operation is the floating-point based computation and is associated with first and second floating-point numbers, further wherein the map is to include one or more of: an assignment of sign elements of the first and second floating-point numbers to an XOR gate of the integer-based compute engines; an assignment of exponent elements of the first and second floating-point numbers to an adder of the integer-based compute engines; and an assignment of mantissa elements of the first and second floating-point numbers to a multiplier of the integer-based compute engines (Pugh Figs. 4-5 and paragraph [0042] “The portion 400 accepts inputs for two multiply operands, A and B, remaps the operands to a format used by the next portion of the arithmetic circuit, and provides the remapped operands to delay registers used by the next portion”; first and second floating-point numbers – operands A and B; paragraph [0048] “The integer arithmetic logic blocks may be used to perform floating-point operations on the mantissas of floating-point operands”; paragraphs [0052-0053] “ Each of the multipliers 520A-520H accepts eight bits of the A operand and eight bits of the B operand”; claim 1 “the plurality of integer multiplier logic blocks is configured to perform operations on floating-point operands”; the claim only requires at least one of the three assignments and Pugh teaches at least the third one). Regarding claim 17, Pugh as modified in view of Garegrat teaches all the limitations of claim 9 as stated above. Further, Pugh as modified in view of Garegrat teaches wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates (Garegrat paragraph [0066] “the logic 182 includes transistor channel regions that are positioned (e.g., embedded) within the substrate(s) 184”). The motivation to combine is the same as claim 9. Regarding claims 18-20, 23 and 25, they are directed to a method practiced by the apparatus of claims 9-11, 14 and 16 respectively. All steps performed by the method of claims 18-20, 23 and 25 would be practiced by the apparatus of claims 9-11, 14 and 16 respectively. Claims 9-11, 14 and 16 analysis applies equally to claims 18-20, 23 and 25 respectively . 07-22-aia AIA Claim s 4-5 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Pugh as applied to claim s 1 and 18 above, and further in view of Ross et al. (US 20200160226 A1), hereinafter Ross . Regarding claim 4, Pugh teaches all the limitations of claim 1 as stated above. Pugh does not explicitly teach wherein the controller is to: identify weight data associated with the operation, wherein the weight data has a first number of dimensions; adjust the weight data to increase the first number of dimensions to a second number of dimensions; store the weight data having the second number of dimensions in a tile-based fashion to a memory; and store input features associated with the operation and output features associated with the operation to the memory in the tile-based fashion . However, on the same field of endeavor, Ross discloses identifying weight data associated with an operation, wherein the weight data has a first number of dimensions; adjusting the weight data to increase the first number of dimensions to a second number of dimensions (Ross Fig. 8 and paragraph [0136] weight data – kernel 820; first number of dimensions – 820 is a one dimensional kernel; second number of dimensions - dimensional kernel 826); storing the weight data having the second number of dimensions in a tile-based fashion to a memory (Ross Fig. 22A and paragraph [0250] the expanded kernel is stored in data storage 2220); and storing input features associated with the operation and output features associated with the operation to a memory in the tile-based fashion (Ross Fig. 22A and paragraph [0250] intermediate convolution results 2227 are stored in data storage 2220 also; paragraph [0055, 0064] the flattened input stream is stored in memory; abstract, Fig. 12A). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Pugh and generalize the teaching of Ross and configure the controller to identify weight data associated with the operation, generate an expanded kernel using the weight data; store the expanded kernel in a tile-based fashion to a memory; and store input features associated with the operation and output features associated with the operation to the memory in the tile-based fashion in order to enable for the computation of the values in each output tile without having to re-read the input values (Ross paragraph [0073]). Therefore, the combination of Pugh as modified in view of Ross teaches wherein the controller is to: identify weight data associated with the operation, wherein the weight data has a first number of dimensions; adjust the weight data to increase the first number of dimensions to a second number of dimensions; store the weight data having the second number of dimensions in a tile-based fashion to a memory; and store input features associated with the operation and output features associated with the operation to the memory in the tile-based fashion. Regarding claim 5, Pugh teaches all the limitations of claim 1 as stated above. Pugh does not explicitly teach wherein the operation is associated with a deep neural network workload . However, on the same field of endeavor, Ross discloses an operation associated with a deep neural network workload (Ross paragraph [0053-0054, 0085]). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Pugh and generalize the teaching of Ross by configuring the system of Pugh to perform operations associated with a neural network workload in order to implement a neural network or a layer of a neural network (Ross paragraph [0085]). Therefore, the combination of Pugh as modified in view of Ross teaches wherein the operation is associated with a deep neural network workload. Regarding claims 21-22, they are directed to a method practiced by the system of claims 4-5 respectively. All steps performed by the method of claims 21-22 would be practiced by the system of claims 4-5 respectively. Claims 4-5 analysis applies equally to claims 21-22 respectively . 07-22-aia AIA Claim s 7 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Pugh as applied to claim s 1 and 18 above, and further in view of Pasca (US 9904512 B1) . Regarding claim 7, Pugh teaches all the limitations of claim 1 as stated above. Pugh does not explicitly teach wherein the map is to include a finite state machine, wherein the controller is to control a flow of data during the operation to the integer- based compute engines based on the finite state machine . However, on the same field of endeavor, Pasca discloses a finite state machine wherein a controller is to control a flow of data during an operation to compute engines based on the finite state machine (Pasca Fig. 1 and col 5 lines 3-14 “Upon receiving a status information signal indicating that the floating-point unit 100 is ready to perform a new floating-point arithmetic operation, control FSM 130 may control the execution of the selected floating-point operation. Control FSM 130 may generate control signals and provide these control signals to other functional blocks such as the FPU core 101, the exponent handling blocks 110 and 120, the normalization and rounding block 140, and the exception handling blocks 112, 122, and 150. For example, control FSM 130 may generate multiplexer selection signals and clock enable signals and provide these signals to FPU core 101”). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Pugh and generalize the teaching of Pasca by including a finite state machine (FSM) in the map and controlling the flow of data and operation of the integer arithmetic blocks based on the FSM in order to generate the appropriate control signals and providing these control signals to the integer arithmetic blocks and to generate the appropriate selection signals provided to the multiplexers such as multiplexers 540A-540D in Fig. 5 (Pasca col 5 lines 7-14). Therefore, the combination of Pugh as modified in view of Pasca teaches wherein the map is to include a finite state machine, wherein the controller is to control a flow of data during the operation to the integer- based compute engines based on the finite state machine. Regarding claim 24, it is directed to a method practiced by the system of claim 7. All steps performed by the method of claim 24 would be practiced by the system of claim 7. Claim 7 analysis applies equally to claim 24 . 07-22-aia AIA Claim s 12-13 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Pugh in view of Garegrat as applied to claim s 9 and 18 above, and further in view of Ross . Regarding claim 12, Pugh as modified in view of Garegrat teaches all the limitations of claim 9 as stated above. Pugh does not explicitly teach wherein the logic coupled to the one or more substrates is to: identify weight data associated with the operation, wherein the weight data has a first number of dimensions; adjust the weight data to increase the first number of dimensions to a second number of dimensions; store the weight data having the second number of dimensions in a tile-based fashion to a memory; and store input features associated with the operation and output features associated with the operation to the memory in the tile-based fashion . However, on the same field of endeavor, Ross discloses identifying weight data associated with an operation, wherein the weight data has a first number of dimensions; adjusting the weight data to increase the first number of dimensions to a second number of dimensions (Ross Fig. 8 and paragraph [0136] weight data – kernel 820; first number of dimensions – 820 is a one dimensional kernel; second number of dimensions - dimensional kernel 826); storing the weight data having the second number of dimensions in a tile-based fashion to a memory (Ross Fig. 22A and paragraph [0250] the expanded kernel is stored in data storage 2220); and storing input features associated with the operation and output features associated with the operation to a memory in the tile-based fashion (Ross Fig. 22A and paragraph [0250] intermediate convolution results 2227 are stored in data storage 2220 also; paragraph [0055, 0064] the flattened input stream is stored in memory; abstract, Fig. 12A). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Pugh in view of Garegrat and generalize the teaching of Ross and configure the logic to identify weight data associated with the operation, generate an expanded kernel using the weight data; store the expanded kernel in a tile-based fashion to a memory; and store input features associated with the operation and output features associated with the operation to the memory in the tile-based fashion in order to enable for the computation of the values in each output tile without having to re-read the input values (Ross paragraph [0073]). Therefore, the combination of Pugh as modified in view of Garegrat and Ross teaches wherein the logic coupled to the one or more substrates is to: identify weight data associated with the operation, wherein the weight data has a first number of dimensions; adjust the weight data to increase the first number of dimensions to a second number of dimensions; store the weight data having the second number of dimensions in a tile-based fashion to a memory; and store input features associated with the operation and output features associated with the operation to the memory in the tile-based fashion. Regarding claim 13, Pugh as modified in view of Garegrat teaches all the limitations of claim 9 as stated above. Pugh does not explicitly teach wherein the operation is associated with a deep neural network workload . However, on the same field of endeavor, Ross discloses an operation associated with a deep neural network workload (Ross paragraph [0053-0054, 0085]). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Pugh in view of Garegrat and generalize the teaching of Ross by configuring the system of Pugh to perform operations associated with a neural network workload in order to implement a neural network or a layer of a neural network (Ross paragraph [0085]). Therefore, the combination of Pugh as modified in view of Garegrat and Ross teaches wherein the operation is associated with a deep neural network workload. Regarding claims 21-22, they are directed to a method practiced by the apparatus of claims 12-13 respectively. All steps performed by the method of claims 21-22 would be practiced by the apparatus of claims 12-13 respectively. Claims 12-13 analysis applies equally to claims 21-22 respectively . 07-22-aia AIA Claim s 15 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Pugh in view of Garegrat as applied to claim s 9 and 18 above, and further in view of Pasca . Regarding claim 15, Pugh as modified in view of Garegrat teaches all the limitations of claim 1 as stated above. Pugh does not explicitly teach wherein: the map is to include a finite state machine, and the logic coupled to the one or more substrates is to control a flow of data to the integer-based compute engines based on the finite state machine, wherein the data is associated with the operation . However, on the same field of endeavor, Pasca discloses a finite state machine wherein a controller is to control a flow of data during an operation to compute engines based on the finite state machine (Pasca Fig. 1 and col 5 lines 3-14 “Upon receiving a status information signal indicating that the floating-point unit 100 is ready to perform a new floating-point arithmetic operation, control FSM 130 may control the execution of the selected floating-point operation. Control FSM 130 may generate control signals and provide these control signals to other functional blocks such as the FPU core 101, the exponent handling blocks 110 and 120, the normalization and rounding block 140, and the exception handling blocks 112, 122, and 150. For example, control FSM 130 may generate multiplexer selection signals and clock enable signals and provide these signals to FPU core 101”). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Pugh in view of Garegrat and generalize the teaching of Pasca by including a finite state machine (FSM) in the map and controlling the flow of data and operation of the integer arithmetic blocks based on the FSM in order to generate the appropriate control signals and providing these control signals to the integer arithmetic blocks and to generate the appropriate selection signals provided to the multiplexers such as multiplexers 540A-540D in Fig. 5 (Pasca col 5 lines 7-14). Therefore, the combination of Pugh as modified in view of Garegrat and Pasca teaches wherein: the map is to include a finite state machine, and the logic coupled to the one or more substrates is to control a flow of data to the integer-based compute engines based on the finite state machine, wherein the data is associated with the operation. Regarding claim 24, it is directed to a method practiced by the apparatus of claim 15. All steps performed by the method of claim 24 would be practiced by the apparatus of claim 15. Claim 7 analysis applies equally to claim 24 . Response to Arguments In response to Applicant’s Comments with respect to the completeness and clarity of examiner’s action, examiner would like to point out that there were no claims presently recited that are allowable. In view of amendments made and Applicant’s arguments, the objection to the drawings under section 3-4, the specification, and the claims has been withdrawn. 07-37 AIA Applicant's arguments filed 05/19/2026, see remarks page 10 bottom, with respect to the objection to the drawings under section 2 have been fully considered but they are not persuasive. Applicant argues that operation map 140 in Fig. 1 described in paragraph [0029] shows every feature of the invention specified in claims 8 , 16 and 25. Response: Examiner respectfully disagrees. Operational map 140 in Fig. 1 does not show an assignment of sign elements of the first and second floating-point numbers to an XOR gate; an assignment of exponent elements of the first and second floating-point numbers to an adder; and an assignment of mantissa elements of the first and second floating-point numbers to a multiplier of the integer-based compute engines as specified in claims 8, 16 and 25 . 07-37 AIA Applicant's arguments filed 05/19/2026, see remarks page 11-12, with respect to the 35 U.S.C. 101 rejection of claims 18-24 have been fully considered but they are not persuasive. Applicant argues the following: 1.) the claims do not recite a mental process because they are directed to a multiformat hardware controller evaluating computational operations and the human mind is not equipped to process instruction set architectures or dynamically configure digital hardware execution pipelines at processor speeds. Response: Examiner respectfully disagrees. Applicant is arguing unclaimed features. The claim does not recite any a multiformat hardware controller. Further, the claim does not recite any speed at which the determining and executing steps are performed and any instruction set architectures. Furthermore, claims can still recite a mental process even if they are claimed as being performed on a computer. See MPEP 2106.04(a)(2) III.C for more information. 2.) the abstract idea is integrated into practical application because the features of “generating a map of the operation to integer-based compute engines to control the integer-based compute engines to execute the floating-point based computation” allows a processor to execute floating-point operations using integer pipelines, thereby reducing the need for dedicated floating-point hardware and improving overall processor area and power metrics as described in paragraphs [0027-0031]. Response: Examiner would like to point out that the claims 18-24 are method claims, and the features of “when the operation is the floating-point based computation, generating a map of the operation to integer-based compute engines to control the integer-based compute engines to execute the floating-point based computation” are contingent limitations that are not required to be performed when the operation is an integer-based computation . Therefore, any alleged improvement of improving overall processor area and power metrics is not reflected in the claims when the operation is an integer-based computation. See MPEP 2111.04 II for more information . 07-37 AIA Applicant's arguments filed 05/19/2026, see remarks page 12-13 with respect to the 35 U.S.C. 112(b) rejection of claims 6, 14 and 23 have been fully considered but they are not persuasive. Applicant argues that Markush groupings only applies to alternative chemical compounds or mutually exclusive structural elements from which a selection is made and the list in claims 6, 14 and 23 merely specifies the operations the claimed engine is configured to execute, rather than offering a Markush-style selection of interchangeable components. Response: Examiner respectfully disagrees. MPEP 2117 states “Although the term "Markush claim" is used throughout the MPEP, any claim that recites alternatively usable members, regardless of format, should be treated as a Markush claim.” See also MPEP 2172.05(h) which states “Claims that set forth a list of alternatives from which a selection is to be made are typically referred to as Markush claims”. Therefore, the list of alternatives recites in claims 6, 14 and 23 recite a Markush claim that is improper because the recited members do not share a common use . 07-37 AIA Applicant's arguments filed 05/19/2026, see remarks page 13-15, with respect to the 35 U.S.C. 102 rejection of claims 1-3, 6, 8, 18-20, 23, and 25 and 35 U.S.C. 103 rejection of claims 9-11, 14, 16-20, 23, and 25 have been fully considered but they are not persuasive. Applicant argues that the bit remap logics 430A-430D described in paragraph [0045] merely teaches remapping or formatting input data operands, such as sign extending or padding zeros, to convert the data into a format expected by the downstream arithmetic portion. Remapping input data is different from the claimed step of generating a map of the operation itself, which entails decomposing the operation and assigning portions of a computation to specific compute engines . Response: Examiner respectfully disagrees. Applicant is arguing unclaimed features. The claims do not recite any details of decomposing the operation and assigning portions of a computation to specific compute engines. The claim only requires to generate a map of the operation to the integer-based compute engines to control the integer-based compute engines to execute the floating-point based computation. Paragraph [0045] discloses in part “Each of the bit remap logics 430A-430D remaps the inputs based on a multiplication mode and byte selection mode input. Exponent and sign bits are output from the bit remap logics 430A-430D as signals <EXPA>, <SGNA>, <EXPB>, <SGNB>, <EXPC>, <SGNC>, <EXPD>, and <SGND>.” Further paragraph [0089] discloses “In response to the mode selection input selecting the second mode, the multiple mode arithmetic circuit configures the plurality of integer arithmetic logic blocks to perform operations on floating-point operands, in operation 1730.” Therefore, the operation is remapped (i.e., the correct portions of the inputs are properly routed) such that the plurality of integer arithmetic logic blocks are configured to perform operations on floating-point operands which is fairly disclosed in Figs. 4-5 and corresponding description, for example, extracting and separating the signs and exponents such that they are not treated as part of the bits (mantissa) being multiplied by the multipliers. Conclusion 07-39 AIA THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlo Waje whose telephone number is (571)272-5767. The examiner can normally be reached 9:00-6:00 M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Carlo Waje/Examiner, Art Unit 2151 (571)272-5767 Application/Control Number: 17/832,999 Page 2 Art Unit: 2151 Application/Control Number: 17/832,999 Page 3 Art Unit: 2151 Application/Control Number: 17/832,999 Page 4 Art Unit: 2151 Application/Control Number: 17/832,999 Page 5 Art Unit: 2151 Application/Control Number: 17/832,999 Page 6 Art Unit: 2151 Application/Control Number: 17/832,999 Page 7 Art Unit: 2151 Application/Control Number: 17/832,999 Page 8 Art Unit: 2151 Application/Control Number: 17/832,999 Page 9 Art Unit: 2151 Application/Control Number: 17/832,999 Page 10 Art Unit: 2151 Application/Control Number: 17/832,999 Page 11 Art Unit: 2151 Application/Control Number: 17/832,999 Page 12 Art Unit: 2151 Application/Control Number: 17/832,999 Page 13 Art Unit: 2151 Application/Control Number: 17/832,999 Page 14 Art Unit: 2151 Application/Control Number: 17/832,999 Page 15 Art Unit: 2151 Application/Control Number: 17/832,999 Page 16 Art Unit: 2151 Application/Control Number: 17/832,999 Page 17 Art Unit: 2151 Application/Control Number: 17/832,999 Page 18 Art Unit: 2151 Application/Control Number: 17/832,999 Page 19 Art Unit: 2151 Application/Control Number: 17/832,999 Page 20 Art Unit: 2151 Application/Control Number: 17/832,999 Page 21 Art Unit: 2151 Application/Control Number: 17/832,999 Page 22 Art Unit: 2151 Application/Control Number: 17/832,999 Page 23 Art Unit: 2151 Application/Control Number: 17/832,999 Page 24 Art Unit: 2151 Application/Control Number: 17/832,999 Page 25 Art Unit: 2151 Application/Control Number: 17/832,999 Page 26 Art Unit: 2151 Application/Control Number: 17/832,999 Page 27 Art Unit: 2151 1 Examiner notes that claim 18 only requires the determining step and one of the when clauses to occur. See MPEP 2111.04 for more information. 2 Although the method claims are rejected using the same analysis as the system claims, examiner notes that the BRI of a process claim that recite similar contingent limitations as the system claim may not require the steps recited in those contingent limitations. See MPEP 2111.04 for more information.
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