DETAILED ACTION
Claims 1-4 and 6-25 are pending in this application.
Claims 1-4 and 6-25 are rejected.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/30/2025 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6, 12-17, 19-21, 23 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al. (U.S. Patent No. 9152553) in view of Boehm et al. (U.S. PGPub No. 2020/0117393) in view of Silvester et al. (U.S. Patent No. 7155615)
Claim 1
Shin (9152553) teaches:
A memory device, comprising: one or more components configured to:
receive, from a host device, a pilot command that includes an indication of a sequence of upcoming memory commands comprising a preconfigured order of upcoming memory commands; Col. 8 line 4-14 and FIG. 1 the descriptor describes a command sequence defining an operation (e.g., read, write, or erase) for a memory device, the descriptor is provided to a memory controller, such as memory control module 130, from host 102; Col 10 line 63 – Col. 11 line 9 the descriptors can be chained together, to enforce order of descriptors
Shin does not explicitly teach receiving a sequence of upcoming commands from a host device, and determining whether subsequently received commands are invalid based on the sequence.
Boehm (2020/0117393) teaches:
receive, from a host device, a pilot command that includes an indication of a sequence of upcoming memory commands comprising a preconfigured order of upcoming memory commands to be transmitted from the host device to the memory device; P. 0069 memory device 310 may store a set of defined commands programmed by the host 305 after assembly
receive a memory command from the host device after receiving the pilot command; P. 0069 the memory device 310 may receive the set of valid commands from the host device 305 and may store the set of valid commands
increment a counter based on determining that the memory command is invalid in association with the sequence of upcoming memory commands based on the indication of the sequence of upcoming memory commands; and P. 0069 valid command circuitry 325 may determine whether a sequence of commands is part of a defined set of command sequences; P. 0073 event log registers 335 may include a counting register for storing a number of invalid commands, which increments a stored value when the event log registers 335 receive the indication of the invalid command 340
reset the memory device […] in response to determining, at the memory device, that a value of a counter satisfies a threshold. P. 0073-0075 if the number of recorded invalid commands satisfies the threshold, the memory device may transition into safe mode. After entering safe mode, a guard key may be transmitted to reset the memory device to access mode
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Shin with receiving a sequence of upcoming commands from a host device, and determining whether subsequently received commands are invalid based on the sequence taught by Boehm.
The motivation being to block undefined commands from execution at the memory device (see Boehm P. 0015)
The systems of Shin and Boehm do not explicitly teach automatically resetting the memory device in response to a number of invalid commands reaching a threshold.
Silvester (7155615) teaches:
reset the memory device automatically in response to determining, at the memory device, that a value of a counter satisfies a threshold. Col. 5 line 59 – Col. 6 line 18 if the predetermined number of invalid requests are received, access to the hard drive is disabled and the power must be cycled off-on
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Shin and Boehm with automatically resetting the memory device in response to a number of invalid commands reaching a threshold taught by Silvester.
The motivation being it would take a long time for a software to run through all possible numbers of a 128-bit token when the power must be cycled off-on after a certain amount of invalid attempts (see Silvester Col. 5 line 59 – Col. 6 line 18)
The systems of Shin, Boehm and Silvester are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Shin and Boehm with Silvester to obtain the invention as recited in claims 1-11.
Claim 2
Shin (9152553) teaches:
The memory device of claim 1, wherein the indication, included in the pilot command, includes a code that maps to the sequence of upcoming memory commands. Col. 8 line 4-14 the descriptor describes a command sequence defining an operation (e.g., read, write, or erase) for a memory device, the descriptor is provided to a memory controller, such as memory control module 130
Claim 3
Shin (9152553) teaches:
The memory device of claim 1, further comprising a memory configured to store a table that indicates mappings between codes and corresponding sequences of upcoming memory commands. Col. 8 line 16-22 memory controller can receive and decode the descriptor and generate a command sequence for controlling the respective memory device; Col. 8 line 45-55 the command sequence corresponding to a command type 210 (within descriptor 200, see FIG. 2) is predefined in the memory controller; Col. 4 line 60 – Col. 5 line 13 the solid state controller 108 can include random-access memory (RAM)
Claim 4
Shin (9152553) teaches:
The memory device of claim 3, wherein the memory device is configured to store the table in a non-host-addressable memory region. Col. 8 line 45-55 the command sequence corresponding to a command type 210 (within descriptor 200, see FIG. 2) is predefined in the memory controller; Col. 4 line 60 – Col. 5 line 13 the solid state controller 108 can include random-access memory (RAM)
Claim 6
Shin (9152553) teaches:
A memory device, comprising: one or more components configured to:
receive, from a host device, a pilot command that includes an indication of a sequence of upcoming memory commands comprising a preconfigured order of upcoming memory commands to be transmitted from the host device to the memory device; Col. 8 line 4-14 and FIG. 1 the descriptor describes a command sequence defining an operation (e.g., read, write, or erase) for a memory device, the descriptor is provided to a memory controller, such as memory control module 130, from host 102; Col 10 line 63 – Col. 11 line 9 the descriptors can be chained together, to enforce order of descriptors
Shin does not explicitly teach receiving a sequence of upcoming commands from a host device, and determining whether subsequently received commands are invalid based on the sequence.
Boehm (2020/0117393) teaches:
receive a memory command from the host device after receiving the pilot command; determine that the memory command is invalid based on the indication of the sequence of upcoming memory commands that comprises the preconfigured order of upcoming memory commands; P. 0069 memory device 310 may store a set of defined commands [preconfigured commands] programmed by the host 305 after assembly; P. 0069 the memory device 310 may receive the set of valid commands from the host device 305 and may store the set of valid commands
increment a counter, stored in memory of the memory device, based on determining that the memory command is invalid; P. 0069 valid command circuitry 325 may determine whether a sequence of commands is part of a defined set of command sequences; P. 0073 event log registers 335 may include a counting register for storing a number of invalid commands, which increments a stored value when the event log registers 335 receive the indication of the invalid command 340
transmit, to the host device and based on determining that the memory command is invalid, a message indicating that the memory command is invalid; and P. 0076 in response to an receiving the invalid command, the event log registers 335 (in memory device 310) may include the invalid command in the feedback transmitted to the host device 305
reset the memory device […] in response to determining, at the memory device, that a value of the counter satisfies a threshold. P. 0073-0075 if the number of recorded invalid commands satisfies the threshold, the memory device may transition into safe mode. After entering safe mode, a guard key may be transmitted to reset the memory device to access mode
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Shin with receiving a sequence of upcoming commands from a host device, and determining whether subsequently received commands are invalid based on the sequence taught by Boehm.
The motivation being to block undefined commands from execution at the memory device (see Boehm P. 0015)
The systems of Shin and Boehm do not explicitly teach automatically resetting the memory device in response to a number of invalid commands reaching a threshold.
Silvester (7155615) teaches:
reset the memory device automatically in response to determining, at the memory device, that a value of the counter satisfies a threshold. Col. 5 line 59 – Col. 6 line 18 if the predetermined number of invalid requests are received, access to the hard drive is disabled and the power must be cycled off-on
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Shin and Boehm with automatically resetting the memory device in response to a number of invalid commands reaching a threshold taught by Silvester.
The motivation being it would take a long time for a software to run through all possible numbers of a 128-bit token when the power must be cycled off-on after a certain amount of invalid attempts (see Silvester Col. 5 line 59 – Col. 6 line 18)
The systems of Shin, Boehm and Silvester are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Shin and Boehm with Silvester to obtain the invention as recited in claim 6.
Claim 12
Shin (9152553) teaches:
A method performed by a memory device, comprising:
receiving, from a host device, a pilot command that includes a code that maps to a sequence of upcoming memory commands to be transmitted from the host device to the memory device, the sequence of upcoming memory commands comprising a preconfigured order of upcoming commands to be transmitted from the host device to the memory device; Col. 8 line 4-14 and FIG. 1 the descriptor describes a command sequence defining an operation (e.g., read, write, or erase) for a memory device, the descriptor is provided to a memory controller, such as memory control module 130, from host 102; Col 10 line 63 – Col. 11 line 9 the descriptors can be chained together, to enforce order of descriptors
Shin does not explicitly teach enabling a validation mode based on receiving the pilot command, receiving a sequence of upcoming commands from a host device, and determining whether subsequently received commands are invalid based on the sequence.
Boehm (2020/0117393) teaches:
enabling a memory command validation mode based on receiving the pilot command; P. 0075 receive a command from host device 305 to return to access mode
receiving, from the host device and while the memory command validation mode is enabled, a memory command; P. 0074 In the access mode, the memory device 310 may execute commands (e.g., the defined commands) received from host device 305
determining whether the memory command is valid based on the preconfigured order of upcoming memory commands; and P. 0069 valid command circuitry 325 may determine whether a sequence of commands is part of a defined set of command sequences; P. 0069 the set of defined commands may programmable by the host 305; P. 0067 commands may be burst commands (multiple sequential commands)
selectively executing or ignoring the memory command based on determining whether the memory command is valid, wherein the memory command is executed if the memory command is valid, and wherein the memory command is ignored if the memory command is invalid; and P. 0079 If the received command is determined to be in the set of defined commands, the received command is propagated to the decoder 360
determining, at the memory device, whether to reset the memory device […] in response to determining whether a value of a counter, associated with invalid memory commands, satisfies a threshold. P. 0073-0075 if the number of recorded invalid commands satisfies the threshold, the memory device may transition into safe mode. After entering safe mode, a guard key may be transmitted to reset the memory device to access mode
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Shin with enabling a validation mode based on receiving the pilot command, receiving a sequence of upcoming commands from a host device, and determining whether subsequently received commands are invalid based on the sequence taught by Boehm.
The motivation being to block undefined commands from execution at the memory device (see Boehm P. 0015)
The systems of Shin and Boehm do not explicitly teach automatically resetting the memory device in response to a number of invalid commands reaching a threshold.
Silvester (7155615) teaches:
determining, at the memory device, whether to reset the memory device automatically in response to determining whether a value of a counter, associated with invalid memory commands, satisfies a threshold. Col. 5 line 59 – Col. 6 line 18 if the predetermined number of invalid requests are received, access to the hard drive is disabled and the power must be cycled off-on
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Shin and Boehm with automatically resetting the memory device in response to a number of invalid commands reaching a threshold taught by Silvester.
The motivation being it would take a long time for a software to run through all possible numbers of a 128-bit token when the power must be cycled off-on after a certain amount of invalid attempts (see Silvester Col. 5 line 59 – Col. 6 line 18)
The systems of Shin, Boehm and Silvester are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Shin and Boehm with Silvester to obtain the invention as recited in claims 12-19.
Claim 13
Boehm (2020/0117393) teaches:
The method of claim 12, further comprising transmitting, to the host device, a message indicating that the memory command is invalid based on determining that the memory command is invalid. P. 0076 event log registers 335 may provide a feedback to the host device 305 related to the invalid command
The rationale to combine Shin with Boehm for claim 12 equally applies for dependent claim 13.
Claim 14
Shin (9152553) teaches:
The method of claim 12, wherein the sequence of upcoming memory commands is a fixed sequence. Col. 10 line 47-62 a generic descriptor may include three command segments and two address segments
Claim 15
Shin (9152553) teaches:
The method of claim 12, wherein the sequence of upcoming memory commands includes a variable number of commands. Col. 8 line 64 – Col. 9 line 9 many different configurations or combinations of command sequences can be generated
Claim 16
Shin (9152553) teaches:
The method of claim 12, wherein the sequence of upcoming memory commands includes a fixed sequence of a fixed number of starting commands, followed by a variable number of commands, followed by a fixed sequence of a fixed number of ending commands. Col. 8 line 64 – Col. 9 line 9 many different configurations or combinations of command sequences can be generated
Claim 17
Boehm (2020/0117393) teaches:
The method of claim 12, wherein the sequence of upcoming memory commands is associated with a read operation, a write operation, or a memory management operation. P. 0068 a defined command may be a read instruction, a write instruction, a refresh instruction
The rationale to combine Shin with Boehm for claim 12 equally applies for dependent claim 17.
Claim 19
Boehm (2020/0117393) teaches:
The method of claim 12, further comprising: receiving an instruction to exit the memory command validation mode; and exiting the memory command validation mode based on the instruction. P. 0075 a command indicates a reset procedure, which transitions the memory device 310 from safe mode to access mode
The rationale to combine Shin with Boehm for claim 12 equally applies for dependent claim 19.
Claim 20
Shin (9152553) teaches:
A system, comprising: a host device configured to: transmit, to a memory device, a pilot command that includes an indication of a sequence of upcoming memory commands comprising a preconfigured order of upcoming commands to be transmitted from the host device to the memory device, Col. 8 line 4-14 and FIG. 1 the descriptor describes a command sequence defining an operation (e.g., read, write, or erase) for a memory device, the descriptor is provided to a memory controller, such as memory control module 130, from host 102; Col 10 line 63 – Col. 11 line 9 the descriptors can be chained together, to enforce order of descriptors
Shin does not explicitly teach enabling a validation mode based on receiving the pilot command, receiving a sequence of upcoming commands from a host device, and determining whether subsequently received commands are invalid based on the sequence.
Boehm (2020/0117393) teaches:
wherein the pilot command is configured to cause the memory device to enter a memory command validation mode to validate memory commands using the preconfigured order of upcoming memory commands; P. 0069 valid command circuitry 325 may determine whether a sequence of commands is part of a defined set of command sequences
P. 0075 receive a command from host device 305 to return to access mode; P. 0074 In the access mode, the memory device 310 may execute commands (e.g., the defined commands) received from host device 305; P. 0069 the set of defined commands may programmable by the host 305; P. 0067 commands may be burst commands (multiple sequential commands)
transmit a memory command to the memory device after transmitting the pilot command; P. 0074 In the access mode, the memory device 310 may execute commands (e.g., the defined commands) received from host device 305
receive, from the memory device, a message indicating that the memory command is invalid in association with the pilot command; and P. 0072 event log registers 335 may store each of the commands of the received sequence of commands that is invalid; P. 0076 event log registers 335 may provide a feedback to the host device 305 related to the invalid command
the memory device configured to: increment a counter based on determining that the memory command is invalid in association with the sequence of upcoming memory commands; and P. 0073 counting register may increment a stored value when the event log registers 335 receive the indication of the invalid command 340
reset the memory device […] in response to determining, at the memory device, that a value of the counter satisfies a threshold P. 0073-0075 if the number of recorded invalid commands satisfies the threshold, the memory device may transition into safe mode. After entering safe mode, a guard key may be transmitted to reset the memory device to access mode
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Shin with enabling a validation mode based on receiving the pilot command, receiving a sequence of upcoming commands from a host device, and determining whether subsequently received commands are invalid based on the sequence taught by Boehm.
The motivation being to block undefined commands from execution at the memory device (see Boehm P. 0015)
The systems of Shin and Boehm do not explicitly teach automatically resetting the memory device in response to a number of invalid commands reaching a threshold.
Silvester (7155615) teaches:
reset the memory device automatically in response to determining, at the memory device, that a value of the counter satisfies a threshold Col. 5 line 59 – Col. 6 line 18 if the predetermined number of invalid requests are received, access to the hard drive is disabled and the power must be cycled off-on
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Shin and Boehm with automatically resetting the memory device in response to a number of invalid commands reaching a threshold taught by Silvester.
The motivation being it would take a long time for a software to run through all possible numbers of a 128-bit token when the power must be cycled off-on after a certain amount of invalid attempts (see Silvester Col. 5 line 59 – Col. 6 line 18)
The systems of Shin, Boehm and Silvester are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Shin and Boehm with Silvester to obtain the invention as recited in claims 20-25.
Claim 21
Boehm (2020/0117393) teaches:
The system of claim 20, wherein the host device is configured to transmit the memory command to the memory device after receiving an acknowledgement, from the memory device, that the memory command validation mode has been enabled for the memory device. P. 0077-78 the host may, based on feedback of the invalid command received from memory device 310, transmit a command to reset from safe mode to access mode
The rationale to combine Shin with Boehm for claim 20 equally applies for dependent claim 21.
Claim 23
Boehm (2020/0117393) teaches:
The system of claim 20, wherein the sequence of upcoming memory commands indicates one or more command parameters associated with the memory command.
P. 0069 valid command circuitry 325 may determine whether a sequence of commands is part of a defined set of command sequences; P. 0069 the set of defined commands may programmable by the host 305; P. 0098 Each of the plurality of commands may include an instruction and/or address
The rationale to combine Shin with Boehm for claim 20 equally applies for dependent claim 23.
Claim 25
Boehm (2020/0117393) teaches:
The system of claim 20, wherein the message excludes an indication of an expected command of the sequence of upcoming memory commands. P. 0076 In some cases, the feedback may include an indication of the invalid command
The rationale to combine Shin with Boehm for claim 20 equally applies for dependent claim 25.
Claim(s) 7-11, 18 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al. (U.S. Patent No. 9152553) in view of Boehm et al. (U.S. PGPub No. 2020/0117393) in view of Silvester et al. (U.S. Patent No. 7155615) in view of Som et al. (U.S. PGPub No. 2020/0257460)
Claim 7
The systems of Shin and Boehm do not explicitly teach determining a command is invalid when a command parameter does not match an expected command parameter.
Som (2020/0257460) teaches:
The memory device of claim 1, wherein the one or more components, to determine that the memory command is invalid, are configured to:
determine that a command parameter associated with the memory command does not match an expected command parameter of a next expected command in the sequence of upcoming memory commands. P. 0044-52 parameters of a command in the register are compared against a list of authorized parameters associated with the command; P. 0106 a metric may be defined to determine whether a READ command has been issued for a location issued following an ERASE command for the same location, when no intervening WRITE/PROGRAM command has occurred
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Shin and Boehm with determining a command is invalid when a command parameter does not match an expected command parameter taught by Som.
The motivation being to ensure a command matches one of the authorized commands, including a correct address range and other parameters (see Som P. 0037)
The systems of Shin, Boehm and Som are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Shin and Boehm with Som to obtain the invention as recited in claims 7-11.
Claim 8
Som (2020/0257460) teaches:
The memory device of claim 7, wherein the command parameter includes at least one of: a command type of the memory command, P. 0095 For example, the BLOCK ERASE or READ command (along with attributes, such as addresses for the command) may be compared to the list of commands 638
whether the memory command is encrypted, whether the memory command is associated with encrypted data, whether the memory command is cryptographically signed, or whether a public key or a private key is used to cryptographically sign the memory command.
The rationale to combine Shin and Boehm with Som for claim 7 equally applies for dependent claim 8.
Claim 9
Som (2020/0257460) teaches:
The memory device of claim 1, wherein the one or more components, to determine that the memory command is invalid, are configured to:
determine that a command parameter associated with the memory command does not match any expected command parameters of any commands in the sequence of upcoming memory commands. P. 0044-52 parameters of a command in the register are compared against a list of authorized parameters associated with the command
The rationale to combine Shin and Boehm with Som for claim 7 equally applies for claim 9.
Claim 10
Som (2020/0257460) teaches:
The memory device of claim 1, wherein the one or more components, to determine that the memory command is invalid, are configured to:
determine that a command type of the memory command does not match an expected command type of a next expected command in the sequence of upcoming memory commands. P. 0106 a metric may be defined to determine whether a READ command has been issued for a location issued following an ERASE command for the same location, when no intervening WRITE/PROGRAM command has occurred
The rationale to combine Shin and Boehm with Som for claim 9 equally applies for dependent claim 10.
Claim 11
Boehm (2020/0117393) teaches:
The memory device of claim 1, wherein the one or more components are further configured to: transmit, to the host device, a message indicating that the memory command is invalid P. 0076 in response to an receiving the invalid command, the event log registers 335 (in memory device 310) may include the invalid command in the feedback transmitted to the host device 305
Som (2020/0257460) teaches:
wherein the message excludes an indication of an expected command of the sequence of upcoming memory commands. P. 0037 accept module may reject the command, for example, by returning an error to the CPU 102
The rationale to combine Shin with Som for claim 1 equally applies for dependent claim 11.
Claim 18
The systems of Shin and Boehm do not explicitly teach exiting validation mode based on a determination the memory command is a final command in the sequence.
Som (2020/0257460) teaches:
The method of claim 12, further comprising exiting the memory command validation mode based on a determination that the memory command is a final command included in the sequence of upcoming memory commands. P. 0111 A metric may be defined to identify a “focused” flash command sequence, that is, commands issued in a sequence identifiable as not serving a legitimate operational purpose; P. 0112 A metric may be defined to identify allowable commands that don't follow an expected sequence
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Shin and Boehm with exiting validation mode based on a determination the memory command is a final command in the sequence taught by Som
The motivation being to protect the contents of the flash ROM 142 (See Som P. 0038)
The systems of Shin, Boehm and Som are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Shin and Boehm with Som to obtain the invention as recited in claim 18.
Claim 24
The systems of Shin and Boehm do not explicitly teach command parameters including a command type.
Som (2020/0257460) teaches:
The system of claim 23, wherein the one or more command parameters includes at least one of: a command type of the memory command, P. 0093 a command may be authorized or depending both upon the type of command and other command attributes
whether the memory command is encrypted, whether the memory command is associated with encrypted data, whether the memory command is cryptographically signed, or whether a public key or a private key is used to cryptographically sign the memory command.
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Shin and Boehm with command parameters including a command type taught by Som.
The motivation being to protect the contents of the flash ROM 142 (See Som P. 0038)
The systems of Shin, Boehm and Som are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Shin and Boehm with Som to obtain the invention as recited in claim 24.
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al. (U.S. Patent No. 9152553) in view of Boehm et al. (U.S. PGPub No. 2020/0117393) in view of Silvester et al. (U.S. Patent No. 7155615) in view of Senoo et al. (U.S. PGPub No. 2022/0413748).
Claim 22
The systems of Shin and Boehm do not explicitly teach determining the pilot command was erroneously transmitted.
Senoo (2022/0413748) teaches:
The system of claim 20, wherein the host device is further configured to:
determine that the pilot command was erroneously transmitted to the memory device; and P. 0028 CRC processing unit 230 checks that the ROM code contains an error, after entering a safe mode, the ECC processing unit 240 may correct the detected error.
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Shin and Boehm with determining the pilot command was erroneously transmitted taught by Senoo.
The motivation being safe operation may be performed to avoid malfunction or operation failure (See Senoo P. 0036)
The systems of Shin, Boehm and Senoo are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Shin and Boehm with Senoo to obtain the invention as recited in claim 22.
Boehm (2020/0117393) further teaches:
transmit, to the memory device, an instruction to exit the memory command validation mode based on determining that the pilot command was erroneously transmitted to the memory device. P. 0077-78 the host may, based on feedback of the invalid command received from memory device 310, transmit a command to reset from safe mode to access mode
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kimball et al. (U.S PGPub No. 2023/0195376) teaches a host providing information to a controller about the order it intends to read the file, by sending a list of LBAs in the order that the host intends to read the file
Kimball et al. (U.S. Patent No. 8621238) a table containing an approved list of sequences of instructions, and determining whether to execute received instructions based on the table.
Sandoval et al. (U.S. PGPub No. 2019/0317676) teaches generating a whitelist of commands based on received input, using the whitelist to determine whether instructions should be permitted.
Oikawa et al. (U.S. PGPub No. 2015/0254022) teaches a host setting control register information specifying an order of commands
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/STEPHANIE WU/ Primary Examiner, Art Unit 2133