Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 4, 6, 8, 9, 11, 13, 14, 16, 18, 19, 21, 23, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over US20020075077A1 (Farine) in view of US20210175892A1 (Mueller) and in view of US4905176A (Schulz).
In regards to claim 1 (Farine) shows a method, comprising:
generating, by a system using a numerical controlled oscillator (NCO) operating using a first clock of the system, a baseline quantum computing signal as a reference for evaluating responses from a quantum computer to noises; Farine [0018] teaches a numerically controlled oscillator that includes a first accumulation stage for a first number of most-significant bits of the binary word, the first accumulation stage being clocked by the clock signal at the first frequency to supply the output signal at a determined frequency. Farine [0036] teaches the first accumulation stage is clocked by a clock signal at a first frequency CLK which can have a value of 4.36 MHz for application in a low power GPS receiver.
generating, by the system using a noise generator of the NCO, a noise signal based on a number generated by a number generator operating using a second clock of the system that is different from the first clock; Farine [0018] teaches a second accumulation stage for a second number of least-significant bits of said binary word, while the second stage is clocked by a clock signal at a second frequency N times lower than the first clock frequency. Farine [0037] teaches the second accumulation stage is clocked by a clock signal at a second frequency CLK/N which is N times less than first clock frequency CLK.
Farine differs from the claimed invention in that it does not explicitly disclose supplying, by the system, via a digital to analog converter (DAC), the baseline quantum computing signal to the quantum computer to obtain a first quantum output from the quantum computer; the noise generator being implemented as a state machine that is separate from a phase accumulator of the NCO, and the number generator being clocked asynchronously to the first clock to decorrelate values generated by the number generator from phase accumulation of the NCO; injecting, by the system, via the DAC, the noise signal to the quantum computer to obtain a second quantum output from the quantum computer; determining, by the system, an effect of the noise signal on the quantum computer based on the first quantum output and the second quantum output;
Mueller teaches supplying, by the system, via a digital to analog converter (DAC), the baseline quantum computing signal to the quantum computer to obtain a first quantum output from the quantum computer; Mueller [0035] teaches an ultra-fast arbitrary waveform generator AWG implemented as an integrated digital-to-analog converter DAC with waveform memory at the input for quantum computing applications. Mueller [0042] teaches a DAC can be provided in front of the receiving unit to allow signal cancelation for quantum systems.
Mueller teaches injecting, by the system, via the DAC, the noise signal to the quantum computer to obtain a second quantum output from the quantum computer; Mueller [0044] teaches cancelation signals emitted by the SCU to linearly combine with analog signals received from the qubits, prior to feeding the combined signals to the DSADC. Mueller [0035] teaches the DAC with waveform memory allows direct signal synthesis for quantum operations.
Mueller teaches determining, by the system, an effect of the noise signal on the quantum computer based on the first quantum output and the second quantum output; Mueller [0021] teaches the DSADC is configured to downsample analog signals obtained from the qubits to down-convert such analog signals from the nth Nyquist zone to the mth Nyquist zone for analysis and comparison.
Mueller differs from the claimed invention in that it does not explicitly disclose the noise generator being implemented as a state machine that is separate from a phase accumulator of the NCO, and the number generator being clocked asynchronously to the first clock to decorrelate values generated by the number generator from phase accumulation of the NCO;
Schulz teaches the noise generator being implemented as a state machine that is separate from a phase accumulator of the NCO, and the number generator being clocked asynchronously to the first clock to decorrelate values generated by the number generator from phase accumulation of the NCO; Schulz [Column 2 Lines 10 - 30] teaches a free-running ring oscillator used to drive a sampled linear feedback shift register asynchronously from the system clock, wherein the linear feedback shift register is a state machine operating independently from the system clock, and the asynchronous clocking introduces randomly occurring deviations that decorrelate the pseudorandom number output from system clock periodicity.
The motivation to combine Farine and Mueller at the effective filing date of the invention is to implement quantum computing applications using robust NCO architecture for noisy environments. Farine teaches dual-clock NCO systems designed for extracting signals from disturbed environments, while Mueller teaches quantum computing with DAC integration. A person of ordinary skill would combine these to achieve quantum noise testing using Farine's proven NCO architecture with Mueller's quantum-specific DAC techniques.
The motivation to combine Farine, Mueller, and Schulz at the effective filing date of the invention is to produce less correlated noise in quantum noise testing by incorporating an asynchronous number generator separate from the NCO phase accumulator. A person of ordinary skill would combine Schulz's asynchronous free-running ring oscillator technique with Farine's NCO architecture and Mueller's quantum DAC integration to reduce periodic noise artifacts caused by synchronous clocking.
In regards to claim 3 (Farine) shows the method of claim 1:
wherein the noise signal comprises at least one of amplitude noise or jitter; Farine [0003] teaches these numerically controlled oscillators are used in fields of applications where the environment is noisy and signals used have to be extracted from the greatly disturbed radiofrequency signals. Farine [0020] teaches this multiphase oscillator is especially useful in a noisy environment as in the case of GPS type radiofrequency signals.
In regards to claim 4 (Farine) shows the method of claim 1:
wherein the second clock is a non-integer clock; Farine [0037] teaches the second clock frequency is fixed at 16 times less than the first clock frequency and may have a value of 272.5 kHz when the first clock frequency is 4.36 MHz. Farine [0022] teaches N is a power of 2, where N is preferably chosen to have a value 2m where m is an integer number greater than 0, creating non-integer frequency relationships.
In regards to claim 6 (Farine) shows:
A computer program product for testing quantum computer responses to noises, the computer program product comprising one or more non-transitory computer readable storage media; Farine [0007] teaches said receivers also include a microprocessor connected to the correlation stage and intended to calculate position, speed and time data as a function of the data extracted from the GPS signals. Farine [0063] teaches the data of the demodulated messages are signals provided to the microprocessor which follows the correlation stage.
program instructions collectively stored on the one or more computer readable storage media, the program instructions executable by a processor to perform operations comprising: generating, using a numerical controlled oscillator (NCO) operating using a first clock of the system, a baseline quantum computing signal as a reference for evaluating responses from a quantum computer to noises; Farine [0018] teaches a numerically controlled oscillator that includes a first accumulation stage for a first number of most-significant bits of the binary word, the first accumulation stage being clocked by the clock signal at the first frequency to supply the output signal at a determined frequency. Farine [0036] teaches the first accumulation stage is clocked by a clock signal at a first frequency CLK which can have a value of 4.36 MHz for application in a low power GPS receiver.
generating, using a noise generator of the NCO, a noise signal based on a number generated by a number generator operating using a second clock of the system that is different from the first clock; Farine [0018] teaches a second accumulation stage for a second number of least-significant bits of said binary word, while the second stage is clocked by a clock signal at a second frequency N times lower than the first clock frequency. Farine [0037] teaches the second accumulation stage is clocked by a clock signal at a second frequency CLK/N which is N times less than first clock frequency CLK.
Farine differs from the claimed invention in that it does not explicitly disclose supplying, via a digital to analog converter (DAC), the baseline quantum computing signal to the quantum computer to obtain a first quantum output from the quantum computer; injecting, via the DAC, the noise signal to the quantum computer to obtain a second quantum output from the quantum computer; determining an effect of the noise signal on the quantum computer based on the first quantum output and the second quantum output;
Mueller teaches supplying, via a digital to analog converter (DAC), the baseline quantum computing signal to the quantum computer to obtain a first quantum output from the quantum computer; Mueller [0035] teaches an ultra-fast arbitrary waveform generator AWG implemented as an integrated digital-to-analog converter DAC with waveform memory at the input for quantum computing applications. Mueller [0042] teaches a DAC can be provided in front of the receiving unit to allow signal cancelation for quantum systems.
Mueller teaches injecting, via the DAC, the noise signal to the quantum computer to obtain a second quantum output from the quantum computer; Mueller [0044] teaches cancelation signals emitted by the SCU to linearly combine with analog signals received from the qubits, prior to feeding the combined signals to the DSADC. Mueller [0035] teaches the DAC with waveform memory allows direct signal synthesis for quantum operations.
Mueller teaches determining an effect of the noise signal on the quantum computer based on the first quantum output and the second quantum output; Mueller [0021] teaches the DSADC is configured to downsample analog signals obtained from the qubits to down-convert such analog signals from the nth Nyquist zone to the mth Nyquist zone for analysis and comparison.
Mueller differs from the claimed invention in that it does not explicitly disclose the noise generator being implemented as a state machine that is separate from a phase accumulator of the NCO, and the number generator being clocked asynchronously to the first clock to decorrelate values generated by the number generator from phase accumulation of the NCO;
Schulz teaches the noise generator being implemented as a state machine that is separate from a phase accumulator of the NCO, and the number generator being clocked asynchronously to the first clock to decorrelate values generated by the number generator from phase accumulation of the NCO; Schulz [Column 2 Lines 10 - 30] teaches a free-running ring oscillator used to drive a sampled linear feedback shift register asynchronously from the system clock, wherein the linear feedback shift register is a state machine operating independently from the system clock, and the asynchronous clocking introduces randomly occurring deviations that decorrelate the pseudorandom number output from system clock periodicity.
The motivation to combine Farine and Mueller at the effective filing date of the invention is to implement quantum computing applications using robust NCO architecture for noisy environments. Farine teaches dual-clock NCO systems designed for extracting signals from disturbed environments, while Mueller teaches quantum computing with DAC integration. A person of ordinary skill would combine these to achieve quantum noise testing using Farine's proven NCO architecture with Mueller's quantum-specific DAC techniques.
The motivation to combine Farine, Mueller, and Schulz at the effective filing date of the invention is to produce less correlated noise in quantum noise testing by incorporating an asynchronous number generator separate from the NCO phase accumulator. A person of ordinary skill would combine Schulz's asynchronous free-running ring oscillator technique with Farine's NCO architecture and Mueller's quantum DAC integration to reduce periodic noise artifacts caused by synchronous clocking.
In regards to claim 8 (Farine) shows the computer program product of claim 6:
wherein the noise signal comprises at least one of amplitude noise or jitter; Farine [0003] teaches these numerically controlled oscillators are used in fields of applications where the environment is noisy and signals used have to be extracted from the greatly disturbed radiofrequency signals. Farine [0020] teaches this multiphase oscillator is especially useful in a noisy environment as in the case of GPS type radiofrequency signals.
In regards to claim 9 (Farine) shows the computer program product of claim 6:
wherein the second clock is a non-integer clock; Farine [0037] teaches the second clock frequency is fixed at 16 times less than the first clock frequency and may have a value of 272.5 kHz when the first clock frequency is 4.36 MHz. Farine [0022] teaches N is a power of 2, where N is preferably chosen to have a value 2m where m is an integer number greater than 0, creating non-integer frequency relationships.
In regards to claim 11 (Farine) shows A system, comprising:
a memory configured to store program instructions; Farine [0011] teaches the GPS receivers generally include the data for these codes in a memory connected to the receiver microprocessor. Farine [0048] teaches the second binary word concerning a value relating to the code or frequency carrier extracted from a memory of the receiver.
a processor configured to execute at least one of the program instructions that: Farine [0007] teaches said receivers also include a microprocessor connected to the correlation stage and intended to calculate position, speed and time data as a function of the data extracted from the GPS signals.
generates, using a numerical controlled oscillator (NCO) operating using a first clock of the system, a baseline quantum computing signal as a reference for evaluating responses, from a quantum computer to noises; Farine [0018] teaches a numerically controlled oscillator that includes a first accumulation stage for a first number of most-significant bits of the binary word, the first accumulation stage being clocked by the clock signal at the first frequency to supply the output signal at a determined frequency. Farine [0036] teaches the first accumulation stage is clocked by a clock signal at a first frequency CLK which can have a value of 4.36 MHz for application in a low power GPS receiver.
generates, using a noise generator of the NCO, a noise signal based on a number generated by a number generator operating using a second clock of the system that is different from the first clock; Farine [0018] teaches a second accumulation stage for a second number of least-significant bits of said binary word, while the second stage is clocked by a clock signal at a second frequency N times lower than the first clock frequency. Farine [0037] teaches the second accumulation stage is clocked by a clock signal at a second frequency CLK/N which is N times less than first clock frequency CLK.
Farine differs from the claimed invention in that it does not explicitly disclose supplies, via a digital to analog converter (DAC), the baseline quantum computing signal to the quantum computer to obtain a first quantum output from the quantum computer; injects, via the DAC, the noise signal to the quantum computer to obtain a second quantum output from the quantum computer; determines an effect of the noise signal on the quantum computer based on the first quantum output and the second quantum output;
Mueller teaches supplies, via a digital to analog converter (DAC), the baseline quantum computing signal to the quantum computer to obtain a first quantum output from the quantum computer; Mueller [0035] teaches an ultra-fast arbitrary waveform generator AWG implemented as an integrated digital-to-analog converter DAC with waveform memory at the input for quantum computing applications. Mueller [0042] teaches a DAC can be provided in front of the receiving unit to allow signal cancelation for quantum systems.
Mueller teaches injects, via the DAC, the noise signal to the quantum computer to obtain a second quantum output from the quantum computer; Mueller [0044] teaches cancelation signals emitted by the SCU to linearly combine with analog signals received from the qubits, prior to feeding the combined signals to the DSADC. Mueller [0035] teaches the DAC with waveform memory allows direct signal synthesis for quantum operations.
Mueller teaches determines an effect of the noise signal on the quantum computer based on the first quantum output and the second quantum output; Mueller [0021] teaches the DSADC is configured to downsample analog signals obtained from the qubits to down-convert such analog signals from the nth Nyquist zone to the mth Nyquist zone for analysis and comparison.
Mueller differs from the claimed invention in that it does not explicitly disclose the noise generator being implemented as a state machine that is separate from a phase accumulator of the NCO, and the number generator being clocked asynchronously to the first clock to decorrelate values generated by the number generator from phase accumulation of the NCO;
Schulz teaches the noise generator being implemented as a state machine that is separate from a phase accumulator of the NCO, and the number generator being clocked asynchronously to the first clock to decorrelate values generated by the number generator from phase accumulation of the NCO; Schulz [Column 2 Lines 10 - 30] teaches a free-running ring oscillator used to drive a sampled linear feedback shift register asynchronously from the system clock, wherein the linear feedback shift register is a state machine operating independently from the system clock, and the asynchronous clocking introduces randomly occurring deviations that decorrelate the pseudorandom number output from system clock periodicity.
The motivation to combine Farine and Mueller at the effective filing date of the invention is to implement quantum computing applications using robust NCO architecture for noisy environments. Farine teaches dual-clock NCO systems designed for extracting signals from disturbed environments, while Mueller teaches quantum computing with DAC integration. A person of ordinary skill would combine these to achieve quantum noise testing using Farine's proven NCO architecture with Mueller's quantum-specific DAC techniques.
The motivation to combine Farine, Mueller, and Schulz at the effective filing date of the invention is to produce less correlated noise in quantum noise testing by incorporating an asynchronous number generator separate from the NCO phase accumulator. A person of ordinary skill would combine Schulz's asynchronous free-running ring oscillator technique with Farine's NCO architecture and Mueller's quantum DAC integration to reduce periodic noise artifacts caused by synchronous clocking.
In regards to claim 13 (Farine) shows the controller module of claim 11:
wherein the noise signal comprises at least one of amplitude noise or jitter; Farine [0003] teaches these numerically controlled oscillators are used in fields of applications where the environment is noisy and signals used have to be extracted from the greatly disturbed radiofrequency signals. Farine [0020] teaches this multiphase oscillator is especially useful in a noisy environment as in the case of GPS type radiofrequency signals.
In regards to claim 14 (Farine) shows the controller module of claim 11:
wherein the second clock is a non-integer clock; Farine [0037] teaches the second clock frequency is fixed at 16 times less than the first clock frequency and may have a value of 272.5 kHz when the first clock frequency is 4.36 MHz. Farine [0022] teaches N is a power of 2, where N is preferably chosen to have a value 2m where m is an integer number greater than 0, creating non-integer frequency relationships.
In regards to claim 16 (Farine) shows a quantum computing system, comprising:
a memory configured to store program instructions; Farine [0011] teaches the GPS receivers generally include the data for these codes in a memory connected to the receiver microprocessor. Farine [0048] teaches the second binary word concerning a value relating to the code or frequency carrier extracted from a memory of the receiver.
a processor configured to execute at least one of the program instructions that; Farine [0007] teaches said receivers also include a microprocessor connected to the correlation stage and intended to calculate position, speed and time data as a function of the data extracted from the GPS signals.
generates, using a numerical controlled oscillator (NCO) operating using a first clock of the system, a baseline quantum computing signal as a reference for evaluating responses from the device to noises; Farine [0018] teaches a numerically controlled oscillator that includes a first accumulation stage for a first number of most-significant bits of the binary word, the first accumulation stage being clocked by the clock signal at the first frequency to supply the output signal at a determined frequency. Farine [0036] teaches the first accumulation stage is clocked by a clock signal at a first frequency CLK which can have a value of 4.36 MHz for application in a low power GPS receiver.
generates, using a noise generator of the NCO, a noise signal based on a number generated by a number generator operating using a second clock of the quantum computing system that is different from the first clock; Farine [0018] teaches a second accumulation stage for a second number of least-significant bits of said binary word, while the second stage is clocked by a clock signal at a second frequency N times lower than the first clock frequency. Farine [0037] teaches the second accumulation stage is clocked by a clock signal at a second frequency CLK/N which is N times less than first clock frequency CLK.
Farine differs from the claimed invention in that it does not explicitly disclose a device comprising qubits; supplies, via a digital to analog converter (DAC), the baseline quantum computing signal to the device to obtain a first quantum output from the device; injects, via the DAC, the noise signal to the device to obtain a second quantum output from the device; determines an effect of the noise signal on the device based on the first quantum output and the second quantum output;
Mueller teaches a device comprising qubits; Mueller [0019] teaches the apparatus comprises M solid-state qubits where M is greater than 1. Mueller [0027] teaches the solid-state qubits can be superconducting quantum circuits controlled by radio frequency RF technology.
Mueller teaches supplies, via a digital to analog converter (DAC), the baseline quantum computing signal to the device to obtain a first quantum output from the device; Mueller [0035] teaches an ultra-fast arbitrary waveform generator AWG implemented as an integrated digital-to-analog converter DAC with waveform memory at the input for quantum computing applications. Mueller [0042] teaches a DAC can be provided in front of the receiving unit to allow signal cancelation for quantum systems.
Mueller teaches injects, via the DAC, the noise signal to the device to obtain a second quantum output from the device; Mueller [0044] teaches cancelation signals emitted by the SCU to linearly combine with analog signals received from the qubits, prior to feeding the combined signals to the DSADC. Mueller [0035] teaches the DAC with waveform memory allows direct signal synthesis for quantum operations.
Mueller teaches determines an effect of the noise signal on the device based on the first quantum output and the second quantum output; Mueller [0021] teaches the DSADC is configured to downsample analog signals obtained from the qubits to down-convert such analog signals from the nth Nyquist zone to the mth Nyquist zone for analysis and comparison.
Mueller differs from the claimed invention in that it does not explicitly disclose the noise generator being implemented as a state machine that is separate from a phase accumulator of the NCO, and the number generator being clocked asynchronously to the first clock to decorrelate values generated by the number generator from phase accumulation of the NCO;
Schulz teaches the noise generator being implemented as a state machine that is separate from a phase accumulator of the NCO, and the number generator being clocked asynchronously to the first clock to decorrelate values generated by the number generator from phase accumulation of the NCO; Schulz [Column 2 Lines 10 - 30] teaches a free-running ring oscillator used to drive a sampled linear feedback shift register asynchronously from the system clock, wherein the linear feedback shift register is a state machine operating independently from the system clock, and the asynchronous clocking introduces randomly occurring deviations that decorrelate the pseudorandom number output from system clock periodicity.
The motivation to combine Farine and Mueller at the effective filing date of the invention is to implement quantum computing applications using robust NCO architecture for noisy environments. Farine teaches dual-clock NCO systems designed for extracting signals from disturbed environments, while Mueller teaches quantum computing with DAC integration. A person of ordinary skill would combine these to achieve quantum noise testing using Farine's proven NCO architecture with Mueller's quantum-specific DAC techniques.
The motivation to combine Farine, Mueller, and Schulz at the effective filing date of the invention is to produce less correlated noise in quantum noise testing by incorporating an asynchronous number generator separate from the NCO phase accumulator. A person of ordinary skill would combine Schulz's asynchronous free-running ring oscillator technique with Farine's NCO architecture and Mueller's quantum DAC integration to reduce periodic noise artifacts caused by synchronous clocking.
In regards to claim 18 (Farine) shows the quantum computing system of claim 16:
wherein the noise signal comprises at least one of amplitude noise or jitter; Farine [0003] teaches these numerically controlled oscillators are used in fields of applications where the environment is noisy and signals used have to be extracted from the greatly disturbed radiofrequency signals. Farine [0020] teaches this multiphase oscillator is especially useful in a noisy environment as in the case of GPS type radiofrequency signals.
In regards to claim 19 (Farine) shows the quantum computing system of claim 16:
wherein the second clock is a non-integer clock; Farine [0037] teaches the second clock frequency is fixed at 16 times less than the first clock frequency and may have a value of 272.5 kHz when the first clock frequency is 4.36 MHz. Farine [0022] teaches N is a power of 2, where N is preferably chosen to have a value 2m where m is an integer number greater than 0, creating non-integer frequency relationships.
In regards to claim 21 (Farine) shows a numerically controlled oscillator, comprising:
a phase accumulator module operating using a first clock, wherein the phase accumulator module is configured to: generate a baseline quantum computing signal responses from a quantum computer to noises; Farine [0012] teaches the oscillator receives at one input a clock signal with a first frequency clocking the oscillator operations to provide at one output at least a signal with a frequency determined as a function of said binary word and the clock signal. Farine [0034] teaches the first accumulation stage is formed of a phase register followed by a phase accumulator supplying a certain number of output binary signals including the determined frequency output signals.
supply, via a phase to amplitude converter module the baseline quantum computing signal to the quantum computer to obtain a first quantum output from the quantum computer; Farine [0034] teaches the first accumulation stage is formed of a phase register followed by a phase accumulator supplying a certain number of output binary signals including the determined frequency output signals. Farine [0034] teaches the signals are selected from among the most-significant bits at the output of accumulator 12.
a noise source controller module, wherein the noise source controller is configured to: generate, using a noise generator of the NCO, a noise signal based on a number generated by a number generator operating using a second clock that is different from the first clock; Farine [0018] teaches a second accumulation stage for least-significant bits clocked by a clock signal at a second frequency N times lower than the first clock frequency. Farine [0033] teaches certain number of output binary bits from the second stage are introduced at the input of the first stage every N cycles of the clock signal at the first frequency.
supplies, via the phase to amplitude converter module, the baseline quantum computing signal to the quantum computer to obtain a first quantum output from the quantum computer; Farine [0034] teaches the first accumulation stage is formed of a phase register followed by a phase accumulator supplying a certain number of output binary signals including the determined frequency output signals. Farine [0034] teaches the signals are selected from among the most-significant bits at the output of accumulator 12.
Farine differs from the claimed invention in that it does not explicitly disclose inject, via the phase to amplitude converter module, the noise signal to the quantum computer to obtain a second quantum output from the quantum computer; determine an effect of the noise signal on the quantum computer based on the first quantum output and the second quantum output;
Mueller teaches inject, via the phase to amplitude converter module, the noise signal to the quantum computer to obtain a second quantum output from the quantum computer; Mueller [0044] teaches cancelation signals emitted by the SCU to linearly combine with analog signals received from the qubits, prior to feeding the combined signals to the DSADC. Mueller [0035] teaches the DAC with waveform memory allows direct signal synthesis for quantum operations.
Mueller teaches determine an effect of the noise signal on the quantum computer based on the first quantum output and the second quantum output; Mueller [0021] teaches the DSADC is configured to downsample analog signals obtained from the qubits to down-convert such analog signals from the nth Nyquist zone to the mth Nyquist zone for analysis and comparison.
Mueller differs from the claimed invention in that it does not explicitly disclose the noise generator being implemented as a state machine that is separate from a phase accumulator of the NCO, and the number generator being clocked asynchronously to the first clock to decorrelate values generated by the number generator from phase accumulation of the NCO;
Schulz teaches the noise generator being implemented as a state machine that is separate from a phase accumulator of the NCO, and the number generator being clocked asynchronously to the first clock to decorrelate values generated by the number generator from phase accumulation of the NCO; Schulz [Column 2 Lines 10 - 30] teaches a free-running ring oscillator used to drive a sampled linear feedback shift register asynchronously from the system clock, wherein the linear feedback shift register is a state machine operating independently from the system clock, and the asynchronous clocking introduces randomly occurring deviations that decorrelate the pseudorandom number output from system clock periodicity.
The motivation to combine Farine and Mueller at the effective filing date of the invention is to implement quantum computing applications using robust NCO architecture for noisy environments. Farine teaches dual-clock NCO systems designed for extracting signals from disturbed environments, while Mueller teaches quantum computing with DAC integration. A person of ordinary skill would combine these to achieve quantum noise testing using Farine's proven NCO architecture with Mueller's quantum-specific DAC techniques.
The motivation to combine Farine, Mueller, and Schulz at the effective filing date of the invention is to produce less correlated noise in quantum noise testing by incorporating an asynchronous number generator separate from the NCO phase accumulator. A person of ordinary skill would combine Schulz's asynchronous free-running ring oscillator technique with Farine's NCO architecture and Mueller's quantum DAC integration to reduce periodic noise artifacts caused by synchronous clocking.
In regards to claim 23 (Farine) shows the numerically controlled oscillator of claim 21:
wherein the noise signal comprises at least one of amplitude noise or jitter; Farine [0003] teaches these numerically controlled oscillators are used in fields of applications where the environment is noisy and signals used have to be extracted from the greatly disturbed radiofrequency signals. Farine [0020] teaches this multiphase oscillator is especially useful in a noisy environment as in the case of GPS type radiofrequency signals.
In regards to claim 24 (Farine) shows the numerically controlled oscillator of claim 21:
wherein the second clock is a non-integer clock; Farine [0037] teaches the second clock frequency is fixed at 16 times less than the first clock frequency and may have a value of 272.5 kHz when the first clock frequency is 4.36 MHz. Farine [0022] teaches N is a power of 2, where N is preferably chosen to have a value 2m where m is an integer number greater than 0, creating non-integer frequency relationships.
Claims 2, 7, 12, 17, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over US20020075077A1 (Farine) in view of US20210175892A1 (Mueller) and in view of US4905176A (Schulz) as applied in claim 1, 11, 16, and 21 above, respectively, and further in view of US20110095830A1 (Tsangaropoulos) and in view of US4901265A (Kerr).
In regards to claim 2 (Farine modified by Mueller and Schulz) does not show the method of claim 1: wherein the number generator is configured to generate offset values having a user-controlled statistical distribution, including at least one of a Gaussian distribution or a bimodal distribution;
Tsangaropoulos teaches wherein the number generator is configured to generate offset values having a user-controlled statistical distribution, including at least one of a Gaussian distribution or a bimodal distribution; Tsangaropoulos [0109][0111] teaches a Controlled PRN Generator comprising a dither control circuit that receives user-provided dither enable and dither select signals to control a multiplexer that selects between zero-mean and non-zero-mean PRN generators, whereby the user directly controls the statistical distribution of the generated pseudo-random sequence.
Tsangaropoulos differs from the claimed invention in that it does not explicitly disclose wherein the noise signal is derived from the offset values;
Kerr teaches wherein the noise signal is derived from the offset values; Kerr teaches pseudorandom numbers generated by a number generator are added to sine amplitude data prior to digital-to-analog conversion, wherein the noise signal is derived directly from the offset values produced by the number generator.
The motivation to combine Farine, Mueller, Schulz, and Tsangaropoulos at the effective filing date of the invention is to provide user-controlled statistical distributions for quantum noise testing. A person of ordinary skill would incorporate Tsangaropoulos's controllable PRN generator into the combined Farine, Mueller, and Schulz system to allow selection of different noise distributions for comprehensive quantum noise characterization.
The motivation to combine Farine, Mueller, Schulz, Tsangaropoulos, and Kerr at the effective filing date of the invention is to derive the noise signal directly from the offset values generated by the number generator. A person of ordinary skill would incorporate Kerr's technique of adding pseudorandom offset values to amplitude data to implement the noise signal derivation required by the claimed system.
In regards to claim 7 (Farine modified by Mueller and Schulz) does not show the computer program product of claim 6: wherein the number generator is configured to generate offset values having a user-controlled statistical distribution, including at least one of a Gaussian distribution or a bimodal distribution;
Tsangaropoulos teaches wherein the number generator is configured to generate offset values having a user-controlled statistical distribution, including at least one of a Gaussian distribution or a bimodal distribution; Tsangaropoulos [0109][0111] teaches a Controlled PRN Generator comprising a dither control circuit that receives user-provided dither enable and dither select signals to control a multiplexer that selects between zero-mean and non-zero-mean PRN generators, whereby the user directly controls the statistical distribution of the generated pseudo-random sequence.
Tsangaropoulos differs from the claimed invention in that it does not explicitly disclose wherein the noise signal is derived from the offset values;
Kerr teaches wherein the noise signal is derived from the offset values; Kerr teaches pseudorandom numbers generated by a number generator are added to sine amplitude data prior to digital-to-analog conversion, wherein the noise signal is derived directly from the offset values produced by the number generator.
The motivation to combine Farine, Mueller, Schulz, and Tsangaropoulos at the effective filing date of the invention is to provide user-controlled statistical distributions for quantum noise testing. A person of ordinary skill would incorporate Tsangaropoulos's controllable PRN generator into the combined Farine, Mueller, and Schulz system to allow selection of different noise distributions for comprehensive quantum noise characterization.
The motivation to combine Farine, Mueller, Schulz, Tsangaropoulos, and Kerr at the effective filing date of the invention is to derive the noise signal directly from the offset values generated by the number generator. A person of ordinary skill would incorporate Kerr's technique of adding pseudorandom offset values to amplitude data to implement the noise signal derivation required by the claimed system.
In regards to claim 12 (Farine modified by Mueller and Schulz) does not show the controller module of claim 11: wherein the number generator is configured to generate offset values having a user-controlled statistical distribution, including at least one of a Gaussian distribution or a bimodal distribution;
Tsangaropoulos teaches wherein the number generator is configured to generate offset values having a user-controlled statistical distribution, including at least one of a Gaussian distribution or a bimodal distribution; Tsangaropoulos [0109][0111] teaches a Controlled PRN Generator comprising a dither control circuit that receives user-provided dither enable and dither select signals to control a multiplexer that selects between zero-mean and non-zero-mean PRN generators, whereby the user directly controls the statistical distribution of the generated pseudo-random sequence.
Tsangaropoulos differs from the claimed invention in that it does not explicitly disclose wherein the noise signal is derived from the offset values;
Kerr teaches wherein the noise signal is derived from the offset values; Kerr teaches pseudorandom numbers generated by a number generator are added to sine amplitude data prior to digital-to-analog conversion, wherein the noise signal is derived directly from the offset values produced by the number generator.
The motivation to combine Farine, Mueller, Schulz, and Tsangaropoulos at the effective filing date of the invention is to provide user-controlled statistical distributions for quantum noise testing. A person of ordinary skill would incorporate Tsangaropoulos's controllable PRN generator into the combined Farine, Mueller, and Schulz system to allow selection of different noise distributions for comprehensive quantum noise characterization.
The motivation to combine Farine, Mueller, Schulz, Tsangaropoulos, and Kerr at the effective filing date of the invention is to derive the noise signal directly from the offset values generated by the number generator. A person of ordinary skill would incorporate Kerr's technique of adding pseudorandom offset values to amplitude data to implement the noise signal derivation required by the claimed system.
In regards to claim 17 (Farine modified by Mueller and Schulz) does not show the quantum computing system of claim 16: wherein the number generator is configured to generate offset values having a user-controlled statistical distribution, including at least one of a Gaussian distribution or a bimodal distribution;
Tsangaropoulos teaches wherein the number generator is configured to generate offset values having a user-controlled statistical distribution, including at least one of a Gaussian distribution or a bimodal distribution; Tsangaropoulos [0109][0111] teaches a Controlled PRN Generator comprising a dither control circuit that receives user-provided dither enable and dither select signals to control a multiplexer that selects between zero-mean and non-zero-mean PRN generators, whereby the user directly controls the statistical distribution of the generated pseudo-random sequence.
Tsangaropoulos differs from the claimed invention in that it does not explicitly disclose wherein the noise signal is derived from the offset values;
Kerr teaches wherein the noise signal is derived from the offset values; Kerr teaches pseudorandom numbers generated by a number generator are added to sine amplitude data prior to digital-to-analog conversion, wherein the noise signal is derived directly from the offset values produced by the number generator.
The motivation to combine Farine, Mueller, Schulz, and Tsangaropoulos at the effective filing date of the invention is to provide user-controlled statistical distributions for quantum noise testing. A person of ordinary skill would incorporate Tsangaropoulos's controllable PRN generator into the combined Farine, Mueller, and Schulz system to allow selection of different noise distributions for comprehensive quantum noise characterization.
The motivation to combine Farine, Mueller, Schulz, Tsangaropoulos, and Kerr at the effective filing date of the invention is to derive the noise signal directly from the offset values generated by the number generator. A person of ordinary skill would incorporate Kerr's technique of adding pseudorandom offset values to amplitude data to implement the noise signal derivation required by the claimed system.
In regards to claim 22 (Farine modified by Mueller and Schulz) does not show the numerically controlled oscillator of claim 21:
Tsangaropoulos teaches wherein the number generator is configured to generate offset values having a user-controlled statistical distribution, including at least one of a Gaussian distribution or a bimodal distribution; Tsangaropoulos [0109][0111] teaches a Controlled PRN Generator comprising a dither control circuit that receives user-provided dither enable and dither select signals to control a multiplexer that selects between zero-mean and non-zero-mean PRN generators, whereby the user directly controls the statistical distribution of the generated pseudo-random sequence.
Tsangaropoulos differs from the claimed invention in that it does not explicitly disclose wherein the noise signal is derived from the offset values;
Kerr teaches wherein the noise signal is derived from the offset values; Kerr teaches pseudorandom numbers generated by a number generator are added to sine amplitude data prior to digital-to-analog conversion, wherein the noise signal is derived directly from the offset values produced by the number generator.
The motivation to combine Farine, Mueller, Schulz, and Tsangaropoulos at the effective filing date of the invention is to provide user-controlled statistical distributions for quantum noise testing. A person of ordinary skill would incorporate Tsangaropoulos's controllable PRN generator into the combined Farine, Mueller, and Schulz system to allow selection of different noise distributions for comprehensive quantum noise characterization.
The motivation to combine Farine, Mueller, Schulz, Tsangaropoulos, and Kerr at the effective filing date of the invention is to derive the noise signal directly from the offset values generated by the number generator. A person of ordinary skill would incorporate Kerr's technique of adding pseudorandom offset values to amplitude data to implement the noise signal derivation required by the claimed system.
Claims 5, 10, 15, 20, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over US20020075077A1 (Farine) in view of US20210175892A1 (Mueller) and in view of US4905176A (Schulz) as applied in claim 1, 11, 16, and 21 above, respectively, and further in view of US20100194444A1 (Patterson).
In regards to claim 5 (Farine) shows the method of claim 1:
wherein generating the noise comprises selecting an amount of noise for the noise signal based on an offset value added to a value obtained from a look up table associated with the number; Farine [0048] teaches a second binary word is added to the first binary word of the loop in the oscillator, where this second binary word concerns a value relating to the code or frequency carrier extracted from a memory of the receiver. Farine [0011] teaches the GPS receivers generally include the data for these codes in a memory, as well as the estimated position of each corresponding satellite in orbit.
Farine differs from the claimed invention in that it does not explicitly disclose wherein the look up table stores baseline phase-to-amplitude conversion values of the NCO;
Patterson teaches wherein the look up table stores baseline phase-to-amplitude conversion values of the NCO; Patterson [0026] teaches for each incremental phase word output from the phase accumulator there is a corresponding amplitude value stored in lookup tables 208 and 209, which store sine and cosine amplitude values corresponding to phase inputs, constituting baseline phase-to-amplitude conversion values of the NCO.
The motivation to combine Farine, Mueller, Schulz, and Patterson at the effective filing date of the invention is to implement a phase-to-amplitude lookup table storing baseline NCO conversion values for noise selection. A person of ordinary skill would incorporate Patterson's sine and cosine lookup tables into the combined Farine, Mueller, and Schulz system to enable offset-based noise generation referenced to baseline NCO amplitude values.
In regards to claim 10 (Farine) shows the computer program product of claim 6:
wherein generating the noise comprises selecting an amount of noise for the noise signal based an offset value added to a value obtained from a look up table associated with the number; Farine [0048] teaches a second binary word is added to the first binary word of the loop in the oscillator, where this second binary word concerns a value relating to the code or frequency carrier extracted from a memory of the receiver. Farine [0011] teaches the GPS receivers generally include the data for these codes in a memory, as well as the estimated position of each corresponding satellite in orbit.
Farine differs from the claimed invention in that it does not explicitly disclose wherein the look up table stores baseline phase-to-amplitude conversion values of the NCO;
Patterson teaches wherein the look up table stores baseline phase-to-amplitude conversion values of the NCO; Patterson [0026] teaches for each incremental phase word output from the phase accumulator there is a corresponding amplitude value stored in lookup tables 208 and 209, which store sine and cosine amplitude values corresponding to phase inputs, constituting baseline phase-to-amplitude conversion values of the NCO.
The motivation to combine Farine, Mueller, Schulz, and Patterson at the effective filing date of the invention is to implement a phase-to-amplitude lookup table storing baseline NCO conversion values for noise selection. A person of ordinary skill would incorporate Patterson's sine and cosine lookup tables into the combined Farine, Mueller, and Schulz system to enable offset-based noise generation referenced to baseline NCO amplitude values.
In regards to claim 15 (Farine) shows the controller module of claim 11:
wherein generating the noise comprises selecting an amount of noise for the noise signal based an offset value added to a value obtained from a look up table associated with the number; Farine [0048] teaches a second binary word is added to the first binary word of the loop in the oscillator, where this second binary word concerns a value relating to the code or frequency carrier extracted from a memory of the receiver. Farine [0011] teaches the GPS receivers generally include the data for these codes in a memory, as well as the estimated position of each corresponding satellite in orbit.
Farine differs from the claimed invention in that it does not explicitly disclose wherein the look up table stores baseline phase-to-amplitude conversion values of the NCO;
Patterson teaches wherein the look up table stores baseline phase-to-amplitude conversion values of the NCO; Patterson [0026] teaches for each incremental phase word output from the phase accumulator there is a corresponding amplitude value stored in lookup tables 208 and 209, which store sine and cosine amplitude values corresponding to phase inputs, constituting baseline phase-to-amplitude conversion values of the NCO.
The motivation to combine Farine, Mueller, Schulz, and Patterson at the effective filing date of the invention is to implement a phase-to-amplitude lookup table storing baseline NCO conversion values for noise selection. A person of ordinary skill would incorporate Patterson's sine and cosine lookup tables into the combined Farine, Mueller, and Schulz system to enable offset-based noise generation referenced to baseline NCO amplitude values.
In regards to claim 20 (Farine) shows the quantum computing system of claim 16:
wherein generating the noise comprises selecting an amount of noise for the noise signal based an offset value added to a value obtained from a look up table associated with the number; Farine [0048] teaches a second binary word is added to the first binary word of the loop in the oscillator, where this second binary word concerns a value relating to the code or frequency carrier extracted from a memory of the receiver. Farine [0011] teaches the GPS receivers generally include the data for these codes in a memory, as well as the estimated position of each corresponding satellite in orbit.
Farine differs from the claimed invention in that it does not explicitly disclose wherein the look up table stores baseline phase-to-amplitude conversion values of the NCO;
Patterson teaches wherein the look up table stores baseline phase-to-amplitude conversion values of the NCO; Patterson [0026] teaches for each incremental phase word output from the phase accumulator there is a corresponding amplitude value stored in lookup tables 208 and 209, which store sine and cosine amplitude values corresponding to phase inputs, constituting baseline phase-to-amplitude conversion values of the NCO.
The motivation to combine Farine, Mueller, Schulz, and Patterson at the effective filing date of the invention is to implement a phase-to-amplitude lookup table storing baseline NCO conversion values for noise selection. A person of ordinary skill would incorporate Patterson's sine and cosine lookup tables into the combined Farine, Mueller, and Schulz system to enable offset-based noise generation referenced to baseline NCO amplitude values.
In regards to claim 25 (Farine) shows the numerically controlled oscillator of claim 21:
wherein generating the noise comprises selecting an amount of noise for the noise signal based an offset value added to a value obtained from a look up table associated with the number; Farine [0048] teaches a second binary word is added to the first binary word of the loop in the oscillator, where this second binary word concerns a value relating to the code or frequency carrier extracted from a memory of the receiver. Farine [0011] teaches the GPS receivers generally include the data for these codes in a memory, as well as the estimated position of each corresponding satellite in orbit.
Farine differs from the claimed invention in that it does not explicitly disclose wherein the look up table stores baseline phase-to-amplitude conversion values of the NCO;
Patterson teaches wherein the look up table stores baseline phase-to-amplitude conversion values of the NCO; Patterson [0026] teaches for each incremental phase word output from the phase accumulator there is a corresponding amplitude value stored in lookup tables 208 and 209, which store sine and cosine amplitude values corresponding to phase inputs, constituting baseline phase-to-amplitude conversion values of the NCO.
The motivation to combine Farine, Mueller, Schulz, and Patterson at the effective filing date of the invention is to implement a phase-to-amplitude lookup table storing baseline NCO conversion values for noise selection. A person of ordinary skill would incorporate Patterson's sine and cosine lookup tables into the combined Farine, Mueller, and Schulz system to enable offset-based noise generation referenced to baseline NCO amplitude values.
Response to Argument
Applicant's arguments filed on March 13, 2026 have been fully considered but they are not persuasive.
The applicant argues with respect to claims 1, 6, 11, 16, and 21 that Farine does not teach a noise generator implemented as a state machine separate from the phase accumulator, and that Farine's second clock CLK/N is a synchronous integer divisor of the first clock rather than an asynchronous decorrelating clock. The applicant further argues that Mueller does not teach an NCO architecture with a separate noise generator state machine or asynchronous number generator, and that Kong does not teach asynchronous clocking for decorrelation from NCO phase accumulation.
However, the examiner respectfully disagrees. The current rejection has been updated to rely on Schulz (US4905176A) to address the state machine and asynchronous clocking limitations. Schulz [Column 2, Lines 10-30] explicitly teaches a free-running ring oscillator used to drive a sampled linear feedback shift register asynchronously from the system clock, wherein the linear feedback shift register operates as a state machine independently from the system clock, and the asynchronous clocking introduces randomly occurring deviations that decorrelate the pseudorandom number output from system clock periodicity. This directly corresponds to the applicant's claimed limitations requiring a noise generator implemented as a state machine separate from the phase accumulator and a number generator clocked asynchronously to decorrelate from NCO phase accumulation. A person of ordinary skill in the art would have been motivated to combine Schulz's asynchronous noise generator technique with Farine's NCO architecture and Mueller's quantum DAC integration to reduce periodic noise artifacts caused by synchronous clocking in quantum noise testing applications.
Regarding the applicant's argument that Farine's LSB accumulation stage is integral to the frequency synthesis path rather than a separate noise generator state machine, the examiner notes that the rejection does not rely on Farine for this limitation. Rather, Schulz expressly teaches the separate state machine and asynchronous clocking limitations, and Farine is relied upon only for the dual-clock NCO architecture and baseline signal generation limitations which remain undisputed.
For claims 2, 7, 12, 17, and 22, the applicant argues that the cited references do not teach a user-controlled statistical distribution including a Gaussian or bimodal distribution with noise derived from offset values. The current rejection has been updated to rely on Tsangaropoulos (US20110095830A1), which teaches a Controlled PRN Generator comprising a dither control circuit that receives user-provided dither enable and dither select signals to control a multiplexer that selects between zero-mean and non-zero-mean PRN generators, whereby the user directly controls the statistical distribution of the generated pseudo-random sequence. Kerr (US4901265A) further teaches that pseudorandom numbers generated by a number generator are added to amplitude data prior to digital-to-analog conversion, wherein the noise signal is derived directly from the offset values produced by the number generator.
For claims 5, 10, 15, 20, and 25, the applicant argues that the cited references do not teach a look up table storing baseline phase-to-amplitude conversion values of the NCO. The current rejection has been updated to rely on Patterson (US20100194444A1), which teaches that for each incremental phase word output from the phase accumulator there is a corresponding amplitude value stored in lookup tables 208 and 209, which store sine and cosine amplitude values corresponding to phase inputs, constituting baseline phase-to-amplitude conversion values of the NCO.
Therefore, the updated prior art combination of Farine, Mueller, and Schulz directly addresses the applicant's amended independent claim limitations, including the state machine and asynchronous clocking limitations that applicant contends are absent from the prior art. Tsangaropoulos and Kerr address the statistical distribution limitations of claims 2, 7, 12, 17, and 22, and Patterson addresses the phase-to-amplitude lookup table limitations of claims 5, 10, 15, 20, and 25. All rejections are maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANWER AHMED ALAWDI whose telephone number is (703)756-1018. The examiner can normally be reached Monday - Friday 8:00 am - 5:30 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on (571)-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANWER AHMED ALAWDI/Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851
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