DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under pre-AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-28 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 lines 3-4 recite “a second input latch capable of latching and outputting odd latch data, and a third input latch capable of latching and outputting even latch data”, with further recitation of “even latch data” and/or “odd latch data” in claim 1, claim 3, claim 4, claim 7, claim 20, claim 21, claim 26, claim 27, and claim 28. Furthermore lines 6-7 recite outputting “odd accumulation data” and outputting “even accumulation data”. It is unclear what is meant by “odd latch data”, “even latch data”, “odd accumulation data”, and “even accumulation data”. It is not clear whether the data itself comprises an even or odd value, or whether the ordering of the data is even or odd, or other. For purposes of examination, Examiner interprets as the ordering of the data is even or odd. Claims 2-28 inherit the same deficiency as claim 1 based on dependence. Further dependent claims inherit the same deficiency as claims upon which they depend with respect to claims 3, claim 4, claim 6, claim 7, claim 20, claim 21, claim 26, and claim 27 based on dependence.
Allowable Subject Matter
Claims 1-28 would be allowable if rewritten to overcome the rejections under 35 USC 112(b).
The following is a statement of reasons for indication of allowable subject matter. Applicant claims apparatus for an accumulator. The apparatus as in claim 1 comprises:
an input latch circuit including a first input latch capable of latching and outputting input data, a second input latch capable of latching and outputting odd latch data, and a third input latch capable of latching and outputting even latch data; an
accumulating circuit configured to add the input data and the odd latch data output from the input latch circuit to output odd accumulation data, and configured to add the input data and the even latch data to output even accumulation data; and
an output latch circuit including a first output latch capable of latching the odd accumulation data output from the accumulating circuit and outputting the odd latch data, and including a second output latch capable of latching the even accumulation data output from the accumulating circuit and outputting the even latch data.
The primary reason for indication of allowable subject matter are the specific configuration of the input latch circuit and the output latch circuit with respect to the accumulator circuit and with respect to even latch data, odd latch data, even accumulation data, and odd accumulation data.
US 20080046495 A1 Du et al., (hereinafter “Du”) discloses a multi-stage floating-point accumulator which includes three input latches and one output latch (abstract, figure 2-4). Du further discloses a first input latch having a delay determined by the delay of an operand alignment unit, a second latch having a delay determined by delays of a multiplexer and a second operand alignment unit, and a third latch having a delay determined by delays of a post alignment unit ([0032]). Du further discloses an output latch circuit that receives and outputs the output of an adder ([0031]). Du does not, however, teach or suggest even latch data, odd latch data, even accumulation data, and odd accumulation data in combination with the remaining limitations.
US 10127013 B1 Langhammer (hereinafter “Langhammer”) discloses a specialized processing block for performing arithmetic operations including multiply accumulation functions (abstract). Langhammer further discloses accumulation circuitry that may produce outputs that alternate between a first and second channel, e.g., even clock cycles for the first channel, and odd clock cycles for the second channel (fig 7, col 9 line 59 -col 10 line 4). Langhammer does not, however, teach or suggest the specific configuration of the input latch circuit and the output latch circuit with respect to the accumulator circuit with respect to even latch data, odd latch data, even accumulation data, and odd accumulation data in combination with the remaining limitations.
US 5490100 Kableshkov (hereinafter “Kableshkov”) discloses a summation device for cumulative summation including of floating point format data (abstract). Kableshkov further discloses a dual latch of two register associated with odd or even bytes (fig 1-112, col 8 lines 46-60). Kableshkov further disclose wherein in odd numbered clock cycles an input switch is latched of inputs data, and in even number clock cycles different input data is latched (fig 3-72, col 9 line 13-25). Kableshkov does not, however, teach or suggest the specific configuration of the input latch circuit and the output latch circuit with respect to the accumulator circuit and with respect to even latch data, odd latch data, even accumulation data, and odd accumulation data.
US 6295597 Resnick et al., (hereinafter “Resnick”) discloses an apparatus performing arithmetic operations including successive add operations (abstract). Resnick further discloses a two-pipe parallel pipeline vector including even numbered vector register elements fed into first and second pipelines (col 7 line 20-41, fig 4, 410, 412, 414 for even 411, 413, 415 for odd). Resnick does not, however, teach or suggest the specific configuration of the input latch circuit and the output latch circuit with respect to the accumulator circuit and with respect to even latch data, odd latch data, even accumulation data, and odd accumulation data.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY E LAROCQUE whose telephone number is (469)295-9289. The examiner can normally be reached on 10:00am - 1200pm, 2:00pm - 8pm ET M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor Andrew Caldwell can be reached on 571-272-3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EMILY E LAROCQUE/ Primary Examiner, Art Unit 2182