Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-29 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The Applicant responded to the previous 112 rejection that the Applicant does not wish to comment on whether Hydrogen is present when annealing in Nitrogen, and the specification is not clear on this subject, thus it seems clear that there is no support in the specification for claiming any step containing Nitrogen but no Hydrogen, thus the 112 rejection is maintained and it is also not clear if the Application is enabled.
Claims 1-29 recite both annealing in FG and annealing in nitrogen, however normally, under broadest reasonable interpretation unless the claim states “pure nitrogen” , annealing in forming gas is annealing in nitrogen because forming gas has nitrogen, however since the claims 1-29 recite both annealing in FG and annealing in nitrogen, and since there is no response from the Applicant on this subject, it is assumed that the annealing in nitrogen may or may not include hydrogen, and there is no support in the specification for claim language including nitrogen but excluding hydrogen.
See also claim 25 depends on claim 21 and in claim 25 the step (b) gas is FG whereas in claim 21 step (b) gas is N2, thus the Applicant is adding hydrogen in claim 25 .
The Examiner notes that the importance of Hydrogen is shown by evidence Lee et al. (see PTO-892) published in 2003 is provided as evidence of the known problems of forming gas, see “Thermal annealing in N2 gas ambient was usually employed to obtain low resistance Ohmic contacts. The main reason for using nitrogen gas as the annealing ambient instead of hydrogen containing gas, as commonly used by most III–V compounds, is to avoid the effect of hydrogen passivation of dopants in GaN” “Similar results were also observed in the Al/n-GaN Ohmic contacts annealed in Ar/4% H2 forming gas.19 The H2 content, however, may cause concerns in doping reduction because of hydrogen passivation. It is known that hydrogen passivation of p-type dopants in p-GaN would result in a large decrease of hole concentration.20,21 Whether annealing in forming gas ambient would lead to a similar reduction in electron concentration and increase of contact resistance of n-GaN needs to be answered. During the annealing process, H2 could diffuse into the bulk n-GaN to form neutral complexes with dopants at annealing temperature higher than 500 °C. On the other hand, the high temperature annealing process would also result in the dissociation of neutral dopant-H complexes”, thus the Examiner specifically notes that in 2003 it was already known to a person of ordinary skill in the art that adding hydrogen would cause passivation of dopants and equally, it was also known that the high temperature causes dissociation of the hydrogen, thus the question of whether or not hydrogen is present is important.
Allowable Subject Matter
Claim 4, 5, 15-19, 22, 23 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Claim 12 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3, 6, 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Adivarahan et al. (US 20100264401 A1) hereafter referred to as Adivarahan in view of Derluyn et al. (US 20200176593 A1) hereafter referred to as Derluyn. Lee et al. (see PTO-892) is provided as evidence.
In regard to claim 1 Adivarahan teaches [see 112 rejection, Applicant is unable to comment on whether Hydrogen is present during the Nitrogen anneal] a method [see Fig. 4 see paragraph 0039, 0055 “array of ultraviolet light-emitting structures, 12”] of fabricating a semiconductor device, the method comprising:
(a) depositing an epitaxial layer [“Several of the layers and buffer layers are applied using a pulsed atomic layer epitaxy (PALE) growth technique” “additional AlInGaN layers are deposited that together with 401, form a second buffer 421. These layers are shown as 402, 403, and 404 in FIGS. 3A, 3B, and 3C. These layers help to minimize overall strain of the epitaxial layer” “as illustrated in FIG. 4, the LED structure is added to the epilayer” “using a combination of the pulsed atomic layer epitaxy (PALE) technique and conventional metal-organic chemical vapor deposition (MOCVD)”] over a substrate to form a semiconductor layer surface;
(b) subjecting the semiconductor layer surface to an etching process [“A mesa-type LED may then be fabricated, the type shown in FIG. 4, using reactive ion etching (RIE) to access the bottom n+ layer”] for forming at least one mesa portion;
(c) depositing a metal stack [“Ti/Al/Ti/Au and Ni/Au are used as metal contacts for the n- and p-contacts, respectively, however, the n-metal contacts can be made of Ti, Al, Ni, Au, Mo, Ta or any combination of these metals. The second contact, the p+ layer contact, can be made of Pd, Ni, Ag, Au, ITO, NiO, PdO or any combination of the above-mentioned metals”] on the semiconductor layer surface;
(d) subjecting the semiconductor layer surface to a thermal annealing system [“These contacts could be annealed in air, a forming gas, nitrogen or any combination of such. In one embodiment, the anneal temperature cycle is a single step with a temperature range of 650.degree. C.-950.degree. C. In another embodiment, the annealing cycle may comprise multiple step annealing”] for ohmic contact annealing in forming gas (FG) comprising H2 and N2; and
(e) [see 112 rejection, Applicant is unable to comment on whether Hydrogen is present during the Nitrogen anneal ] subjecting the semiconductor layer surface to [“The second metal electrode on top of individual pillars are thickened by depositing additional titanium and gold layers. Annealing of said second electrode is done in nitrogen ambient” i.e. after first anneal in forming gas, the thickening of the metal electrode on top is performed, then the second anneal in Nitrogen is performed] the thermal annealing system for ohmic contact annealing in nitrogen (N2),
but does not specifically teach that the thermal annealing is rapid thermal annealing (RTA) and wherein step (d) comprises annealing in FG at a temperature in a range of 700- 900C for a duration in a range of 10-50 seconds or step (e) comprises annealing in N2 at a temperature in a range of 750-950°C for a duration in a range of 10-50 seconds.
See Derluyn teaches see paragraph 0158 “The defined ohmic contacts may then be subjected to one or more alloying steps, for example a rapid thermal annealing step for a duration of one minute in a reduced or inert atmosphere such as for example hydrogen or forming gas or nitrogen gas at a temperature for example between 800° C. and 900° C. A high electron mobility transistor 1 according to the present invention is obtained”.
Lee published in 2003 is provided as evidence of the known problems of forming gas, see “Thermal annealing in N2 gas ambient was usually employed to obtain low resistance Ohmic contacts. The main reason for using nitrogen gas as the annealing ambient instead of hydrogen containing gas, as commonly used by most III–V compounds, is to avoid the effect of hydrogen passivation of dopants in GaN” “Similar results were also observed in the Al/n-GaN Ohmic contacts annealed in Ar/4% H2 forming gas.19 The H2 content, however, may cause concerns in doping reduction because of hydrogen passivation. It is known that hydrogen passivation of p-type dopants in p-GaN would result in a large decrease of hole concentration.20,21 Whether annealing in forming gas ambient would lead to a similar reduction in electron concentration and increase of contact resistance of n-GaN needs to be answered. During the annealing process, H2 could diffuse into the bulk n-GaN to form neutral complexes with dopants at annealing temperature higher than 500 °C. On the other hand, the high temperature annealing process would also result in the dissociation of neutral dopant-H complexes”, thus the Examiner specifically notes that in 2003 it was already known to a person of ordinary skill in the art that adding hydrogen would cause passivation of dopants and equally, it was also known that the high temperature causes dissociation of the hydrogen, thus the annealing sequence of Adivarahan should be understood in the context of this existing knowledge by a person of ordinary skill in the art.
The Examiner notes that as stated in the rejection above, Adivarahan is clear that the second anneal is performed in nitrogen ambient and see evidence of Lee this has a known advantage, thus even though Adivarahan does not state the advantage, the fact that the inventor has recognized another advantage which would flow naturally from following the suggestion of the prior art cannot be the basis for patentability when the differences would otherwise be obvious. See Ex parte Obiaya, 227 USPQ 58, 60 (Bd. Pat. App. & Inter. 1985).
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Adivarahan to include that that the thermal annealing is rapid thermal annealing (RTA) .
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that rapid thermal annealing is known to give good results in annealing semiconductor devices with providing heat quickly to avoid bad effects of long device exposure to heat.
Adivarahan and Derluyn as combined teaches [see Adivarahan paragraph 0055 “the anneal temperature cycle is a single step with a temperature range of 650.degree. C.-950.degree. C”] but does not specifically teach wherein step (d) comprises annealing in FG at a temperature in a range of 700- 900C for a duration in a range of 10-50 seconds or step (e) comprises annealing in N2 at a temperature in a range of 750-950°C for a duration in a range of 10-50 seconds.
See rejection of claim 1 above “These contacts could be annealed in air, a forming gas, nitrogen or any combination of such. In one embodiment, the anneal temperature cycle is a single step with a temperature range of 650.degree. C.-950.degree. C. In another embodiment, the annealing cycle may comprise multiple step annealing”.
See rejection of claim 1 above Derluyn teaches see paragraph 0158 “The defined ohmic contacts may then be subjected to one or more alloying steps, for example a rapid thermal annealing step for a duration of one minute in a reduced or inert atmosphere such as for example hydrogen or forming gas or nitrogen gas at a temperature for example between 800° C. and 900° C. A high electron mobility transistor 1 according to the present invention is obtained”.
However see Adivarahan paragraph 0055 “the anneal temperature cycle is a single step with a temperature range of 650.degree. C.-950.degree. C”, see evidence reference Lee has anneal durations.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “wherein step (d) comprises annealing in FG at a temperature in a range of 700- 900C for a duration in a range of 10-50 seconds or step (e) comprises annealing in N2 at a temperature in a range of 750-950°C for a duration in a range of 10-50 seconds” , since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233
In regard to claim 3 Adivarahan and Derluyn as combined teaches wherein the epitaxial layer is deposited [see Adivarahan paragraph 0044 “using a combination of the pulsed atomic layer epitaxy (PALE) technique and conventional metal-organic chemical vapor deposition (MOCVD)”] over the substrate using metal organic chemical vapor deposition (MOCVD).
In regard to claim 6 [see 112 rejection] Adivarahan and Derluyn as combined teaches wherein the metal stack [see Adivarahan “Ti/Al/Ti/Au and Ni/Au are used as metal contacts for the n- and p-contacts, respectively, however, the n-metal contacts can be made of Ti, Al, Ni, Au, Mo, Ta or any combination of these metals. The second contact, the p+ layer contact, can be made of Pd, Ni, Ag, Au, ITO, NiO, PdO or any combination of the above-mentioned metals” “The second metal electrode on top of individual pillars are thickened by depositing additional titanium and gold layers”] comprises titanium (Ti), aluminum (Al), nickel (Ni), gold (Au), or a combination of any two or more thereof.
In regard to claim 13 Adivarahan and Derluyn as combined teaches [see Adivarahan does not suggest passivation process in the anneal, see use of Nitrogen ambient] wherein no passivation process is applied to the semiconductor device.
Claim(s) 2, 8-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Adivarahan and Derluyn as combined and further in view of Then et al. (US 20220102344 A1) hereafter referred to as Then.
In regard to claim 2 Adivarahan and Derluyn as combined teaches wherein the substrate [see paragraph 0068 “Although preferably made of sapphire, the substrate may be made of silicon carbide, GaN, AlN, AlGaN, InN, InGaN, AlInGaN, Silicon ..”] comprises silicon, and further comprising: (f) subjecting the semiconductor layer surface to an oxygen plasma [“In another embodiment, the annealing can be done in air, oxygen ambient also”, see the oxygen is at high temperature ] treatment;
but does not teach and (g) depositing a T-shaped metal gate on the semiconductor layer surface.
See Then teaches integration, see paragraph 0214 “building GaN 3D IC solutions in consideration of build-to-demand cost and speed-to-market. Devices of different functionalities (e.g., where each functionality is defined and confined to its functional layer) are provided and built with different process technologies as well as design rules and are integrated using 3D stacking and bonding techniques. Such process technologies can be very dissimilar. Exemplary functional layers may include, but are not limited to, (1) red III-V (InGaAsP) micro-LED or laser technology, (2) GaN blue and green micro-LED or laser technologies, (3) 3D TFT (thin film transistor) technology, (4) GaN transistor technology with N-channel GaN HEMT, MOSHEMT and MOSFET technologies as well as GaN P-channel HEMT, MOSHEMT and MOSFET technologies” see the GaN HEMT in Fig. 1 see paragraph 0087 “two-dimensional electron gas (2DEG) effect or layer 150 in the top surface of GaN layer 102 as illustrated in FIG. 1” “gate electrode 112, such as a metal gate electrode” “gate structure 108 has a “T” shape as illustrated in FIG. 1” “Gate structure 108 may include an upper gate portion 113 and a lower gate portion 115”, see the T-shape “upper gate portion 113 extends a distance (d.sub.UG) above drain region 116”, see the mesa shape in Figs. 4-8.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Adivarahan to include transistors such as HEMTs i.e. to modify Adivarahan to include and (g) depositing a T-shaped metal gate on the semiconductor layer surface.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to integrate more functionality on the semiconductor substrate by including devices such as transistor.
In regard to claim 8 Adivarahan, Derluyn and Then as combined teaches wherein the T-shaped metal gate [see metals used by Adivarahan] comprises Ni, Au, or a combination thereof.
In regard to claim 9 Adivarahan, Derluyn and Then as combined teaches wherein step (e) occurs [see claim 1] after step (d) and at least step (d) occurs [see claim 1 see after first anneal in forming gas, the thickening of the metal electrode on top is performed, then the second anneal in Nitrogen is performed] before step (g), and FG comprises [the Examiner notes this is in a standard formulation range for forming gas] 5% H2 and 95% N2.
In regard to claim 10 Adivarahan, Derluyn and Then as combined teaches [see combination Then] wherein the semiconductor device comprises a high electron mobility transistor (HEMT).
In regard to claim 11 Adivarahan, Derluyn and Then as combined teaches [see Adivarahan paragraph 0068 “Although preferably made of sapphire, the substrate may be made of silicon carbide, GaN, AlN, AlGaN, InN, InGaN, AlInGaN, Silicon ..” see Then paragraph 0096 “A gallium nitride (GaN) layer 302 may be disposed above a substrate 304, such as but not limited to a monocrystalline silicon substrate, a silicon carbide substrate, and aluminum oxide (Al.sub.2O.sub.3) substrate. As shown in FIG. 3A, a polarization layer 306, such as but not limited to aluminum gallium nitride (AlGaN), aluminum indium gallium nitride (AlInGaN) and indium gallium nitride (InGaN) may be disposed on GaN layer 302” “sufficient to create a 2DEG layer 305”] an indium aluminum nitride/qallium nitride high electron mobility transistor (InAIN/GaN HEMT) on a silicon (Si) substrate (InAIN/GaN HEMT on Si semiconductor device),
but does not state wherein the semiconductor device comprises a 50-nm gate length.
However transistor current is inversely proportional to gate length, and thus gate length is selected based on lithography constraints, see Then paragraph 0089 dimensions, “In an embodiment, transistor 100 has a gate width (Gw) between 0.010 microns-100 microns”, thus It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “wherein the semiconductor device comprises a 50-nm gate length”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Adivarahan et al. (US 20100264401 A1) hereafter referred to as Adivarahan in view of Then et al. (US 20220102344 A1) hereafter referred to as Then. Lee et al. (see PTO-892) is provided as evidence.
In regard to claim 14 Adivarahan teaches a [see Fig. 4 see paragraph 0039, 0055 “array of ultraviolet light-emitting structures, 12”] semiconductor device comprising:
a semiconductor layer surface [“Several of the layers and buffer layers are applied using a pulsed atomic layer epitaxy (PALE) growth technique” “additional AlInGaN layers are deposited that together with 401, form a second buffer 421. These layers are shown as 402, 403, and 404 in FIGS. 3A, 3B, and 3C. These layers help to minimize overall strain of the epitaxial layer” “as illustrated in FIG. 4, the LED structure is added to the epilayer” “using a combination of the pulsed atomic layer epitaxy (PALE) technique and conventional metal-organic chemical vapor deposition (MOCVD)”] including an epitaxial layer over a substrate [see paragraph 0068 “Although preferably made of sapphire, the substrate may be made of silicon carbide, GaN, AlN, AlGaN, InN, InGaN, AlInGaN, Silicon ..”] comprising silicon;
at least one mesa portion [“A mesa-type LED may then be fabricated, the type shown in FIG. 4, using reactive ion etching (RIE) to access the bottom n+ layer”] formed on the semiconductor layer surface;
a metal stack [“Ti/Al/Ti/Au and Ni/Au are used as metal contacts for the n- and p-contacts, respectively, however, the n-metal contacts can be made of Ti, Al, Ni, Au, Mo, Ta or any combination of these metals. The second contact, the p+ layer contact, can be made of Pd, Ni, Ag, Au, ITO, NiO, PdO or any combination of the above-mentioned metals”] on the semiconductor layer surface, the metal stack being sequentially annealed [“These contacts could be annealed in air, a forming gas, nitrogen or any combination of such. In one embodiment, the anneal temperature cycle is a single step with a temperature range of 650.degree. C.-950.degree. C. In another embodiment, the annealing cycle may comprise multiple step annealing” “The second metal electrode on top of individual pillars are thickened by depositing additional titanium and gold layers. Annealing of said second electrode is done in nitrogen ambient”] in FG and then in N2 [after first anneal in forming gas, the thickening of the metal electrode on top is performed, then the second anneal in Nitrogen is performed], each for a predetermined [this is true, see that Adivarahan ends the annealing steps and does not suggest in any way that the durations are varied] duration; and
but does not teach a T-shaped metal gate on the semiconductor layer surface.
See Then teaches integration, see paragraph 0214 “building GaN 3D IC solutions in consideration of build-to-demand cost and speed-to-market. Devices of different functionalities (e.g., where each functionality is defined and confined to its functional layer) are provided and built with different process technologies as well as design rules and are integrated using 3D stacking and bonding techniques. Such process technologies can be very dissimilar. Exemplary functional layers may include, but are not limited to, (1) red III-V (InGaAsP) micro-LED or laser technology, (2) GaN blue and green micro-LED or laser technologies, (3) 3D TFT (thin film transistor) technology, (4) GaN transistor technology with N-channel GaN HEMT, MOSHEMT and MOSFET technologies as well as GaN P-channel HEMT, MOSHEMT and MOSFET technologies” see the GaN HEMT in Fig. 1 see paragraph 0087 “two-dimensional electron gas (2DEG) effect or layer 150 in the top surface of GaN layer 102 as illustrated in FIG. 1” “gate electrode 112, such as a metal gate electrode” “gate structure 108 has a “T” shape as illustrated in FIG. 1” “Gate structure 108 may include an upper gate portion 113 and a lower gate portion 115”, see the T-shape “upper gate portion 113 extends a distance (d.sub.UG) above drain region 116”, see the mesa shape in Figs. 4-8.
Lee published in 2003 is provided as evidence of the known problems of forming gas, see “Thermal annealing in N2 gas ambient was usually employed to obtain low resistance Ohmic contacts. The main reason for using nitrogen gas as the annealing ambient instead of hydrogen containing gas, as commonly used by most III–V compounds, is to avoid the effect of hydrogen passivation of dopants in GaN” “Similar results were also observed in the Al/n-GaN Ohmic contacts annealed in Ar/4% H2 forming gas.19 The H2 content, however, may cause concerns in doping reduction because of hydrogen passivation. It is known that hydrogen passivation of p-type dopants in p-GaN would result in a large decrease of hole concentration.20,21 Whether annealing in forming gas ambient would lead to a similar reduction in electron concentration and increase of contact resistance of n-GaN needs to be answered. During the annealing process, H2 could diffuse into the bulk n-GaN to form neutral complexes with dopants at annealing temperature higher than 500 °C. On the other hand, the high temperature annealing process would also result in the dissociation of neutral dopant-H complexes”, thus the Examiner specifically notes that in 2003 it was already known to a person of ordinary skill in the art that adding hydrogen would cause passivation of dopants and equally, it was also known that the high temperature causes dissociation of the hydrogen, thus the annealing sequence of Adivarahan should be understood in the context of this existing knowledge by a person of ordinary skill in the art.
The Examiner notes that as stated in the rejection above, Adivarahan is clear that the second anneal is performed in nitrogen ambient and see evidence of Lee this has a known advantage, thus even though Adivarahan does not state the advantage, the fact that the inventor has recognized another advantage which would flow naturally from following the suggestion of the prior art cannot be the basis for patentability when the differences would otherwise be obvious. See Ex parte Obiaya, 227 USPQ 58, 60 (Bd. Pat. App. & Inter. 1985).
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Adivarahan to include transistors such as HEMTs i.e. to modify Adivarahan to include a T-shaped metal gate on the semiconductor layer surface.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to integrate more functionality on the semiconductor substrate by including devices such as transistor.
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Adivarahan et al. (US 20100264401 A1) hereafter referred to as Adivarahan in view of Derluyn et al. (US 20200176593 A1) hereafter referred to as Derluyn. Lee et al. (see PTO-892) is provided as evidence.
In regard to claim 20 Adivarahan teaches a method [see Fig. 4 see paragraph 0039, 0055 “array of ultraviolet light-emitting structures, 12”] of subjecting a semiconductor layer [“Several of the layers and buffer layers are applied using a pulsed atomic layer epitaxy (PALE) growth technique” “additional AlInGaN layers are deposited that together with 401, form a second buffer 421. These layers are shown as 402, 403, and 404 in FIGS. 3A, 3B, and 3C. These layers help to minimize overall strain of the epitaxial layer” “as illustrated in FIG. 4, the LED structure is added to the epilayer” “using a combination of the pulsed atomic layer epitaxy (PALE) technique and conventional metal-organic chemical vapor deposition (MOCVD)”] surface to [“Ti/Al/Ti/Au and Ni/Au are used as metal contacts for the n- and p-contacts, respectively, however, the n-metal contacts can be made of Ti, Al, Ni, Au, Mo, Ta or any combination of these metals. The second contact, the p+ layer contact, can be made of Pd, Ni, Ag, Au, ITO, NiO, PdO or any combination of the above-mentioned metals”] post- metallization annealing, the method comprising:
(a) subjecting the semiconductor layer surface to a first anneal phase [“These contacts could be annealed in air, a forming gas, nitrogen or any combination of such. In one embodiment, the anneal temperature cycle is a single step with a temperature range of 650.degree. C.-950.degree. C. In another embodiment, the annealing cycle may comprise multiple step annealing”], the first anneal phase comprising subjecting the semiconductor layer surface to annealing for ohmic contact annealing in forming gas (FG) comprising H2 and N2; and
(b) subjecting the semiconductor layer surface to a second anneal phase [“The second metal electrode on top of individual pillars are thickened by depositing additional titanium and gold layers. Annealing of said second electrode is done in nitrogen ambient”], the second anneal phase comprising subjecting the semiconductor layer surface to the annealing for ohmic contact annealing in N2;
wherein step (b) occurs after [after first anneal in forming gas, the thickening of the metal electrode on top is performed, then the second anneal in Nitrogen is performed] step (a) ,
but does not specifically teach that the annealing is an RTA system.
See Derluyn teaches see paragraph 0158 “The defined ohmic contacts may then be subjected to one or more alloying steps, for example a rapid thermal annealing step for a duration of one minute in a reduced or inert atmosphere such as for example hydrogen or forming gas or nitrogen gas at a temperature for example between 800° C. and 900° C. A high electron mobility transistor 1 according to the present invention is obtained”.
Lee published in 2003 is provided as evidence of the known problems of forming gas, see “Thermal annealing in N2 gas ambient was usually employed to obtain low resistance Ohmic contacts. The main reason for using nitrogen gas as the annealing ambient instead of hydrogen containing gas, as commonly used by most III–V compounds, is to avoid the effect of hydrogen passivation of dopants in GaN” “Similar results were also observed in the Al/n-GaN Ohmic contacts annealed in Ar/4% H2 forming gas.19 The H2 content, however, may cause concerns in doping reduction because of hydrogen passivation. It is known that hydrogen passivation of p-type dopants in p-GaN would result in a large decrease of hole concentration.20,21 Whether annealing in forming gas ambient would lead to a similar reduction in electron concentration and increase of contact resistance of n-GaN needs to be answered. During the annealing process, H2 could diffuse into the bulk n-GaN to form neutral complexes with dopants at annealing temperature higher than 500 °C. On the other hand, the high temperature annealing process would also result in the dissociation of neutral dopant-H complexes”, thus the Examiner specifically notes that in 2003 it was already known to a person of ordinary skill in the art that adding hydrogen would cause passivation of dopants and equally, it was also known that the high temperature causes dissociation of the hydrogen, thus the annealing sequence of Adivarahan should be understood in the context of this existing knowledge by a person of ordinary skill in the art.
The Examiner notes that as stated in the rejection above, Adivarahan is clear that the second anneal is performed in nitrogen ambient and see evidence of Lee this has a known advantage, thus even though Adivarahan does not state the advantage, the fact that the inventor has recognized another advantage which would flow naturally from following the suggestion of the prior art cannot be the basis for patentability when the differences would otherwise be obvious. See Ex parte Obiaya, 227 USPQ 58, 60 (Bd. Pat. App. & Inter. 1985).
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Adivarahan to include that the thermal annealing is rapid thermal annealing (RTA).
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that rapid thermal annealing is known to give good results in annealing semiconductor devices with providing heat quickly to avoid bad effects of long device exposure to heat.
[this was the old claim 21] Adivarahan and Derluyn as combined does not specifically teach further comprising: (c) subjecting the semiconductor layer surface to a pre-anneal phase, the pre-anneal phase comprising heating to a first temperature for a first predetermined duration, wherein the first temperature is between 15° C and 35° C or the first predetermined duration is between 30 to 90 seconds; (d) subjecting the semiconductor layer surface to a post-anneal phase, the post-anneal phase comprising heating to a second temperature.
However see Adivarahan “the annealing cycle may comprise multiple step annealing”. The Examiner notes that room temperature is about 25° C and that at the start of an anneal, the anneal chamber is not hot yet.
See Derluyn teaches see paragraph 0158 “The defined ohmic contacts may then be subjected to one or more alloying steps, for example a rapid thermal annealing step for a duration of one minute in a reduced or inert atmosphere such as for example hydrogen or forming gas or nitrogen gas at a temperature for example between 800° C. and 900° C. A high electron mobility transistor 1 according to the present invention is obtained”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Adivarahan to include further comprising: (c) subjecting the semiconductor layer surface to a pre-anneal phase, the pre-anneal phase comprising heating to a first temperature for a first predetermined duration, wherein the first temperature is between 15° C and 35° C or the first predetermined duration is between 30 to 90 seconds; (d) subjecting the semiconductor layer surface to a post-anneal phase, the post-anneal phase comprising heating to a second temperature.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that initially the anneal chamber is at room temperature and that rapid thermal annealing is known to give good results in annealing semiconductor devices with providing heat quickly to avoid bad effects of long device exposure to heat and that Adivarahan teaches “the annealing cycle may comprise multiple step annealing” to obtain all the anneal results desired such as including cool down of the wafer.
In regard to claim 23 Adivarahan and Derluyn as combined teaches wherein FG comprises [the Examiner notes this is in a standard formulation range for forming gas] 5% of H2 and 95% of N2.
In regard to claim 24 Adivarahan and Derluyn as combined teaches [see combination, this is simply a cool down phase, room temperature is about 25° C] wherein the second temperature is between 15° C and 35° C.
In regard to claim 25 Adivarahan and Derluyn [see 112 rejection for claim 25, addition of hydrogen to N2] as combined does not state wherein step (b) comprises annealing the semiconductor layer surface between 700° C and 900° C in FG.
However see Adivarahan teaches annealing in forming gas or nitrogen, see “In one embodiment, the anneal temperature cycle is a single step with a temperature range of 650.degree. C.-950.degree. C”, see Derluyn teaches see paragraph 0158 “The defined ohmic contacts may then be subjected to one or more alloying steps, for example a rapid thermal annealing step for a duration of one minute in a reduced or inert atmosphere such as for example hydrogen or forming gas or nitrogen gas at a temperature for example between 800° C. and 900° C. ”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Adivarahan to include wherein step (b) comprises annealing the semiconductor layer surface between 700° C and 900° C in FG.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that these are temperature ranges and gases taught by both Adivarahan and Derluyn known to give good results for anneal.
In regard to claim 26 Adivarahan and Derluyn as combined does not state wherein step (b) comprises annealing the semiconductor layer surface in FG for between 10 and 50 seconds.
See Derluyn teaches see paragraph 0158 “The defined ohmic contacts may then be subjected to one or more alloying steps, for example a rapid thermal annealing step for a duration of one minute in a reduced or inert atmosphere such as for example hydrogen or forming gas or nitrogen gas at a temperature for example between 800° C. and 900° C. ”.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “wherein step (b) comprises annealing the semiconductor layer surface in FG for between 10 and 50 seconds ”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233
In regard to claim 27 Adivarahan and Derluyn as combined does not state wherein step (c) comprises annealing the semiconductor layer surface between 750° C and 950° C in N2.
However see Adivarahan teaches “These contacts could be annealed in air, a forming gas, nitrogen or any combination of such. In one embodiment, the anneal temperature cycle is a single step with a temperature range of 650.degree. C.-950.degree. C. In another embodiment, the annealing cycle may comprise multiple step annealing” “The second metal electrode on top of individual pillars are thickened by depositing additional titanium and gold layers. Annealing of said second electrode is done in nitrogen ambient”, it is noted that adding anneal steps gives more annealing, see relevant case law it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co.v. Bemis Co., 193 USPQ 8;
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Adivarahan to include wherein step (c) comprises annealing the semiconductor layer surface between 750° C and 950° C in N2.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that adding anneal steps gives more annealing to give better anneal.
In regard to claim 28 Adivarahan and Derluyn as combined does not state wherein step (c) comprises annealing the semiconductor layer surface in N2 for between 10 and 50 seconds.
See combination see Derluyn teaches see paragraph 0158 “The defined ohmic contacts may then be subjected to one or more alloying steps, for example a rapid thermal annealing step for a duration of one minute in a reduced or inert atmosphere such as for example hydrogen or forming gas or nitrogen gas at a temperature for example between 800° C. and 900° C. ”.
See Adivarahan teaches “These contacts could be annealed in air, a forming gas, nitrogen or any combination of such. In one embodiment, the anneal temperature cycle is a single step with a temperature range of 650.degree. C.-950.degree. C. In another embodiment, the annealing cycle may comprise multiple step annealing”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Adivarahan to include wherein step (c) comprises annealing the semiconductor layer surface in N2 for between 10 and 50 seconds.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that adding anneal steps gives more annealing to give better anneal.
In regard to claim 29 Adivarahan and Derluyn as combined does not state wherein step (d) comprises annealing the semiconductor layer surface in FG.
See Adivarahan teaches “These contacts could be annealed in air, a forming gas, nitrogen or any combination of such. In one embodiment, the anneal temperature cycle is a single step with a temperature range of 650.degree. C.-950.degree. C. In another embodiment, the annealing cycle may comprise multiple step annealing”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Adivarahan to include wherein step (d) comprises annealing the semiconductor layer surface in FG.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that adding anneal steps gives more annealing to give better anneal.
Response to Arguments
Applicant's arguments filed 9/4/2025 have been fully considered but they are not persuasive.
On page 3, 4 the Applicant argues “On page 4-7 of the Office Action, the Office contends that Adivarahan allegedly teaches all features of claim 1, except for the feature of step (d) subjecting the semiconductor layer surface to a rapid thermal annealing (RTA) system. Thus, the Office relies upon 1158 of Derluyn to disclose the missing feature. Further, the Examiner cites Lee as evidence of known problems of forming gas (FG), such that it would have been known to one skilled in the art that the "high temperature causes dissociation of the hydrogen," such that one skilled in the art would have modified the method described in Adivarahan to include a "second anneal [step]... performed in nitrogen ambient," as allegedly taught in Derluyn and the advantages thereof would have been allegedly obvious based on Lee. The foregoing rejection is moot as to amended claim 1 and dependent claims thereof. As amended, claim 1 now requires features previously recited in dependent claim 7, including "wherein step (d) comprises annealing in FG at a temperature in a range of 700-900°C for a duration in a range of 10-50 seconds; and step
(e) comprises annealing in N2 at a temperature in a range of 750-950°C for a duration in a range of 10-50 seconds." See e.g. page 8, line 1 to page 9, line 19 of the specification as filed as well as FIGS. 4 and 15, illustrating features of embodiments of the invention. Further, the rejection based on Adivarahan, Derluyn, and Lee should not be maintained against amended claim 1 because the disclosure therein does not disclose all features of the claimed method. For example, in rejecting the pending claims, the Office asserts that in general, the concept of a two-step annealing process (and sequentially in forming gas (FG) and N2) is taught by the prior art. However the Office only points to the following mere teaching of Adivarahan: "anneal temperature cycle is a single step with a temperature range of 650 °C - 950 °C" as a basis for disclosure of the claimed respective annealing temperature ranges and duration ranges with respect to steps (d) and (e), as now recited in amended claim 1. This cited disclosure in Adivarahan is silent with respect to at least the respective annealing duration range(s) and the remaining applied references do not cure this deficiency of Adivarahan. Thus, the applied references, individually or in combination with each other, do not disclose all features of the claimed method, as now recited by amended claim 1. Accordingly, Applicant respectfully requests that this rejection of claim 1 and dependent claims thereof be withdrawn”.
The Examiner responds that the rejection of claim 1 does teach a plurality of anneal steps, see Adivarahan “These contacts could be annealed in air, a forming gas, nitrogen or any combination of such. In one embodiment, the anneal temperature cycle is a single step with a temperature range of 650.degree. C.-950.degree. C. In another embodiment, the annealing cycle may comprise multiple step annealing” and “The second metal electrode on top of individual pillars are thickened by depositing additional titanium and gold layers. Annealing of said second electrode is done in nitrogen ambient” i.e. after first anneal in forming gas, the thickening of the metal electrode on top is performed, then the second anneal in Nitrogen is performed. In addition, the Applicants invention of merely adding a plurality of steps is not novel because Adivarahan himself states that the two anneals can comprise multiple steps and the Applicant is trying to state that temperature rise and fall are novel but this is just start and end of the cycle i.e. not novel.
On page 4 the Applicant argues “Still further, Applicant respectfully submits that the cited references are silent as to performing the first annealing step (d) prior to step (g) of depositing a T-shaped metal gate on the semiconductor layer surface, as recited in dependent claim 9. Thus, in addition to being allowable for at least the reasons discussed above with respect to claim 1, from which claim 9 ultimately depends, claim 9 recites additional distinguishing features which are not disclosed by the applied references”
The Examiner responds that the rejection of claim 1 does teach a plurality of anneal steps, see Adivarahan “These contacts could be annealed in air, a forming gas, nitrogen or any combination of such. In one embodiment, the anneal temperature cycle is a single step with a temperature range of 650.degree. C.-950.degree. C. In another embodiment, the annealing cycle may comprise multiple step annealing” and “The second metal electrode on top of individual pillars are thickened by depositing additional titanium and gold layers. Annealing of said second electrode is done in nitrogen ambient” i.e. after first anneal in forming gas, the thickening of the metal electrode on top is performed, then the second anneal in Nitrogen is performed.
On page 5 the Applicant argues “In rejecting claim 21, which describes a step (c) of subjecting the semiconductor layer surface to a pre-anneal phase and a step (d) of subjecting the semiconductor layer surface to a post-anneal phase, the Office merely points to the following teaching of Adivarahan: "the annealing cycle may comprise multiple step annealing." Amended claim 21 now requires, inter alia, "wherein the first temperature is between 15° C and 350 C and the first predetermined duration is between 30 to 90 seconds." Applicant respectfully submits that the cited references are silent as to the specific annealing temperature ranges and annealing duration ranges as now recited in amended claim 21. Accordingly, Applicant respectfully requests that this rejection of claim 21 and dependent claims thereof be withdrawn.”
The Examiner responds that the rejection of claim 1 does teach a plurality of anneal steps, see Adivarahan “These contacts could be annealed in air, a forming gas, nitrogen or any combination of such. In one embodiment, the anneal temperature cycle is a single step with a temperature range of 650.degree. C.-950.degree. C. In another embodiment, the annealing cycle may comprise multiple step annealing” and “The second metal electrode on top of individual pillars are thickened by depositing additional titanium and gold layers. Annealing of said second electrode is done in nitrogen ambient” i.e. after first anneal in forming gas, the thickening of the metal electrode on top is performed, then the second anneal in Nitrogen is performed. In addition, the Applicants invention of merely adding a plurality of steps is not novel because Adivarahan himself states that the two anneals can comprise multiple steps and the Applicant is trying to state that temperature rise and fall are novel but this is just start and end of the cycle i.e. not novel.
On page 5 the Applicant argues “Still further, new claim 23 include the features of claim 22, from which it ultimately depends. Accordingly, Applicant respectfully submits that claim 23 is allowable for at least the reasons discussed above with respect to claim 22, which has been converted into independent form. In addition, claim 23 recites distinguishing features including "wherein FG comprises 5% of H2 and 95% of N2."
The Examiner responds that see the 112 rejection for all the claims 1-29.
On page 5 the Applicant argues “ New claims 24-29 include the features of claim 21, from which they ultimately depend. Accordingly, Applicant respectfully submits that claims 24-29 are allowable for at least the reasons discussed above with respect to claim 21. Moreover, claim 24 recites distinguishing features including "wherein the second temperature is between 15° C and 350 C." Claim 25 recites distinguishing features including "wherein step (b) comprises annealing the semiconductor layer surface between 700° C and 900° C in FG." Claim 26 recites distinguishing features including "wherein step (b) comprises annealing the semiconductor layer surface in FG for between 10 and 50 seconds." Claim 27 recites distinguishing features including "wherein step (c) comprises annealing the semiconductor layer surface between 750° C and 950° C in N2." Claim 28 recites distinguishing features including "wherein step (c) comprises annealing the semiconductor layer surface in N2 for between 10 and 50 seconds." Claim 29 recites distinguishing features includi