DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claims 1-3, 5, and 7-10 are pending.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-3, 5 and 7-12 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Claim 1 recite(s) “generate a diagnosis program for diagnosing a processor” and “a calculation process defined in a neural network”, “a determination processing unit configured to, for each predetermined diagnosis target node among a plurality of nodes in the neural network, calculate an expected value expected as a calculation result of a node calculation process corresponding to the predetermined diagnosis target node”, “a generation processing unit configured to, for each diagnosis target node, generate as the diagnosis program a program for comparing the calculation result of the node calculation process corresponding to the diagnosis target node”, “an analysis processing unit configured to analyze, for each of the plurality of nodes, an influence degree of a hardware failure of the processor on the calculation result of the node calculation process, wherein the influence degree is an architectural vulnerability factor defined as an error ratio of an error bit to all bits of the calculation result, and determine the diagnosis target node from the plurality of nodes based on the influence degree”, “a specification processing unit configured to specify a correspondence relation between the diagnosis target node and a calculation core of the plurality of configuration cores configured to execute the node calculation process corresponding to the diagnosis target node; and an execution processing unit configured to specify, based on the correspondence relation, parallelizable processes that are the node calculation processes executable in parallel using the plurality of calculation cores; wherein the generation processing unit is configured to generate the diagnosis program so that the parallelizable processes are executed in parallel by the processor;” and “a diagnosis process, which is based on the diagnosis program, based on neural network calculation and diagnosis sequence data; and wherein the diagnosis process of the processor is executed without considering coupling between the nodes in the neural network, and the diagnosis process determines hardware failures in the diagnosis target node of the processor” which is considered to be directed to mental processes and/or mathematical concepts.
This judicial exception is not integrated into a practical application because “a computer”, “a processor, the processor being configured to execute”, “calculation processing is executed by the processor”, “a neural network using a plurality of calculation cores”, “execute the node calculation process corresponding to the diagnosis target node;”, “the parallelizable processes are executed in parallel by the processor;” and “wherein the computer controls the processor to execute the calculation process and a diagnosis process” are generically recited computer elements that do not add a meaningful limitation to the abstract idea because they amount to simply implementing the abstract idea on a computer. Further, “which is obtained when the node calculation process is executed using a predetermined input value” and “which is obtained when the node calculation processing is executed by the processor using the input value, with the expected value” are considered to be data gathering and transferring steps required to use the correlation that do not add a meaningful limitation to the method as they are insignificant extra-solution activity.
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because “a computer”, “a processor being configured to execute”, “calculation processing is executed by the processor”, “a neural network using a plurality of calculation cores”, “execute the node calculation process corresponding to the diagnosis target node;”, “the parallelizable processes are executed in parallel by the processor;” and “wherein the computer controls the processor to execute the calculation process and a diagnosis process” are considered to be well-understood, routine, conventional computer functions as recognized by the court decisions listed in MPEP § 2106.05(d). Further, “which is obtained when the node calculation process is executed using a predetermined input value” and “which is obtained when the node calculation processing is executed by the processor using the input value, with the expected value” are considered to be well-understood, routine, conventional computer functions as recognized by the court decisions listed in MPEP § 2106.05(d)(i).
In claim 8 the elements of “a controller including the processor and a control processor separate from the processor, wherein the control processor is configured to cause the processor to execute the calculation process and a diagnosis process that is based on the diagnosis program” are not integrated into a practical application or include additional elements that are sufficient to amount to significantly more than the judicial exception as they are considered to be generically recited computer elements that do not add a meaningful limitation to the abstract idea because they amount to simply implementing the abstract idea on a computer and well-understood, routine, conventional computer functions as recognized by the court decisions listed in MPEP § 2106.05(d).
In claim 9 the elements of “predict an idle time from end of the calculation process to start of a next calculation process, and when the idle time is equal to or longer than a predetermined time, cause the processor to execute the diagnosis process” are considered to further describe the abstract ideas above. The elements of “wherein the control processor is configured to monitor an operation status of the processor” are not integrated into a practical application or include additional elements that are sufficient to amount to significantly more than the judicial exception as they are considered to be are considered to be data gathering and transferring steps required to use the correlation that do not add a meaningful limitation to the method as they are insignificant extra-solution activity and are considered to be well-understood, routine, conventional computer functions as recognized by the court decisions listed in MPEP § 2106.05(d)(i)
Claim 10 recites “generate a diagnosis program for diagnosing a processor, the processor being configured to execute a calculation process defined in a neural network”, “for each predetermined diagnosis target node among a plurality of nodes in the neural network, calculating an expected value expected as a calculation result of a node calculation process corresponding to the predetermined diagnosis target node, which is obtained when the node calculation process is executed using a predetermined input value; and for each diagnosis target node, generating as the diagnosis program a program for comparing the calculation result of the node calculation process corresponding to the diagnosis target node, which is obtained when the node calculation process is executed by the processor using the input value, with the expected value”, “for each of the plurality of nodes, analyzing an influence degree of a hardware failure of the processor on the calculation result of the node calculation process, wherein the influence degree is an architectural vulnerability factor defined as an error ratio of an error bit to all bits of the calculation result, and determining the diagnosis target node from the plurality of nodes based on the influence degree”, “specifying a correspondence relation between the diagnosis target node and a calculation core of the plurality of configuration cores configured to execute the node calculation process corresponding to the diagnosis target node; and specifying, based on the correspondence relation, parallelizable processes that are the node calculation processes executable in parallel using the plurality of calculation cores; wherein the computer is configured to generate the diagnosis program so that the parallelizable processes are executed in parallel by the processor;” “execute the node calculation process corresponding to the diagnosis target node;”, “the parallelizable processes are executed in parallel by the processor;” and “a diagnosis process, which is based on the diagnosis program, based on neural network calculation and diagnosis sequence data; and wherein the diagnosis process of the processor is executed without considering coupling between the nodes in the neural network, and the diagnosis process determines hardware failures in the diagnosis target node of the processor” which is considered to be directed to mental processes and/or mathematical concepts.
This judicial exception is not integrated into a practical application because “a computer configured to”, “a neural network using a plurality of calculation cores”, “execute the node calculation process corresponding to the diagnosis target node;”, “the parallelizable processes are executed in parallel by the processor;” and “wherein the computer controls the processor to execute the calculation process and a diagnosis process” is a generically recited computer element that does not add a meaningful limitation to the abstract idea because it amounts to simply implementing the abstract idea on a computer.
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because “a computer configured to”, “a neural network using a plurality of calculation cores”, and “wherein the computer controls the processor to execute the calculation process and a diagnosis process” is considered to be a well-understood, routine, conventional computer function as recognized by the court decisions listed in MPEP § 2106.05(d).
Claims 2-3, 5, 7 and 11-12 are considered to further describe the abstract ideas above.
Examiner Note with regards to Prior Art of Record
Claims 1-3, 5, and 7-12 are distinguished over the prior art of record as previously indicated.
Response to Arguments
Applicant's arguments filed 12/02/2025 have been fully considered but they are not persuasive. regarding applicant’s 101 arguments on pages 2-4, the examiner respectfully disagrees. Foremost, the examiner does not believe that the situation in SRI international applies to the current claims. While applicant asserts an improvement in that “the diagnostic load on the computer is reduced and the speed of analyzing the neural network is increased” based on the cited specification, notably, “a diagnosis load such as a diagnosis time can be reduced” and “diagnosis of the NN calculation processor 22 can be executed at a higher speed” (emphasis added). Looking at the claims and specification to support said improvement, the additional steps are recited at a high level of generality and the mere assertion of an improvement or a possible improvement is not enough to be considered integrated into a practical application or significantly more, per MPEP 2106.04(d)(1) “if the specification explicitly sets forth an improvement but in a conclusory manner (i.e., a bare assertion of an improvement without the detail necessary to be apparent to a person of ordinary skill in the art), the examiner should not determine the claim improves technology. Second, if the specification sets forth an improvement in technology, the claim must be evaluated to ensure that the claim itself reflects the disclosed improvement. That is, the claim includes the components or steps of the invention that provide the improvement described in the specification”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20150317240 A1, TESTING IMPLEMENTATION PARAMETERS OF A COMPUTER PROGRAM IN A DISTRIBUTED ENVIRONMENT; US 20070198880 A1, Semiconductor Integrated Circuit And Testing Method Thereof.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON J BECKER whose telephone number is (571)431-0689. The examiner can normally be reached M-F 9:30-5:30.
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/B.J.B/Examiner, Art Unit 2857
/SHELBY A TURNER/Supervisory Patent Examiner, Art Unit 2857