DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is FINAL and is in response to the amendment filed March 2nd, 2026. Claims 1-18 are pending, of which claims 1-4 and 8 are currently rejected. Claims 5-7 and 9-18 remain objected to.
Response to Arguments
The amendment filed March 2nd, 2026 has been entered. Claims 1-18 remain pending in the application. Applicant’s amendments have overcome every objection to the specification and claims, and 112(b) rejection previously set forth in the Non-Final Office Action mailed December 16th, 2025.
Specification Objections
Applicant has amended abstract, and therefore the specification objection as set forth in the Office Action mailed December 16th, 2025 has been withdrawn.
Claim Objections
Applicant has amended claims and therefore claim objections as previously set forth in the Office Action mailed December 16th, 2025 have been withdrawn.
Claim Rejections – 35 USC § 112
Applicant has amended claim 13, no longer invoking 112(f). As such the interpretation under 112(f) has been withdrawn, and accordingly the rejections under 112(a) and 112(b) have also been withdrawn.
Prior Art Rejections
Applicant’s arguments regarding the previously cited art have been fully considered and are not persuasive.
Applicant alleges that Kim (US 2020/0167632) (hereinafter “Kim”) in view of Ho (7346643) (hereinafter “Ho”) does not teach the mantissa alignment circuit receiving first input mantissa data (Applicant Remarks: Pgs. 16-17) and establishes that the shifter i.e., mantissa alignment circuit of Kim receives mantissa data from a multiplier as shown in Fig. 7B of Kim.
Examiner respectfully disagrees. As is shown in Fig. 7B of Kim that Applicant makes reference to, there is a Fb/A (also shown in Fig. 9A Fa) which is a mantissa portion (called fraction bits in this reference) of the input, which is input directly into the shifter 23 i.e., the mantissa alignment circuit, and is explicitly described in Fig. 8B and ¶ 0108 of Kim as a mantissa portion of an input. Therefore, Kim does in fact teach first mantissa data being input to the mantissa alignment circuit.
Applicant alleges that Kim does not teach the “1” search circuit receiving second mantissa data from the mantissa alignment circuit to output shift data (Applicant Remarks: Pgs. 18-19). Examiner respectfully disagrees. Fig. 9A of Kim shows another arrangement of the device that be used and shows the LOD circuit i.e., “1” search circuit that takes R2 from the Shifter and Adder, R2 being a second mantissa data as explained in … and outputting SH2 i.e., shifting data/information. Therefore, Kim does in fact teach the “1” search circuit receiving second mantissa data from the mantissa alignment circuit to output shift data.
Applicant alleges that the generation order and input relationship of the shift data are completely opposite to those of the claimed invention (exponent addition circuit performs an addition operation on shift data and first exponent data, and performs a +1 operation on a result of the addition operation, having shift data being generated based on a leading 1 position of the second mantissa data, which is then used as an input to the exponent addition circuit). Examiner respectfully disagrees. As can be seen in Fig. 9A of Kim, exponent addition circuit being 27 (which carries out a +1 operation), and the addition operation is carried out on first exponent data (exponent, sign data obtained from 22 and leading into 27) as well as shift data SH2 (provided from LOD 25 which detects a leading 1 i.e., “1” search circuit).
Applicant alleges that claim 1 recites the one bit left shift being performed in an initial stage, which is not disclosed by Kim in view of Ho, clarifying that the second mantissa is created from the first mantissa by the one bit shift. However, Examiner points out that this is not claimed. In response to applicant’s argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., one bit left shift being performed at an initial stage) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Although this limitation is included earlier in the claim, no wherein the claim does it positively recite that this one bit left shift is used in order to transform the first mantissa data into a second mantissa data. Instead, what is recited is that the second mantissa data is bit shifted, without clarification of when it does occur. Within BRI, this bit shift can occur at any point in the processing and normalizing. Therefore, Kim in view of Ho does in fact teach claim 1.
See Claim Rejections - 35 USC § 103.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2020/0167632 A1) (hereinafter “Kim”), in view of Ho et al. (US 7346643) (hereinafter “Ho”).
Regarding claim 1, Kim teaches:
A normalizer receiving input data including first exponent data and first mantissa data and generating normalized output data (Kim: ¶ 0042 output is floating point data which is normalized as discussed in ¶ 0130; ¶ 0085 inputs are floating point numbers having an exponent i.e., first exponent data and fraction part i.e., first mantissa data), the normalizer comprising:
a mantissa alignment circuit configured to receive the first mantissa data of the input data and to output second mantissa data (Kim: Fig. 9A elements 23 and 24 as mantissa alignment circuit receiving Fa i.e., first mantissa data and outputting R2 after 24; ¶ 0120 shifting of fraction part of number i.e., mantissa to output second mantissa data; ¶ 0108 shifting based on absolute value of exponent computations);
a “1” search circuit configured to receive the second mantissa data from the mantissa alignment circuit and search for an uppermost bit position of a leading “1” in the second mantissa data to output shift data (Kim: Fig. 9A element 25 LOD as “1” search circuit receiving R2 i.e., second mantissa data from elements 23 and 24; ¶ 0097 searching for leading 1 in order to determine a shifting amount; ¶ 0091 shifting occurs based on leading 1 position);
an exponent addition circuit configured to perform an addition operation on the shift data and the first exponent data and configured to perform a “+1” operation on a result of the addition operation to output addition data (Kim: Fig. 9A element 27 increment and shift circuit, more specifically the incrementing internal circuitry components; ¶ 0127 discusses incrementing of exponent data); and
a normalization circuit configured to perform normalization by outputting the addition data as exponent data of the normalized output data and by outputting result data that is obtained by shifting the second mantissa data by a number of bits that correspond to an absolute value of the shift data as mantissa data of the normalized output data (Kim: ¶ 0130 functionality of 7B which operates same as Fig. 9A as discussed in ¶ 0111 - ¶ 0114 a normalized output is provided from Fig. 9A element 27 i.e., normalizing circuit functionality of circuit specifically shifting internal components of 27 functions similarly to element 23 mantissa shifter, and so shifting occurs with respect to absolute values of exponent computations i.e., shift data).
Kim does not explicitly teach:
a binary point of the second mantissa data being shifted by one bit to the left in comparison to a binary point of the first mantissa data.
However, Ho teaches:
a binary point of the second mantissa data being shifted by one bit to the left in comparison to a binary point of the first mantissa data (Ho: Col. 7 Lines 47-53 right or left 1 bit shift to normalize to 1.xxx… format).
It would be obvious to combine the one bit shift as taught by Ho with the normalizing structure as taught by Kim as both teachings are directed towards normalizing of floating-point operands. One with ordinary skill in the art would be motivated to combine the teachings to further aid in the normalizing to the standard format (Ho: Col. 7 Lines 47-53).
Therefore, Kim in view of Ho teaches:
A normalizer receiving input data including first exponent data and first mantissa data and generating normalized output data, the normalizer comprising:
a mantissa alignment circuit configured to receive the first mantissa data of the input data and to output second mantissa data, a binary point of the second mantissa data being shifted by one bit to the left in comparison to a binary point of the first mantissa data;
a “1” search circuit configured to receive the second mantissa data from the mantissa alignment circuit and search for an uppermost bit position of a leading “1” in the second mantissa data to output shift data;
an exponent addition circuit configured to perform an addition operation on the shift data and the first exponent data and configured to perform a “+1” operation on a result of the addition operation to output addition data; and
a normalization circuit configured to perform normalization by outputting the addition data as exponent data of the normalized output data and by outputting result data that is obtained by shifting the second mantissa data by a number of bits that correspond to an absolute value of the shift data as mantissa data of the normalized output data.
Regarding claim 2, Kim in view of Ho further teaches:
The normalizer of claim 1, wherein the “1” search circuit is configured to output the shift data including the same number of bits as the first exponent data (Ho: Fig. 5A and Fig. 5B the number of bits used to represent the first exponent data as shown in Fig. 5B is equal to the number of bits shown to represent the new exponent data i.e., shift data as shown in Fig. 5A).
The motivation to combine with respect to claim 1 applies equally to claim 2.
Regarding claim 3, while Kim teaches a “1” search circuit searching for an uppermost bit position of the leading “1” in the second mantissa data (Kim: Fig. 9A element 25 LOD; ¶ 0097 searching for leading 1 in order to determine an amount; ¶ 0091 shifting occurs based on leading 1 position), Kim does not explicitly teach a binary data being output in order to have a shifting amount having an end result of the format 1. xxxx.
However, Ho teaches data output, representative of the number of bits to be shifted, is in the form of a control signal i.e., binary data (Ho: Col. 7 Lines 66-67 and Col. 8 Lines 1-3) and normalizing to the format of 1.xxx (Ho: Col. 7 Lines 47-53).
The motivation to combine with respect to claim 1 applies equally to claim 3.
Therefore, Kim in view of Ho teaches:
The normalizer of claim 1, wherein the “1” search circuit is configured to:
search for the uppermost bit position of the leading “1” in the second mantissa data to generate binary data of the number of bits to be shifted so that the second mantissa data has a format of 1.xxx; and
output the binary data or 2’s complement of the binary data as the shift data.
Regarding claim 8, Kim in view of Ho further teaches:
The normalizer of claim 1, wherein the normalization circuit is configured to perform the normalization by performing a shifting operation to shift in a left direction for the second mantissa data (Kim: Fig. 9A shifter 27 accepts shifting information from element 25, Fig 11 further shows that left shifting may be indicated to be carried out in order to have normalized second mantissa data).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Ho, further in view of Ahmed (6301594).
While Kim in view of Ho teaches a “1” search circuit (Kim: Fig. 9A LOD 25 as “1” search circuit; ¶ 0097 searching for leading 1 in order to determine a shifting amount; ¶ 0091 shifting occurs based on leading 1 position) and shifting in the right direction and outputting shifting information as binary data to indicate shifting (Ho: Col. 7 Lines 47-53 normalize to 1.xxx format; Col. 7 Lines 66-67 and Col. 8 Lines 1-3 data output, representative of the number of bits to be shifted, is in the form of a control signal i.e., binary data), Kim in view of Ho does not explicitly teach outputting a 2’s complement of the binary data as shift data when the shifting operation for the second mantissa data shifting is performed in a left direction.
However, Ahmed teaches outputting a 2s complement of shifting data when left shifting is to occur (Ahmed: Col. 5 Lines 1-3 left shift is done by the amount of the early shift count amount; Col. 4 Lines 1-8 the early shift count amount is output as 2s complement).
It would be obvious to combine the 2s complement left shift indication as taught by Ahmed with the normalizer as taught by Kim in view of Ho as all teachings are directed towards normalizing of floating-point operands. One with ordinary skill in the art would be motivated to combine the teachings because doing so would reduce the time required to perform exponent adjustment by minimizing the number of steps needed during computations (Ahmed: Col. 2 Lines 37-39).
Allowable Subject Matter
Claims 5-7 and 9-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 5-7 and 9-18 would be allowable for the same reasons as indicated in the Office Action mailed December 16th, 2025 if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/M.D.R./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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